Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	522990386	2218310	0	0
intr_enable_rd_A	522990386	2311	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522990386	2218310	0	0
T1	105310	173346	0	0
T2	248179	0	0	0
T3	395753	0	0	0
T4	134209	0	0	0
T5	177556	0	0	0
T6	164192	0	0	0
T7	0	41425	0	0
T8	0	81096	0	0
T9	78327	0	0	0
T10	0	492659	0	0
T12	0	194296	0	0
T13	0	33340	0	0
T14	117079	0	0	0
T15	72657	0	0	0
T16	56664	0	0	0
T62	0	115459	0	0
T63	0	43242	0	0
T64	0	32077	0	0
T65	0	62239	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522990386	2311	0	0
T1	105310	134	0	0
T2	248179	0	0	0
T3	395753	0	0	0
T4	134209	0	0	0
T5	177556	0	0	0
T6	164192	0	0	0
T9	78327	0	0	0
T14	117079	0	0	0
T15	72657	0	0	0
T16	56664	0	0	0
T66	0	4	0	0
T67	0	60	0	0
T68	0	17	0	0
T69	0	15	0	0
T70	0	9	0	0
T71	0	39	0	0
T72	0	43	0	0
T73	0	12	0	0
T74	0	14	0	0