Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 43910037 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 41807300 1 T1 29914 T2 125121 T3 4526



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 40767987 1 T1 28754 T2 117822 T3 4647
values[0x0] 21041212 1 T1 13506 T2 609889 T3 1949
values[0x1] 23908138 1 T1 15049 T2 705222 T3 2207



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 33739118 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 51978219 1 T1 36439 T2 154932 T3 5488



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 300441 1 T1 219 T2 9077 T3 93
valid_sources[0x01] 263643 1 T1 253 T2 9543 T3 19
valid_sources[0x02] 294636 1 T1 206 T2 9798 T3 55
valid_sources[0x03] 261591 1 T1 229 T2 9863 T3 18
valid_sources[0x04] 258583 1 T1 185 T2 10277 T3 57
valid_sources[0x05] 264693 1 T1 186 T2 10082 T3 51
valid_sources[0x06] 270183 1 T1 218 T2 9337 T3 11
valid_sources[0x07] 397171 1 T1 268 T2 10111 T3 14
valid_sources[0x08] 257467 1 T1 269 T2 9307 T3 22
valid_sources[0x09] 254662 1 T1 237 T2 9623 T3 31
valid_sources[0x0a] 259102 1 T1 200 T2 9652 T3 13
valid_sources[0x0b] 264285 1 T1 239 T2 9720 T3 40
valid_sources[0x0c] 257464 1 T1 205 T2 9576 T3 21
valid_sources[0x0d] 310680 1 T1 218 T2 10024 T3 7
valid_sources[0x0e] 261564 1 T1 234 T2 9959 T3 78
valid_sources[0x0f] 261791 1 T1 196 T2 9681 T3 72
valid_sources[0x10] 265941 1 T1 218 T2 9894 T3 42
valid_sources[0x11] 310810 1 T1 251 T2 9973 T3 21
valid_sources[0x12] 271360 1 T1 234 T2 9757 T3 47
valid_sources[0x13] 383673 1 T1 229 T2 9611 T3 18
valid_sources[0x14] 272365 1 T1 209 T2 9768 T3 7
valid_sources[0x15] 272415 1 T1 234 T2 9654 T3 11
valid_sources[0x16] 269603 1 T1 215 T2 9961 T3 47
valid_sources[0x17] 266253 1 T1 195 T2 9810 T3 39
valid_sources[0x18] 310048 1 T1 179 T2 9513 T3 46
valid_sources[0x19] 338359 1 T1 212 T2 9653 T3 18
valid_sources[0x1a] 258009 1 T1 244 T2 9730 T3 36
valid_sources[0x1b] 264616 1 T1 232 T2 10191 T3 21
valid_sources[0x1c] 407724 1 T1 252 T2 9881 T3 7
valid_sources[0x1d] 264514 1 T1 248 T2 9629 T3 90
valid_sources[0x1e] 265553 1 T1 228 T2 9437 T3 23
valid_sources[0x1f] 548799 1 T1 284 T2 9764 T3 38
valid_sources[0x20] 615928 1 T1 157 T2 10200 T3 1
valid_sources[0x21] 254047 1 T1 186 T2 9963 T3 56
valid_sources[0x22] 904386 1 T1 228 T2 9638 T3 38
valid_sources[0x23] 256911 1 T1 232 T2 9974 T3 83
valid_sources[0x24] 261731 1 T1 261 T2 9655 T3 23
valid_sources[0x25] 258406 1 T1 224 T2 9639 T3 72
valid_sources[0x26] 326672 1 T1 240 T2 9720 T3 18
valid_sources[0x27] 271484 1 T1 267 T2 9617 T3 12
valid_sources[0x28] 260218 1 T1 296 T2 9495 T3 37
valid_sources[0x29] 292121 1 T1 237 T2 9697 T3 41
valid_sources[0x2a] 311003 1 T1 157 T2 9564 T3 61
valid_sources[0x2b] 329475 1 T1 293 T2 9447 T3 56
valid_sources[0x2c] 255810 1 T1 232 T2 9907 T3 8
valid_sources[0x2d] 314719 1 T1 242 T2 9416 T3 42
valid_sources[0x2e] 270859 1 T1 227 T2 10225 T3 19
valid_sources[0x2f] 259186 1 T1 263 T2 9908 T3 8
valid_sources[0x30] 278936 1 T1 223 T2 10078 T3 44
valid_sources[0x31] 262980 1 T1 222 T2 9933 T3 10
valid_sources[0x32] 623364 1 T1 251 T2 9685 T3 52
valid_sources[0x33] 292087 1 T1 268 T2 9321 T3 27
valid_sources[0x34] 264789 1 T1 258 T2 10029 T3 30
valid_sources[0x35] 266145 1 T1 216 T2 9716 T3 31
valid_sources[0x36] 258632 1 T1 189 T2 9640 T3 29
valid_sources[0x37] 263924 1 T1 281 T2 10164 T3 34
valid_sources[0x38] 257572 1 T1 287 T2 9811 T3 26
valid_sources[0x39] 275189 1 T1 271 T2 9247 T3 39
valid_sources[0x3a] 258833 1 T1 265 T2 9733 T3 19
valid_sources[0x3b] 262213 1 T1 236 T2 9692 T3 13
valid_sources[0x3c] 265161 1 T1 230 T2 9376 T3 17
valid_sources[0x3d] 266969 1 T1 189 T2 9841 T3 59
valid_sources[0x3e] 265490 1 T1 221 T2 9717 T3 25
valid_sources[0x3f] 268755 1 T1 218 T2 9758 T3 25
valid_sources[0x40] 274395 1 T1 242 T2 9878 T3 61
valid_sources[0x41] 344663 1 T1 239 T2 9810 T3 10
valid_sources[0x42] 271805 1 T1 162 T2 10044 T3 30
valid_sources[0x43] 259556 1 T1 245 T2 9579 T3 26
valid_sources[0x44] 277141 1 T1 211 T2 10042 T3 57
valid_sources[0x45] 272243 1 T1 229 T2 9696 T3 39
valid_sources[0x46] 351869 1 T1 234 T2 9707 T3 20
valid_sources[0x47] 318300 1 T1 177 T2 9564 T3 66
valid_sources[0x48] 259185 1 T1 211 T2 10154 T3 12
valid_sources[0x49] 265619 1 T1 191 T2 10160 T3 15
valid_sources[0x4a] 265343 1 T1 236 T2 9633 T3 54
valid_sources[0x4b] 259956 1 T1 185 T2 9419 T3 17
valid_sources[0x4c] 263015 1 T1 228 T2 9493 T3 33
valid_sources[0x4d] 265485 1 T1 192 T2 10179 T3 33
valid_sources[0x4e] 260886 1 T1 217 T2 9657 T3 62
valid_sources[0x4f] 334182 1 T1 250 T2 9798 T3 93
valid_sources[0x50] 272294 1 T1 227 T2 9752 T3 51
valid_sources[0x51] 261985 1 T1 237 T2 10217 T3 11
valid_sources[0x52] 267292 1 T1 195 T2 9590 T3 29
valid_sources[0x53] 348409 1 T1 268 T2 9575 T3 34
valid_sources[0x54] 259498 1 T1 259 T2 9223 T3 47
valid_sources[0x55] 268284 1 T1 200 T2 9960 T3 38
valid_sources[0x56] 630311 1 T1 152 T2 10113 T3 27
valid_sources[0x57] 270380 1 T1 243 T2 9516 T3 23
valid_sources[0x58] 264274 1 T1 230 T2 9977 T3 23
valid_sources[0x59] 257082 1 T1 289 T2 10196 T3 20
valid_sources[0x5a] 267108 1 T1 212 T2 10486 T3 4
valid_sources[0x5b] 263485 1 T1 168 T2 9804 T3 34
valid_sources[0x5c] 1038743 1 T1 239 T2 9766 T3 19
valid_sources[0x5d] 401453 1 T1 210 T2 8872 T3 25
valid_sources[0x5e] 300676 1 T1 244 T2 9673 T3 31
valid_sources[0x5f] 402893 1 T1 255 T2 9832 T3 43
valid_sources[0x60] 295942 1 T1 242 T2 9606 T3 7
valid_sources[0x61] 267049 1 T1 178 T2 9849 T3 15
valid_sources[0x62] 269600 1 T1 217 T2 9478 T3 13
valid_sources[0x63] 259678 1 T1 228 T2 9954 T3 72
valid_sources[0x64] 257376 1 T1 197 T2 9648 T3 12
valid_sources[0x65] 257806 1 T1 237 T2 9762 T3 48
valid_sources[0x66] 257971 1 T1 242 T2 9899 T3 31
valid_sources[0x67] 268000 1 T1 279 T2 10154 T3 39
valid_sources[0x68] 261722 1 T1 224 T2 9907 T3 73
valid_sources[0x69] 762275 1 T1 225 T2 10174 T3 26
valid_sources[0x6a] 267769 1 T1 214 T2 9683 T3 14
valid_sources[0x6b] 266800 1 T1 271 T2 9481 T3 29
valid_sources[0x6c] 269399 1 T1 223 T2 9631 T3 2
valid_sources[0x6d] 262423 1 T1 210 T2 9478 T3 9
valid_sources[0x6e] 400890 1 T1 193 T2 9807 T3 53
valid_sources[0x6f] 257261 1 T1 216 T2 9691 T3 33
valid_sources[0x70] 261318 1 T1 198 T2 9537 T3 5
valid_sources[0x71] 262683 1 T1 235 T2 10011 T3 14
valid_sources[0x72] 261292 1 T1 175 T2 9923 T3 12
valid_sources[0x73] 293320 1 T1 200 T2 9242 T3 65
valid_sources[0x74] 259454 1 T1 170 T2 10235 T3 44
valid_sources[0x75] 262395 1 T1 262 T2 9737 T3 36
valid_sources[0x76] 398031 1 T1 217 T2 9674 T3 15
valid_sources[0x77] 308086 1 T1 272 T2 9708 T3 44
valid_sources[0x78] 269204 1 T1 219 T2 9690 T3 51
valid_sources[0x79] 261223 1 T1 209 T2 9486 T3 12
valid_sources[0x7a] 260923 1 T1 245 T2 10143 T3 68
valid_sources[0x7b] 262876 1 T1 222 T2 9806 T3 55
valid_sources[0x7c] 271831 1 T1 181 T2 9587 T3 8
valid_sources[0x7d] 260552 1 T1 215 T2 9502 T3 36
valid_sources[0x7e] 276575 1 T1 268 T2 10012 T3 37
valid_sources[0x7f] 259483 1 T1 216 T2 10043 T3 54
valid_sources[0x80] 264449 1 T1 229 T2 9080 T3 35



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20169887 1 T1 14188 T2 584385 T3 2209
values[0x0] all_enables biggest_size 11642182 1 T1 8279 T2 355833 T3 1185
values[0x1] all_enables biggest_size 9995231 1 T1 7447 T2 310997 T3 1132

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%