Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48143718

1

T1

27395

T2

162524

T3

4277

full_word

42081516

1

T1

29914

T2

127565

T3

4526

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90224854	1			T1	57309		T2	290090		T3	8803
auto[TlIntgErrCmd]	130	1			T60	5		T61	12		T62	6
auto[TlIntgErrData]	108	1			T60	9		T61	3		T62	4
auto[TlIntgErrBoth]	142	1			T60	16		T61	15		T62	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42188502

1

T1

28754

T2

130487

T3

4647

auto[1]

48036732

1

T1

28555

T2

159602

T3

4156

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21910274	1			T1	14566		T2	710979		T3	2438
auto[TlIntgErrNone]	partial	auto[1]	26233087	1			T1	12829		T2	914263		T3	1839
auto[TlIntgErrNone]	full_word	auto[0]	20278049	1			T1	14188		T2	593894		T3	2209
auto[TlIntgErrNone]	full_word	auto[1]	21803444	1			T1	15726		T2	681765		T3	2317
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T61	5		T62	3		T122	5
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T60	5		T61	7		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T62	1		T123	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T125	1		T126	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T60	7		T61	1		T122	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T60	2		T61	1		T62	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T123	1		T120	1		T127	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T61	1		T123	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T60	4		T61	6		T62	5
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T60	10		T61	9		T62	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T60	1		T128	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T60	1		T62	1		T129	1