Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	495370910	2419332	0	0
intr_enable_rd_A	495370910	3092	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495370910	2419332	0	0
T2	641530	224233	0	0
T3	85361	0	0	0
T4	71098	0	0	0
T5	488342	0	0	0
T6	0	159895	0	0
T7	0	19013	0	0
T8	421607	0	0	0
T11	0	27314	0	0
T12	0	265186	0	0
T13	0	56719	0	0
T14	714	0	0	0
T15	1005	0	0	0
T16	64460	0	0	0
T17	19293	0	0	0
T20	0	238275	0	0
T23	119974	0	0	0
T64	0	32817	0	0
T65	0	159521	0	0
T66	0	313298	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495370910	3092	0	0
T7	588836	0	0	0
T11	0	131	0	0
T12	0	208	0	0
T67	81298	30	0	0
T68	392853	19	0	0
T69	0	23	0	0
T70	0	16	0	0
T71	0	16	0	0
T72	0	4	0	0
T73	0	13	0	0
T74	0	22	0	0
T75	286974	0	0	0
T76	83682	0	0	0
T77	106461	0	0	0
T78	22130	0	0	0
T79	190504	0	0	0
T80	828827	0	0	0
T81	540439	0	0	0