Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48643930

1

T1

49560

T2

933

T3

92652

full_word

43054159

1

T1

39800

T2

953

T3

72354

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91697679	1			T1	89360		T2	1886		T3	165006
auto[TlIntgErrCmd]	142	1			T57	3		T58	3		T59	13
auto[TlIntgErrData]	116	1			T57	3		T58	3		T59	6
auto[TlIntgErrBoth]	152	1			T57	4		T58	4		T59	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43028327

1

T1

44904

T2

963

T3

82841

auto[1]

48669762

1

T1

44456

T2

923

T3

82165

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22220748	1			T1	22415		T2	494		T3	41625
auto[TlIntgErrNone]	partial	auto[1]	26422809	1			T1	27145		T2	439		T3	51027
auto[TlIntgErrNone]	full_word	auto[0]	20807398	1			T1	22489		T2	469		T3	41216
auto[TlIntgErrNone]	full_word	auto[1]	22246724	1			T1	17311		T2	484		T3	31138
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T57	1		T58	1		T59	8
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T57	2		T58	2		T59	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T123	1		T120	2		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T123	2		T118	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T57	2		T59	4		T123	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T57	1		T58	3		T59	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T123	1		T124	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T120	1		T121	2		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T57	2		T59	6		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T57	2		T58	4		T59	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T126	1		T127	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T123	1		T120	1		T122	2