Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40358107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38548112

1

T1

361442

T2

25647

T3

392300

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37497601	1			T1	359149		T2	28799		T3	370588
values[0x0]	19376557	1			T1	181810		T2	13110		T3	196167
values[0x1]	22032061	1			T1	207480		T2	15380		T3	220784

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31034451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47871768

1

T1

447944

T2

32875

T3

480726

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	303982	1			T1	3078		T3	2947		T4	342
valid_sources[0x01]	249452	1			T1	2935		T3	2754		T4	437
valid_sources[0x02]	271570	1			T1	2846		T3	2962		T4	354
valid_sources[0x03]	250190	1			T1	2904		T3	2803		T4	436
valid_sources[0x04]	257002	1			T1	2918		T3	3010		T4	465
valid_sources[0x05]	298981	1			T1	2753		T3	2866		T4	462
valid_sources[0x06]	261501	1			T1	2875		T3	2772		T4	503
valid_sources[0x07]	718192	1			T1	2838		T3	3262		T4	581
valid_sources[0x08]	246985	1			T1	2945		T3	3438		T4	307
valid_sources[0x09]	261139	1			T1	2803		T3	3276		T4	444
valid_sources[0x0a]	565710	1			T1	2919		T3	3283		T4	359
valid_sources[0x0b]	246102	1			T1	2821		T3	2920		T4	416
valid_sources[0x0c]	425243	1			T1	2927		T3	2848		T4	527
valid_sources[0x0d]	254399	1			T1	2987		T3	2957		T4	453
valid_sources[0x0e]	252603	1			T1	2712		T3	3063		T4	326
valid_sources[0x0f]	354300	1			T1	2739		T3	3436		T4	442
valid_sources[0x10]	268182	1			T1	2882		T3	3076		T4	532
valid_sources[0x11]	248877	1			T1	3063		T3	2767		T4	373
valid_sources[0x12]	249479	1			T1	2905		T3	2968		T4	367
valid_sources[0x13]	262716	1			T1	2718		T3	2994		T4	411
valid_sources[0x14]	247868	1			T1	2926		T2	1		T3	3013
valid_sources[0x15]	250195	1			T1	3112		T3	2610		T4	663
valid_sources[0x16]	279696	1			T1	3165		T3	3678		T4	361
valid_sources[0x17]	255911	1			T1	2910		T3	3670		T4	321
valid_sources[0x18]	249229	1			T1	2852		T3	2997		T4	486
valid_sources[0x19]	261346	1			T1	2885		T3	3293		T4	395
valid_sources[0x1a]	256718	1			T1	2848		T3	2985		T4	448
valid_sources[0x1b]	246460	1			T1	2876		T3	3374		T4	476
valid_sources[0x1c]	928861	1			T1	2879		T3	3520		T4	409
valid_sources[0x1d]	255426	1			T1	2953		T3	2745		T4	343
valid_sources[0x1e]	248016	1			T1	2870		T3	3022		T4	406
valid_sources[0x1f]	250589	1			T1	3035		T3	3113		T4	392
valid_sources[0x20]	261146	1			T1	2809		T3	3311		T4	434
valid_sources[0x21]	247945	1			T1	2820		T3	2949		T4	362
valid_sources[0x22]	254252	1			T1	2889		T3	3333		T4	556
valid_sources[0x23]	256998	1			T1	2787		T3	3103		T4	510
valid_sources[0x24]	277048	1			T1	3052		T2	1		T3	2966
valid_sources[0x25]	347926	1			T1	3047		T3	3433		T4	448
valid_sources[0x26]	264982	1			T1	2876		T3	3206		T4	486
valid_sources[0x27]	253387	1			T1	3050		T3	2862		T4	401
valid_sources[0x28]	295175	1			T1	2854		T3	2562		T4	282
valid_sources[0x29]	249579	1			T1	3102		T3	3106		T4	502
valid_sources[0x2a]	745876	1			T1	2861		T3	3174		T4	322
valid_sources[0x2b]	259265	1			T1	2979		T3	2543		T4	306
valid_sources[0x2c]	247628	1			T1	2860		T3	3366		T4	423
valid_sources[0x2d]	249502	1			T1	2916		T3	2807		T4	529
valid_sources[0x2e]	248637	1			T1	2973		T3	2979		T4	476
valid_sources[0x2f]	819076	1			T1	2826		T3	3202		T4	455
valid_sources[0x30]	245512	1			T1	2902		T3	2822		T4	390
valid_sources[0x31]	257425	1			T1	2948		T3	3071		T4	391
valid_sources[0x32]	245929	1			T1	3011		T3	2747		T4	510
valid_sources[0x33]	250346	1			T1	2990		T3	3059		T4	472
valid_sources[0x34]	251836	1			T1	2792		T3	2875		T4	349
valid_sources[0x35]	247150	1			T1	2998		T3	2521		T4	387
valid_sources[0x36]	255665	1			T1	2860		T3	3017		T4	394
valid_sources[0x37]	715939	1			T1	3090		T3	2261		T4	352
valid_sources[0x38]	339731	1			T1	3101		T3	3512		T4	410
valid_sources[0x39]	252284	1			T1	2937		T3	3480		T4	331
valid_sources[0x3a]	256277	1			T1	3127		T3	3482		T4	382
valid_sources[0x3b]	269166	1			T1	2804		T3	3060		T4	454
valid_sources[0x3c]	259091	1			T1	2843		T3	3162		T4	441
valid_sources[0x3d]	294905	1			T1	2891		T3	2738		T4	401
valid_sources[0x3e]	252130	1			T1	3006		T3	2642		T4	427
valid_sources[0x3f]	243559	1			T1	2771		T3	2957		T4	407
valid_sources[0x40]	265073	1			T1	2793		T3	3014		T4	477
valid_sources[0x41]	260210	1			T1	3057		T3	2862		T4	393
valid_sources[0x42]	250959	1			T1	3035		T3	2954		T4	427
valid_sources[0x43]	258265	1			T1	2921		T3	3450		T4	413
valid_sources[0x44]	272963	1			T1	2856		T3	3156		T4	444
valid_sources[0x45]	287618	1			T1	3038		T3	3262		T4	522
valid_sources[0x46]	275122	1			T1	3032		T2	1		T3	2774
valid_sources[0x47]	258063	1			T1	3057		T3	2577		T4	461
valid_sources[0x48]	258595	1			T1	2954		T3	3263		T4	517
valid_sources[0x49]	290020	1			T1	2980		T3	3636		T4	351
valid_sources[0x4a]	259407	1			T1	2970		T3	2840		T4	375
valid_sources[0x4b]	311204	1			T1	2995		T3	2636		T4	411
valid_sources[0x4c]	420039	1			T1	3047		T2	27877		T3	3025
valid_sources[0x4d]	252761	1			T1	3050		T3	2542		T4	492
valid_sources[0x4e]	275688	1			T1	2812		T3	2957		T4	491
valid_sources[0x4f]	249309	1			T1	2880		T3	2648		T4	346
valid_sources[0x50]	247875	1			T1	2981		T3	2532		T4	448
valid_sources[0x51]	251154	1			T1	2811		T3	2680		T4	474
valid_sources[0x52]	253244	1			T1	3063		T3	2684		T4	408
valid_sources[0x53]	248408	1			T1	3019		T3	2552		T4	441
valid_sources[0x54]	253609	1			T1	2826		T3	3089		T4	487
valid_sources[0x55]	256872	1			T1	2827		T3	2773		T4	286
valid_sources[0x56]	250547	1			T1	2792		T3	2915		T4	359
valid_sources[0x57]	262413	1			T1	3087		T3	3409		T4	324
valid_sources[0x58]	249240	1			T1	3089		T3	3753		T4	523
valid_sources[0x59]	337427	1			T1	2852		T3	3079		T4	360
valid_sources[0x5a]	289096	1			T1	2893		T3	2898		T4	398
valid_sources[0x5b]	369972	1			T1	2921		T3	3218		T4	476
valid_sources[0x5c]	269967	1			T1	3102		T3	2887		T4	354
valid_sources[0x5d]	246918	1			T1	2862		T3	2612		T4	459
valid_sources[0x5e]	245794	1			T1	2928		T3	3034		T4	401
valid_sources[0x5f]	247939	1			T1	2872		T3	3079		T4	434
valid_sources[0x60]	251758	1			T1	2824		T3	2579		T4	409
valid_sources[0x61]	2221769	1			T1	2905		T3	2691		T4	575
valid_sources[0x62]	249406	1			T1	2745		T3	3142		T4	519
valid_sources[0x63]	256013	1			T1	2939		T3	3399		T4	466
valid_sources[0x64]	303129	1			T1	3011		T3	2922		T4	518
valid_sources[0x65]	251816	1			T1	2854		T3	3704		T4	425
valid_sources[0x66]	247270	1			T1	3079		T3	3355		T4	359
valid_sources[0x67]	367211	1			T1	2865		T3	2897		T4	455
valid_sources[0x68]	248955	1			T1	2936		T3	3228		T4	475
valid_sources[0x69]	250494	1			T1	2932		T3	3356		T4	488
valid_sources[0x6a]	245695	1			T1	2968		T3	3232		T4	291
valid_sources[0x6b]	314685	1			T1	3034		T3	3237		T4	471
valid_sources[0x6c]	301651	1			T1	2936		T3	3123		T4	378
valid_sources[0x6d]	252340	1			T1	2964		T3	2982		T4	315
valid_sources[0x6e]	251209	1			T1	3038		T3	3112		T4	426
valid_sources[0x6f]	247512	1			T1	2911		T3	2873		T4	479
valid_sources[0x70]	329277	1			T1	2991		T3	3018		T4	464
valid_sources[0x71]	271741	1			T1	3040		T3	3149		T4	496
valid_sources[0x72]	267081	1			T1	2938		T3	3029		T4	440
valid_sources[0x73]	261169	1			T1	2833		T3	3080		T4	460
valid_sources[0x74]	260739	1			T1	2984		T3	3338		T4	456
valid_sources[0x75]	251344	1			T1	2826		T3	2651		T4	478
valid_sources[0x76]	252169	1			T1	2895		T3	3404		T4	409
valid_sources[0x77]	264603	1			T1	3070		T3	3162		T4	477
valid_sources[0x78]	270015	1			T1	2835		T3	2868		T4	502
valid_sources[0x79]	293962	1			T1	3017		T3	2857		T4	423
valid_sources[0x7a]	252229	1			T1	2976		T3	3270		T4	356
valid_sources[0x7b]	256014	1			T1	2775		T3	2844		T4	421
valid_sources[0x7c]	255431	1			T1	2976		T3	2852		T4	353
valid_sources[0x7d]	260270	1			T1	3106		T3	2936		T4	453
valid_sources[0x7e]	259972	1			T1	2751		T3	3268		T4	507
valid_sources[0x7f]	251250	1			T1	2852		T3	3128		T4	403
valid_sources[0x80]	918856	1			T1	2979		T3	2863		T4	380

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18575723

1

T1

178999

T2

14345

T3

183965

values[0x0]

all_enables

biggest_size

10740978

1

T1

98308

T2

6260

T3

111640

values[0x1]

all_enables

biggest_size

9231411

1

T1

84135

T2

5042

T3

96695