Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44189219

1

T1

386997

T2

31642

T3

395239

full_word

38796763

1

T1

361442

T2

25647

T3

392300

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82985452	1			T1	748439		T2	57289		T3	787539
auto[TlIntgErrCmd]	166	1			T51	14		T52	11		T53	5
auto[TlIntgErrData]	178	1			T51	11		T52	12		T53	11
auto[TlIntgErrBoth]	186	1			T51	5		T52	7		T53	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38775418

1

T1

359149

T2

28799

T3

370588

auto[1]

44210564

1

T1

389290

T2

28490

T3

416951

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20102262	1			T1	180150		T2	14454		T3	186623
auto[TlIntgErrNone]	partial	auto[1]	24086463	1			T1	206847		T2	17188		T3	208616
auto[TlIntgErrNone]	full_word	auto[0]	18672913	1			T1	178999		T2	14345		T3	183965
auto[TlIntgErrNone]	full_word	auto[1]	20123814	1			T1	182443		T2	11302		T3	208335
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T51	7		T52	7		T53	2
auto[TlIntgErrCmd]	partial	auto[1]	94	1			T51	7		T52	4		T53	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T120	1		T119	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T53	1		T116	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	90	1			T51	7		T52	7		T53	6
auto[TlIntgErrData]	partial	auto[1]	82	1			T51	3		T52	5		T53	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T53	1		T119	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T51	1		T121	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	74	1			T51	4		T52	5		T53	1
auto[TlIntgErrBoth]	partial	auto[1]	94	1			T51	1		T52	2		T53	9
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T53	2		T117	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T53	2		T120	1		T119	1