Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	489117631	2213652	0	0
intr_enable_rd_A	489117631	4182	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489117631	2213652	0	0
T8	468837	73216	0	0
T9	0	121023	0	0
T10	0	170395	0	0
T12	0	98576	0	0
T14	0	388746	0	0
T34	0	219053	0	0
T54	0	52038	0	0
T55	0	156364	0	0
T56	0	67966	0	0
T57	0	67582	0	0
T58	940	0	0	0
T59	50587	0	0	0
T60	150123	0	0	0
T61	533809	0	0	0
T62	45165	0	0	0
T63	108873	0	0	0
T64	34456	0	0	0
T65	633130	0	0	0
T66	461453	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489117631	4182	0	0
T1	684684	1	0	0
T2	605439	0	0	0
T3	830830	0	0	0
T4	114523	0	0	0
T5	440637	0	0	0
T8	0	112	0	0
T9	0	90	0	0
T14	0	167	0	0
T15	167992	0	0	0
T16	694792	0	0	0
T17	1315	0	0	0
T18	39848	0	0	0
T19	123490	0	0	0
T67	0	62	0	0
T68	0	17	0	0
T69	0	55	0	0
T70	0	25	0	0
T71	0	59	0	0
T72	0	81	0	0