Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17809585	1			T1	13439		T2	16147		T3	22160
all_values[1]	17809585	1			T1	13439		T2	16147		T3	22160
all_values[2]	17809585	1			T1	13439		T2	16147		T3	22160

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265091

1

T2

716

T3

403

T18

17

auto[1]

53163664

1

T1

40317

T2

47725

T3

66077

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45472713

1

T1

34438

T2

37440

T3

55765

auto[1]

7956042

1

T1

5879

T2

11001

T3

10715

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90645	1			T18	2		T7	8		T25	564
all_values[0]	auto[0]	auto[1]	374	1			T18	2		T25	2		T27	2
all_values[0]	auto[1]	auto[0]	17699000	1			T1	13434		T2	16142		T3	22146
all_values[0]	auto[1]	auto[1]	19566	1			T1	5		T2	5		T3	14
all_values[1]	auto[0]	auto[0]	104469	1			T2	716		T3	2		T18	4
all_values[1]	auto[0]	auto[1]	264	1			T18	3		T25	3		T29	3
all_values[1]	auto[1]	auto[0]	17704545	1			T1	13439		T2	15431		T3	22158
all_values[1]	auto[1]	auto[1]	307	1			T18	1		T25	4		T29	1
all_values[2]	auto[0]	auto[0]	27597	1			T3	98		T18	4		T5	501
all_values[2]	auto[0]	auto[1]	41742	1			T3	303		T18	2		T5	1505
all_values[2]	auto[1]	auto[0]	9846457	1			T1	7565		T2	5151		T3	11361
all_values[2]	auto[1]	auto[1]	7893789	1			T1	5874		T2	10996		T3	10398