Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123132

1

T2

22

T3

28

T6

16

auto[1]

135458

1

T1

20

T2

12

T3

14

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	99414	1			T1	3		T2	11		T3	16
len_1026_2046	6228	1			T6	2		T4	1		T19	1
len_514_1022	3718	1			T7	4		T19	54		T25	33
len_2_510	4118	1			T3	1		T19	61		T25	47
len_2056	164	1			T27	2		T29	2		T96	1
len_2048	355	1			T3	1		T25	1		T96	7
len_2040	154	1			T27	2		T67	4		T146	2
len_1032	156	1			T27	1		T29	2		T88	2
len_1024	1813	1			T19	2		T5	1		T25	3
len_1016	199	1			T25	4		T27	2		T29	1
len_520	263	1			T19	1		T27	1		T95	1
len_512	354	1			T19	2		T31	1		T25	1
len_504	194	1			T19	2		T27	7		T96	1
len_8	1349	1			T1	6		T4	6		T5	8
len_0	10816	1			T1	1		T2	6		T3	3

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

124

1

T25

1

T28

1

T30

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	48449	1			T2	8		T3	11		T6	5
auto[0]	len_1026_2046	2610	1			T19	1		T31	3		T25	30
auto[0]	len_514_1022	1988	1			T19	54		T25	17		T27	2
auto[0]	len_2_510	2475	1			T19	61		T25	24		T27	3
auto[0]	len_2056	84	1			T27	2		T96	1		T67	4
auto[0]	len_2048	195	1			T25	1		T96	4		T147	1
auto[0]	len_2040	76	1			T27	2		T67	4		T146	2
auto[0]	len_1032	87	1			T27	1		T29	2		T67	3
auto[0]	len_1024	261	1			T19	2		T25	3		T27	2
auto[0]	len_1016	113	1			T25	3		T27	2		T29	1
auto[0]	len_520	158	1			T19	1		T67	9		T146	1
auto[0]	len_512	210	1			T19	2		T25	1		T30	1
auto[0]	len_504	120	1			T19	2		T27	2		T96	1
auto[0]	len_8	111	1			T48	1		T9	35		T148	1
auto[0]	len_0	4629	1			T2	3		T3	3		T6	3
auto[1]	len_2050_plus	50965	1			T1	3		T2	3		T3	5
auto[1]	len_1026_2046	3618	1			T6	2		T4	1		T31	2
auto[1]	len_514_1022	1730	1			T7	4		T25	16		T29	53
auto[1]	len_2_510	1643	1			T3	1		T25	23		T27	4
auto[1]	len_2056	80	1			T29	2		T149	2		T67	1
auto[1]	len_2048	160	1			T3	1		T96	3		T88	2
auto[1]	len_2040	78	1			T8	5		T89	1		T9	3
auto[1]	len_1032	69	1			T88	2		T42	1		T150	2
auto[1]	len_1024	1552	1			T5	1		T27	5		T47	1
auto[1]	len_1016	86	1			T25	1		T132	1		T67	3
auto[1]	len_520	105	1			T27	1		T95	1		T67	3
auto[1]	len_512	144	1			T31	1		T29	1		T147	3
auto[1]	len_504	74	1			T27	5		T67	2		T146	1
auto[1]	len_8	1238	1			T1	6		T4	6		T5	8
auto[1]	len_0	6187	1			T1	1		T2	3		T6	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

66

1

T28

1

T30

1

T20

1

auto[1]

len_upper

58

1

T25

1

T56

1

T69

2