Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4384429

1

T1

2102

T2

2506

T3

4968

auto[1]

2802587

1

T1

4661

T2

1521

T3

6003

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2710443

1

T1

5463

T2

948

T3

5330

auto[1]

4476573

1

T1

1300

T2

3079

T3

5641

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3227595

1

T2

2253

T3

8512

T6

1582

auto[1]

3959421

1

T1

6763

T2

1774

T3

2459

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4532475

1

T1

4984

T2

2820

T3

6717

auto[1]

2654541

1

T1

1779

T2

1207

T3

4254

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6492856	1			T1	5903		T2	4006		T3	9744
fifo_depth[1]	113548	1			T1	165		T2	16		T3	208
fifo_depth[2]	84737	1			T1	133		T2	4		T3	219
fifo_depth[3]	67411	1			T1	146		T2	1		T3	211
fifo_depth[4]	61815	1			T1	130		T3	186		T6	2
fifo_depth[5]	49973	1			T1	109		T3	174		T4	186
fifo_depth[6]	40534	1			T1	79		T3	113		T4	144
fifo_depth[7]	27204	1			T1	54		T3	65		T4	91

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694160

1

T1

860

T2

21

T3

1227

auto[1]

6492856

1

T1

5903

T2

4006

T3

9744

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7174240

1

T1

6763

T2

4027

T3

10971

auto[1]

12776

1

T29

73

T30

113

T67

68

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

36839

1

T3

221

T31

7

T25

119

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25937

1

T6

20

T31

7

T25

208

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32654

1

T2

13

T3

76

T31

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

32832

1

T3

346

T6

26

T25

141

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

121361

1

T19

3680

T25

36

T47

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30696

1

T3

496

T6

2

T25

89

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35335

1

T7

76

T25

199

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35732

1

T2

8

T31

1

T25

38

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45081

1

T1

334

T7

8

T5

692

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

41739

1

T3

4

T6

3

T4

965

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38588

1

T1

37

T5

1036

T25

183

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

39868

1

T3

84

T6

17

T31

19

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48320

1

T4

415

T5

271

T25

185

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

41448

1

T25

52

T27

1

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43862

1

T1

489

T6

16

T4

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43868

1

T6

21

T7

170

T5

864

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

154667

1

T3

384

T6

310

T7

365

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

151176

1

T2

2

T6

290

T31

300

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

174187

1

T2

530

T3

1205

T6

429

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

153192

1

T2

171

T3

648

T6

306

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1716296

1

T2

1039

T3

2426

T19

143813

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

163707

1

T2

1

T3

1014

T6

198

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

186383

1

T3

1696

T7

313

T25

3805

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

176601

1

T2

489

T6

1

T31

532

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

456247

1

T1

1111

T2

1

T3

407

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

414865

1

T1

656

T2

229

T3

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

470445

1

T1

2203

T2

1

T3

295

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

442126

1

T1

1122

T2

1

T3

1651

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

507393

1

T2

1234

T3

7

T4

758

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

428657

1

T1

1

T6

22

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

464817

1

T1

810

T2

2

T6

1265

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

432097

1

T2

306

T3

2

T6

394

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

189873

1

T3

605

T6

310

T7

365

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

176322

1

T2

2

T6

310

T31

307

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

205876

1

T2

543

T3

1281

T6

429

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

184409

1

T2

171

T3

994

T6

332

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1837024

1

T2

1039

T3

2426

T19

147493

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

193963

1

T2

1

T3

1510

T6

200

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

220884

1

T3

1696

T7

389

T25

4004

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

211397

1

T2

497

T6

1

T31

533

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

500996

1

T1

1445

T2

1

T3

407

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

455894

1

T1

656

T2

229

T3

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

508941

1

T1

2240

T2

1

T3

295

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

481805

1

T1

1122

T2

1

T3

1735

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

554909

1

T2

1234

T3

7

T4

1173

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

468520

1

T1

1

T6

22

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

508371

1

T1

1299

T2

2

T6

1281

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

475056

1

T2

306

T3

2

T6

415

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1633

1

T30

5

T135

2

T155

84

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

791

1

T30

46

T135

19

T40

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

965

1

T135

2

T155

50

T39

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1615

1

T29

4

T30

60

T39

106

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

633

1

T155

6

T39

20

T40

38

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

440

1

T29

33

T135

8

T155

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

834

1

T39

29

T156

8

T157

45

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

936

1

T135

5

T39

47

T156

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

332

1

T29

4

T135

10

T157

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

710

1

T29

32

T67

54

T135

20

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

92

1

T156

12

T157

8

T158

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

189

1

T39

9

T159

82

T160

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

804

1

T39

26

T40

1

T156

42

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1585

1

T30

1

T156

30

T157

206

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

308

1

T67

14

T155

5

T39

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

909

1

T30

1

T135

79

T40

420

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

154667

1

T3

384

T6

310

T7

365

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

151176

1

T2

2

T6

290

T31

300

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

174187

1

T2

530

T3

1205

T6

429

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

153192

1

T2

171

T3

648

T6

306

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1716296

1

T2

1039

T3

2426

T19

143813

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

163707

1

T2

1

T3

1014

T6

198

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

186383

1

T3

1696

T7

313

T25

3805

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

176601

1

T2

489

T6

1

T31

532

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

456247

1

T1

1111

T2

1

T3

407

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

414865

1

T1

656

T2

229

T3

9

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

470445

1

T1

2203

T2

1

T3

295

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

442126

1

T1

1122

T2

1

T3

1651

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

507393

1

T2

1234

T3

7

T4

758

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

428657

1

T1

1

T6

22

T4

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

464817

1

T1

810

T2

2

T6

1265

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

432097

1

T2

306

T3

2

T6

394

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3628

1

T3

37

T31

5

T25

53

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2806

1

T6

13

T31

7

T25

64

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3550

1

T2

8

T3

10

T31

10

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3204

1

T3

60

T6

14

T25

69

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

38247

1

T19

2697

T25

20

T49

19

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3335

1

T3

93

T6

1

T25

44

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4310

1

T7

9

T25

114

T27

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3339

1

T2

8

T31

1

T25

33

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6570

1

T1

56

T5

115

T25

28

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5353

1

T6

2

T4

145

T25

4

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6367

1

T1

8

T5

146

T25

116

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6479

1

T3

8

T6

10

T31

14

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8060

1

T4

80

T5

46

T25

107

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5568

1

T25

32

T48

5

T49

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6876

1

T1

101

T6

6

T4

4

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5856

1

T6

13

T7

19

T5

126

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134

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21

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9

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51

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1

T3

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75

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60

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69

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1

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7

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87

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4

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13

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5

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1

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3

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57

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32