Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17809585	1			T1	13439		T2	16147		T3	22160
all_pins[1]	17809585	1			T1	13439		T2	16147		T3	22160
all_pins[2]	17809585	1			T1	13439		T2	16147		T3	22160

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45514249	1			T1	34438		T2	37440		T3	56066
values[0x1]	7914506	1			T1	5879		T2	11001		T3	10414
transitions[0x0=>0x1]	7914337	1			T1	5879		T2	11001		T3	10414
transitions[0x1=>0x0]	7914354	1			T1	5879		T2	11001		T3	10414

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17789197	1			T1	13434		T2	16142		T3	22144
all_pins[0]	values[0x1]	20388	1			T1	5		T2	5		T3	16
all_pins[0]	transitions[0x0=>0x1]	20311	1			T1	5		T2	5		T3	16
all_pins[0]	transitions[0x1=>0x0]	7893729	1			T1	5874		T2	10996		T3	10398
all_pins[1]	values[0x0]	17809256	1			T1	13439		T2	16147		T3	22160
all_pins[1]	values[0x1]	329	1			T18	1		T25	4		T29	2
all_pins[1]	transitions[0x0=>0x1]	289	1			T18	1		T25	2		T29	2
all_pins[1]	transitions[0x1=>0x0]	20348	1			T1	5		T2	5		T3	16
all_pins[2]	values[0x0]	9915796	1			T1	7565		T2	5151		T3	11762
all_pins[2]	values[0x1]	7893789	1			T1	5874		T2	10996		T3	10398
all_pins[2]	transitions[0x0=>0x1]	7893737	1			T1	5874		T2	10996		T3	10398
all_pins[2]	transitions[0x1=>0x0]	277	1			T25	2		T29	2		T67	6