Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1034 1 T18 10 T25 17 T29 4
all_values[1] 1034 1 T18 10 T25 17 T29 4
all_values[2] 1034 1 T18 10 T25 17 T29 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1584 1 T18 17 T25 20 T29 6
auto[1] 1518 1 T18 13 T25 31 T29 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1070 1 T18 16 T25 10 T29 4
auto[1] 2032 1 T18 14 T25 41 T29 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1754 1 T18 18 T25 27 T29 7
auto[1] 1348 1 T18 12 T25 24 T29 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 204 1 T18 2 T58 1 T88 4
all_values[0] auto[0] auto[0] auto[1] 103 1 T25 2 T58 1 T67 4
all_values[0] auto[0] auto[1] auto[0] 198 1 T18 4 T25 1 T29 2
all_values[0] auto[0] auto[1] auto[1] 97 1 T25 4 T29 1 T58 1
all_values[0] auto[1] auto[0] auto[1] 225 1 T18 3 T25 3 T58 1
all_values[0] auto[1] auto[1] auto[1] 207 1 T18 1 T25 7 T29 1
all_values[1] auto[0] auto[0] auto[0] 159 1 T18 2 T25 1 T58 2
all_values[1] auto[0] auto[0] auto[1] 146 1 T18 1 T25 3 T29 1
all_values[1] auto[0] auto[1] auto[0] 134 1 T18 3 T25 3 T67 9
all_values[1] auto[0] auto[1] auto[1] 123 1 T25 3 T88 1 T67 4
all_values[1] auto[1] auto[0] auto[1] 247 1 T18 3 T25 3 T29 3
all_values[1] auto[1] auto[1] auto[1] 225 1 T18 1 T25 4 T58 1
all_values[2] auto[0] auto[0] auto[0] 188 1 T18 2 T25 4 T88 4
all_values[2] auto[0] auto[0] auto[1] 107 1 T18 1 T25 2 T29 1
all_values[2] auto[0] auto[1] auto[0] 187 1 T18 3 T25 1 T29 2
all_values[2] auto[0] auto[1] auto[1] 108 1 T25 3 T67 10 T8 6
all_values[2] auto[1] auto[0] auto[1] 205 1 T18 3 T25 2 T29 1
all_values[2] auto[1] auto[1] auto[1] 239 1 T18 1 T25 5 T58 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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