Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4402	1			T1	2		T2	4		T3	8
sha2_none	4323	1			T1	6		T2	3		T3	9
sha2_512	7682	1			T1	2		T2	4		T3	4
sha2_384	7383	1			T1	1		T2	2		T3	3
sha2_256	6133	1			T1	3		T2	5		T3	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18725

1

T1

3

T2

9

T3

17

auto[1]

11588

1

T1

11

T2

10

T3

16

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11432

1

T1

11

T2

10

T3

19

auto[1]

18881

1

T1

3

T2

9

T3

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15824

1

T1

14

T2

7

T3

10

disabled

14489

1

T2

12

T3

23

T6

7

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4834	1			T1	3		T2	8		T3	7
key_none	7600	1			T1	1		T2	1		T3	7
key_1024	4370	1			T1	2		T2	2		T3	6
key_512	3754	1			T1	2		T2	2		T3	4
key_384	3464	1			T1	1		T2	1		T3	4
key_256	3207	1			T1	3		T2	3		T3	3
key_128	3005	1			T1	2		T2	2		T3	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19075

1

T1

8

T2

10

T3

20

auto[1]

11238

1

T1

6

T2

9

T3

13

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30132

1

T1

14

T2

18

T3

33

disabled

181

1

T2

1

T25

1

T48

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1655

1

T1

1

T2

1

T3

1

enabled

auto[0]

auto[0]

auto[1]

1639

1

T1

1

T2

1

T3

2

enabled

auto[0]

auto[1]

auto[0]

1643

1

T1

5

T2

1

T3

1

enabled

auto[0]

auto[1]

auto[1]

1623

1

T1

4

T2

1

T3

4

enabled

auto[1]

auto[0]

auto[0]

4325

1

T2

1

T3

1

T4

2

enabled

auto[1]

auto[0]

auto[1]

1604

1

T1

1

T6

1

T4

1

enabled

auto[1]

auto[1]

auto[0]

1750

1

T1

2

T6

4

T4

4

enabled

auto[1]

auto[1]

auto[1]

1585

1

T2

2

T3

1

T6

1

disabled

auto[0]

auto[0]

auto[0]

1239

1

T3

3

T6

1

T7

1

disabled

auto[0]

auto[0]

auto[1]

1156

1

T2

2

T6

1

T31

1

disabled

auto[0]

auto[1]

auto[0]

1276

1

T2

3

T3

5

T6

1

disabled

auto[0]

auto[1]

auto[1]

1201

1

T2

1

T3

3

T6

2

disabled

auto[1]

auto[0]

auto[0]

5893

1

T2

4

T3

7

T19

386

disabled

auto[1]

auto[0]

auto[1]

1214

1

T3

3

T6

1

T7

1

disabled

auto[1]

auto[1]

auto[0]

1294

1

T3

2

T7

1

T25

19

disabled

auto[1]

auto[1]

auto[1]

1216

1

T2

2

T6

1

T31

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15755

1

T1

14

T2

7

T3

10

enabled

disabled

69

1

T48

3

T52

2

T53

1

disabled

disabled

112

1

T2

1

T25

1

T48

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14377

1

T2

11

T3

23

T6

7

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1246	1			T1	1		T2	4		T5	4
key_invalid	sha2_none	865	1			T1	1		T3	3		T7	1
key_invalid	sha2_512	921	1			T1	1		T2	1		T3	1
key_invalid	sha2_384	874	1			T2	1		T3	2		T6	1
key_invalid	sha2_256	833	1			T2	1		T3	1		T6	1
key_none	sha2_invalid	561	1			T1	1		T3	2		T7	1
key_none	sha2_none	559	1			T2	1		T3	1		T6	1
key_none	sha2_512	2570	1			T3	1		T6	1		T7	1
key_none	sha2_384	2498	1			T19	386		T5	1		T31	2
key_none	sha2_256	1372	1			T3	2		T6	1		T5	1
key_1024	sha2_invalid	513	1			T3	3		T5	2		T25	6
key_1024	sha2_none	587	1			T1	2		T2	1		T3	2
key_1024	sha2_512	1722	1			T6	1		T7	1		T25	5
key_1024	sha2_384	898	1			T4	1		T5	5		T31	2
key_512	sha2_invalid	504	1			T3	1		T5	2		T25	4
key_512	sha2_none	590	1			T1	1		T7	2		T5	1
key_512	sha2_512	616	1			T2	2		T3	2		T6	2
key_512	sha2_384	1195	1			T7	1		T5	1		T31	1
key_512	sha2_256	803	1			T1	1		T3	1		T25	9
key_384	sha2_invalid	520	1			T3	1		T6	1		T5	1
key_384	sha2_none	582	1			T3	2		T5	2		T31	1
key_384	sha2_512	571	1			T4	1		T31	1		T25	3
key_384	sha2_384	638	1			T2	1		T4	2		T25	13
key_384	sha2_256	1107	1			T1	1		T3	1		T4	2
key_256	sha2_invalid	538	1			T3	1		T4	1		T7	1
key_256	sha2_none	562	1			T1	1		T2	1		T6	1
key_256	sha2_512	629	1			T1	1		T4	1		T5	3
key_256	sha2_384	642	1			T3	1		T6	1		T4	1
key_256	sha2_256	783	1			T1	1		T2	2		T18	1
key_128	sha2_invalid	505	1			T5	1		T25	8		T27	2
key_128	sha2_none	563	1			T1	1		T3	1		T6	1
key_128	sha2_512	637	1			T2	1		T25	8		T27	1
key_128	sha2_384	621	1			T1	1		T4	1		T31	1
key_128	sha2_256	631	1			T2	1		T3	1		T6	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

589

1

T2

1

T3

1

T6

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1246	1			T1	1		T2	4		T5	4
key_invalid	sha2_none	865	1			T1	1		T3	3		T7	1
key_invalid	sha2_512	921	1			T1	1		T2	1		T3	1
key_invalid	sha2_384	874	1			T2	1		T3	2		T6	1
key_invalid	sha2_256	833	1			T2	1		T3	1		T6	1
key_none	sha2_invalid	561	1			T1	1		T3	2		T7	1
key_none	sha2_none	559	1			T2	1		T3	1		T6	1
key_none	sha2_512	2570	1			T3	1		T6	1		T7	1
key_none	sha2_384	2498	1			T19	386		T5	1		T31	2
key_none	sha2_256	1372	1			T3	2		T6	1		T5	1
key_1024	sha2_invalid	513	1			T3	3		T5	2		T25	6
key_1024	sha2_none	587	1			T1	2		T2	1		T3	2
key_1024	sha2_512	1722	1			T6	1		T7	1		T25	5
key_1024	sha2_384	898	1			T4	1		T5	5		T31	2
key_1024	sha2_256	589	1			T2	1		T3	1		T6	2
key_512	sha2_invalid	504	1			T3	1		T5	2		T25	4
key_512	sha2_none	590	1			T1	1		T7	2		T5	1
key_512	sha2_512	616	1			T2	2		T3	2		T6	2
key_512	sha2_384	1195	1			T7	1		T5	1		T31	1
key_512	sha2_256	803	1			T1	1		T3	1		T25	9
key_384	sha2_invalid	520	1			T3	1		T6	1		T5	1
key_384	sha2_none	582	1			T3	2		T5	2		T31	1
key_384	sha2_512	571	1			T4	1		T31	1		T25	3
key_384	sha2_384	638	1			T2	1		T4	2		T25	13
key_384	sha2_256	1107	1			T1	1		T3	1		T4	2
key_256	sha2_invalid	538	1			T3	1		T4	1		T7	1
key_256	sha2_none	562	1			T1	1		T2	1		T6	1
key_256	sha2_512	629	1			T1	1		T4	1		T5	3
key_256	sha2_384	642	1			T3	1		T6	1		T4	1
key_256	sha2_256	783	1			T1	1		T2	2		T18	1
key_128	sha2_invalid	505	1			T5	1		T25	8		T27	2
key_128	sha2_none	563	1			T1	1		T3	1		T6	1
key_128	sha2_512	637	1			T2	1		T25	8		T27	1
key_128	sha2_384	621	1			T1	1		T4	1		T31	1
key_128	sha2_256	631	1			T2	1		T3	1		T6	1