Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 657
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T533 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4198697209 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:08 PM PDT 24 57591163 ps
T114 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3972054799 Jul 22 06:59:11 PM PDT 24 Jul 22 06:59:20 PM PDT 24 125285011 ps
T94 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1284644735 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:27 PM PDT 24 330349442 ps
T534 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.777071506 Jul 22 06:59:12 PM PDT 24 Jul 22 06:59:21 PM PDT 24 24484175 ps
T535 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1214821915 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:39 PM PDT 24 13616840 ps
T536 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2761189397 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:41 PM PDT 24 51953790 ps
T74 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.319081078 Jul 22 06:59:02 PM PDT 24 Jul 22 06:59:12 PM PDT 24 212339118 ps
T537 /workspace/coverage/cover_reg_top/28.hmac_intr_test.505663570 Jul 22 06:59:21 PM PDT 24 Jul 22 06:59:37 PM PDT 24 11611867 ps
T75 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.175305700 Jul 22 06:59:19 PM PDT 24 Jul 22 06:59:35 PM PDT 24 192219810 ps
T538 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1521830981 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:24 PM PDT 24 20176620 ps
T539 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3131498137 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:26 PM PDT 24 16680193 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3299739811 Jul 22 06:59:36 PM PDT 24 Jul 22 06:59:55 PM PDT 24 93228769 ps
T541 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3544444543 Jul 22 07:00:32 PM PDT 24 Jul 22 07:00:47 PM PDT 24 13721765 ps
T139 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3241270874 Jul 22 06:59:19 PM PDT 24 Jul 22 06:59:34 PM PDT 24 72446549 ps
T138 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.903003507 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:43 PM PDT 24 228911566 ps
T542 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1035314933 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:37 PM PDT 24 15422923 ps
T543 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2773664022 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 10317531 ps
T115 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2839560847 Jul 22 06:59:08 PM PDT 24 Jul 22 06:59:18 PM PDT 24 131733226 ps
T121 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.908669790 Jul 22 06:59:04 PM PDT 24 Jul 22 06:59:23 PM PDT 24 4587673483 ps
T544 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.843760436 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:42 PM PDT 24 100506420 ps
T125 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3247705090 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:22 PM PDT 24 32978669 ps
T141 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.710534497 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:26 PM PDT 24 1203159528 ps
T545 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1258356177 Jul 22 06:59:11 PM PDT 24 Jul 22 06:59:22 PM PDT 24 346823774 ps
T546 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3495629029 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 32517587 ps
T547 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.84500465 Jul 22 06:59:18 PM PDT 24 Jul 22 06:59:32 PM PDT 24 166022995 ps
T126 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4145549328 Jul 22 07:00:31 PM PDT 24 Jul 22 07:00:46 PM PDT 24 512039001 ps
T127 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1781296472 Jul 22 06:59:04 PM PDT 24 Jul 22 06:59:13 PM PDT 24 19924030 ps
T548 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3548030353 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:46 PM PDT 24 51969515 ps
T136 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.862834157 Jul 22 06:59:18 PM PDT 24 Jul 22 06:59:33 PM PDT 24 172713745 ps
T549 /workspace/coverage/cover_reg_top/39.hmac_intr_test.801983854 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 10795507 ps
T550 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.103301025 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:26 PM PDT 24 235806882 ps
T142 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.877082437 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:41 PM PDT 24 904070212 ps
T128 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3212639082 Jul 22 06:59:08 PM PDT 24 Jul 22 06:59:17 PM PDT 24 44445353 ps
T551 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1319030190 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 336118107 ps
T552 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1309850773 Jul 22 07:00:24 PM PDT 24 Jul 22 07:00:41 PM PDT 24 1830428442 ps
T553 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3577586937 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 101995715 ps
T554 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2397821307 Jul 22 06:59:27 PM PDT 24 Jul 22 06:59:44 PM PDT 24 212850048 ps
T555 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3022383399 Jul 22 06:59:12 PM PDT 24 Jul 22 06:59:22 PM PDT 24 144011006 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1962734356 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:48 PM PDT 24 23806297 ps
T557 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1928951787 Jul 22 06:59:34 PM PDT 24 Jul 22 06:59:51 PM PDT 24 37688094 ps
T137 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4134294693 Jul 22 06:59:25 PM PDT 24 Jul 22 06:59:45 PM PDT 24 490761856 ps
T116 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1881154460 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:09 PM PDT 24 39509268 ps
T558 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2777601024 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:41 PM PDT 24 68909546 ps
T559 /workspace/coverage/cover_reg_top/20.hmac_intr_test.747198812 Jul 22 07:00:32 PM PDT 24 Jul 22 07:00:46 PM PDT 24 17071165 ps
T129 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2689348630 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:27 PM PDT 24 383542243 ps
T560 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1177558917 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:29 PM PDT 24 126378730 ps
T561 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2892474609 Jul 22 06:59:12 PM PDT 24 Jul 22 06:59:21 PM PDT 24 24901483 ps
T562 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.512847459 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:26 PM PDT 24 49034663 ps
T563 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3050839577 Jul 22 06:59:21 PM PDT 24 Jul 22 06:59:37 PM PDT 24 66946309 ps
T117 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.263744138 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:39 PM PDT 24 63777539 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4038511825 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:09 PM PDT 24 19147937 ps
T130 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2749669809 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:38 PM PDT 24 19402673 ps
T565 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.84242163 Jul 22 06:59:07 PM PDT 24 Jul 22 06:59:17 PM PDT 24 53492042 ps
T76 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3638290926 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:12 PM PDT 24 496897038 ps
T566 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1437092166 Jul 22 07:00:30 PM PDT 24 Jul 22 07:00:44 PM PDT 24 57874900 ps
T567 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4102797726 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 23060783 ps
T568 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1814038729 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:09 PM PDT 24 13797174 ps
T569 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1055336212 Jul 22 07:00:03 PM PDT 24 Jul 22 07:00:16 PM PDT 24 304622783 ps
T570 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.292485342 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:25 PM PDT 24 113212205 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2796637238 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:11 PM PDT 24 247723596 ps
T571 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1029834730 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:27 PM PDT 24 189498324 ps
T572 /workspace/coverage/cover_reg_top/31.hmac_intr_test.576915307 Jul 22 07:00:14 PM PDT 24 Jul 22 07:00:30 PM PDT 24 13271976 ps
T573 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3790155461 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:25 PM PDT 24 140609346 ps
T574 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2594978850 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:43 PM PDT 24 48235129 ps
T575 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3952669701 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 35667050 ps
T576 /workspace/coverage/cover_reg_top/13.hmac_intr_test.352257908 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:48 PM PDT 24 14549284 ps
T577 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1990003645 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:44 PM PDT 24 16990946 ps
T131 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4247017513 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 20233414 ps
T578 /workspace/coverage/cover_reg_top/25.hmac_intr_test.877413648 Jul 22 06:59:25 PM PDT 24 Jul 22 06:59:41 PM PDT 24 49007808 ps
T579 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1991886085 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:39 PM PDT 24 13191398 ps
T580 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2078595059 Jul 22 06:59:28 PM PDT 24 Jul 22 06:59:46 PM PDT 24 431472324 ps
T581 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3726033630 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:39 PM PDT 24 13516835 ps
T119 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2633278681 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:38 PM PDT 24 26957672 ps
T582 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.320192289 Jul 22 06:59:25 PM PDT 24 Jul 22 06:59:45 PM PDT 24 289601357 ps
T583 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2084468573 Jul 22 06:59:33 PM PDT 24 Jul 22 06:59:51 PM PDT 24 32905260 ps
T143 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3702504628 Jul 22 06:59:20 PM PDT 24 Jul 22 06:59:38 PM PDT 24 667757855 ps
T584 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3897029551 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 14994535 ps
T585 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3438475212 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:25 PM PDT 24 147705237 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.517720094 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:27 PM PDT 24 20296296 ps
T587 /workspace/coverage/cover_reg_top/49.hmac_intr_test.649540563 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:43 PM PDT 24 50710051 ps
T120 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1733438219 Jul 22 06:59:08 PM PDT 24 Jul 22 06:59:32 PM PDT 24 1542071366 ps
T122 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3452089961 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:10 PM PDT 24 2623983193 ps
T123 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3827768979 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:09 PM PDT 24 91140564 ps
T588 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3677744558 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:45 PM PDT 24 618246635 ps
T589 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4022654612 Jul 22 06:59:20 PM PDT 24 Jul 22 06:59:36 PM PDT 24 939748639 ps
T590 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.741410825 Jul 22 06:59:08 PM PDT 24 Jul 22 06:59:19 PM PDT 24 222073919 ps
T591 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1329548933 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:28 PM PDT 24 64849902 ps
T140 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.134599170 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:52 PM PDT 24 682836489 ps
T124 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2284233795 Jul 22 06:59:36 PM PDT 24 Jul 22 07:00:02 PM PDT 24 1027979652 ps
T144 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.951520346 Jul 22 07:00:03 PM PDT 24 Jul 22 07:00:16 PM PDT 24 162394250 ps
T592 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1057939620 Jul 22 06:58:59 PM PDT 24 Jul 22 06:59:14 PM PDT 24 431868989 ps
T593 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1144098368 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:23 PM PDT 24 69077747 ps
T594 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3457419864 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:17 PM PDT 24 110866558 ps
T595 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2352228009 Jul 22 06:59:18 PM PDT 24 Jul 22 06:59:31 PM PDT 24 21686708 ps
T596 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1078043878 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:50 PM PDT 24 67663287 ps
T597 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3350062878 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 16558674 ps
T598 /workspace/coverage/cover_reg_top/16.hmac_intr_test.878360513 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:49 PM PDT 24 50078159 ps
T599 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3914056449 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:12 PM PDT 24 29213945 ps
T600 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1451468499 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:39 PM PDT 24 179951291 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3968917706 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:23 PM PDT 24 62677641 ps
T602 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2483212885 Jul 22 06:59:18 PM PDT 24 Jul 22 06:59:31 PM PDT 24 11819448 ps
T603 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3310606283 Jul 22 06:59:19 PM PDT 24 Jul 22 06:59:36 PM PDT 24 106108397 ps
T604 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2116344371 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 12304914 ps
T605 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1577367762 Jul 22 07:00:31 PM PDT 24 Jul 22 07:00:46 PM PDT 24 42518377 ps
T145 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2959157044 Jul 22 07:00:03 PM PDT 24 Jul 22 07:00:14 PM PDT 24 200627881 ps
T606 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1562599892 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:26 PM PDT 24 127822827 ps
T607 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2017196207 Jul 22 07:00:03 PM PDT 24 Jul 22 07:00:13 PM PDT 24 57169970 ps
T608 /workspace/coverage/cover_reg_top/24.hmac_intr_test.644186897 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 11662076 ps
T609 /workspace/coverage/cover_reg_top/12.hmac_intr_test.641820660 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:24 PM PDT 24 13558632 ps
T610 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4249458261 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:08 PM PDT 24 76805546 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2999311132 Jul 22 07:00:31 PM PDT 24 Jul 22 07:00:46 PM PDT 24 42041767 ps
T612 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1425065221 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:11 PM PDT 24 37430027 ps
T613 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2801086732 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:47 PM PDT 24 1475746101 ps
T614 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2545047272 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:38 PM PDT 24 23820188 ps
T615 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4048268118 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:08 PM PDT 24 68367207 ps
T616 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3755831619 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:28 PM PDT 24 897428459 ps
T617 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.691261200 Jul 22 07:00:13 PM PDT 24 Jul 22 07:00:31 PM PDT 24 884580181 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4211542036 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:12 PM PDT 24 2689414285 ps
T619 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3329642225 Jul 22 06:59:29 PM PDT 24 Jul 22 06:59:47 PM PDT 24 506799109 ps
T620 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1690060558 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:30 PM PDT 24 3489499761 ps
T621 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2729374452 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:42 PM PDT 24 60237350 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3765501567 Jul 22 06:59:08 PM PDT 24 Jul 22 06:59:19 PM PDT 24 172139773 ps
T623 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3243303623 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:41 PM PDT 24 52463550 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1756538232 Jul 22 06:58:58 PM PDT 24 Jul 22 06:59:05 PM PDT 24 58353480 ps
T625 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2848313024 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:11 PM PDT 24 250543854 ps
T626 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.834662751 Jul 22 06:59:25 PM PDT 24 Jul 22 06:59:43 PM PDT 24 64196207 ps
T627 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3557427787 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:40 PM PDT 24 25122096 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4028512451 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:07 PM PDT 24 13438156 ps
T629 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1606864378 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:11 PM PDT 24 229368486 ps
T630 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2262462261 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:29 PM PDT 24 93592712 ps
T631 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4191997816 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:23 PM PDT 24 254066062 ps
T632 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3872924187 Jul 22 06:59:14 PM PDT 24 Jul 22 06:59:26 PM PDT 24 40068799 ps
T633 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3344861602 Jul 22 06:59:04 PM PDT 24 Jul 22 06:59:12 PM PDT 24 35953156 ps
T634 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.462808900 Jul 22 06:59:25 PM PDT 24 Jul 22 06:59:43 PM PDT 24 87072581 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1628908653 Jul 22 06:59:29 PM PDT 24 Jul 22 06:59:48 PM PDT 24 584862117 ps
T636 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3837156526 Jul 22 06:59:19 PM PDT 24 Jul 22 06:59:34 PM PDT 24 150748428 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3921097723 Jul 22 06:59:12 PM PDT 24 Jul 22 06:59:22 PM PDT 24 186298170 ps
T638 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1963269242 Jul 22 06:59:24 PM PDT 24 Jul 22 06:59:41 PM PDT 24 18760728 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.635160597 Jul 22 06:59:13 PM PDT 24 Jul 22 06:59:22 PM PDT 24 52452024 ps
T640 /workspace/coverage/cover_reg_top/14.hmac_intr_test.780304688 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:27 PM PDT 24 11939741 ps
T641 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1826966866 Jul 22 06:59:27 PM PDT 24 Jul 22 06:59:44 PM PDT 24 49373237 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.897180337 Jul 22 06:59:20 PM PDT 24 Jul 22 06:59:36 PM PDT 24 63021637 ps
T643 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3137156669 Jul 22 06:59:28 PM PDT 24 Jul 22 06:59:45 PM PDT 24 43149989 ps
T644 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.848918636 Jul 22 06:59:19 PM PDT 24 Jul 22 06:59:36 PM PDT 24 120263334 ps
T645 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3724891067 Jul 22 06:59:15 PM PDT 24 Jul 22 06:59:27 PM PDT 24 67326262 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3004235607 Jul 22 06:59:26 PM PDT 24 Jul 22 06:59:44 PM PDT 24 416383743 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1466135648 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:08 PM PDT 24 195374621 ps
T648 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.521422358 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:09 PM PDT 24 51674165 ps
T649 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1740176787 Jul 22 06:59:31 PM PDT 24 Jul 22 06:59:48 PM PDT 24 35781429 ps
T650 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2462622112 Jul 22 06:59:03 PM PDT 24 Jul 22 06:59:13 PM PDT 24 206272228 ps
T651 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4080583256 Jul 22 06:59:22 PM PDT 24 Jul 22 06:59:38 PM PDT 24 28975186 ps
T652 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.384308264 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:08 PM PDT 24 18337695 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1331705881 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:11 PM PDT 24 113646077 ps
T654 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2689746831 Jul 22 06:59:23 PM PDT 24 Jul 22 06:59:40 PM PDT 24 96667605 ps
T655 /workspace/coverage/cover_reg_top/0.hmac_intr_test.108408444 Jul 22 06:59:01 PM PDT 24 Jul 22 06:59:08 PM PDT 24 40277151 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.521261871 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:11 PM PDT 24 111921220 ps
T657 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.350638980 Jul 22 06:59:00 PM PDT 24 Jul 22 06:59:09 PM PDT 24 643855881 ps

Test location /workspace/coverage/default/19.hmac_long_msg.1916714968
Short name T3
Test name
Test status
Simulation time 7643913976 ps
CPU time 100.71 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:29:26 PM PDT 24
Peak memory 216684 kb
Host smart-dc89bb11-585f-4f55-ab97-62b35877cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916714968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1916714968
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3222857900
Short name T58
Test name
Test status
Simulation time 105671234480 ps
CPU time 560.72 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 06:37:53 PM PDT 24
Peak memory 469964 kb
Host smart-1150fb76-5a0a-4b73-9cec-6e2f2445a520
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222857900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3222857900
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.546432564
Short name T9
Test name
Test status
Simulation time 556922158752 ps
CPU time 4532.82 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 07:43:03 PM PDT 24
Peak memory 818408 kb
Host smart-1ebbf709-259f-4e6e-84e8-d5019d0b9e65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546432564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.546432564
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2312453332
Short name T25
Test name
Test status
Simulation time 57293489410 ps
CPU time 1460.16 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:51:52 PM PDT 24
Peak memory 466744 kb
Host smart-d16c52af-00be-46ee-a7d7-a3868b0faa61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312453332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2312453332
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all.368793568
Short name T29
Test name
Test status
Simulation time 20637380135 ps
CPU time 2855.58 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 804096 kb
Host smart-baf177f2-6a92-44e1-8673-60e9a9fccf46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368793568 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.368793568
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.319081078
Short name T74
Test name
Test status
Simulation time 212339118 ps
CPU time 3.17 seconds
Started Jul 22 06:59:02 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 199892 kb
Host smart-6b928139-bddd-4583-9a9a-39c3e2114acd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319081078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.319081078
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1950415297
Short name T59
Test name
Test status
Simulation time 236741819 ps
CPU time 0.95 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:27:29 PM PDT 24
Peak memory 218644 kb
Host smart-a8b3915b-f9f7-4b35-b317-19637239a66b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950415297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1950415297
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2839560847
Short name T115
Test name
Test status
Simulation time 131733226 ps
CPU time 0.94 seconds
Started Jul 22 06:59:08 PM PDT 24
Finished Jul 22 06:59:18 PM PDT 24
Peak memory 199644 kb
Host smart-6b1e0013-4be3-4de7-a642-cd3dbfe2621c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839560847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2839560847
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2554720820
Short name T157
Test name
Test status
Simulation time 140010652825 ps
CPU time 1128.75 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:46:29 PM PDT 24
Peak memory 675056 kb
Host smart-dfbc486f-c60a-4b40-9fc6-316b233d6f51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554720820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2554720820
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.889944779
Short name T33
Test name
Test status
Simulation time 16686791399 ps
CPU time 72.29 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:29:00 PM PDT 24
Peak memory 200260 kb
Host smart-96a2d448-5ab2-41f3-b741-de28cf5153a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889944779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.889944779
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3453139625
Short name T57
Test name
Test status
Simulation time 15767217 ps
CPU time 0.63 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:27:49 PM PDT 24
Peak memory 195996 kb
Host smart-2417fe94-d078-44b5-8bf4-30686f1f2aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453139625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3453139625
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.862834157
Short name T136
Test name
Test status
Simulation time 172713745 ps
CPU time 2.98 seconds
Started Jul 22 06:59:18 PM PDT 24
Finished Jul 22 06:59:33 PM PDT 24
Peak memory 199660 kb
Host smart-d841ccc4-55f8-4aec-920f-af07fde3161d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862834157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.862834157
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4285197249
Short name T88
Test name
Test status
Simulation time 311623615990 ps
CPU time 2482.19 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 07:08:57 PM PDT 24
Peak memory 765656 kb
Host smart-1e4d0a73-903f-4073-a9da-a1626d1dfd5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285197249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4285197249
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2837271245
Short name T148
Test name
Test status
Simulation time 101119143258 ps
CPU time 939.77 seconds
Started Jul 22 06:28:41 PM PDT 24
Finished Jul 22 06:44:21 PM PDT 24
Peak memory 675028 kb
Host smart-0df7b34d-ffd4-4c52-8e6e-bcb0ebbfcb22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837271245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2837271245
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.710534497
Short name T141
Test name
Test status
Simulation time 1203159528 ps
CPU time 4.56 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 199936 kb
Host smart-4370396a-1a29-49a4-9d32-7a2facaf75e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710534497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.710534497
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3991492123
Short name T433
Test name
Test status
Simulation time 8957270834 ps
CPU time 1081.95 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:45:48 PM PDT 24
Peak memory 748712 kb
Host smart-f5168de3-7c99-4868-b9fc-876755a665b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991492123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3991492123
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4019082732
Short name T83
Test name
Test status
Simulation time 25653867364 ps
CPU time 115.96 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:29:45 PM PDT 24
Peak memory 200380 kb
Host smart-0336bade-afbe-4fd2-8897-d66fc8b795ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019082732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4019082732
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3638290926
Short name T76
Test name
Test status
Simulation time 496897038 ps
CPU time 4.21 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 199888 kb
Host smart-b609c858-a4fa-4e30-a1c1-d3ffeee114ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638290926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3638290926
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3069907361
Short name T8
Test name
Test status
Simulation time 356542305718 ps
CPU time 1654.16 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:55:06 PM PDT 24
Peak memory 731808 kb
Host smart-b478c504-bf89-48c6-9d3e-9faed1cb2b04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069907361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3069907361
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2284233795
Short name T124
Test name
Test status
Simulation time 1027979652 ps
CPU time 8.55 seconds
Started Jul 22 06:59:36 PM PDT 24
Finished Jul 22 07:00:02 PM PDT 24
Peak memory 199788 kb
Host smart-edbf29f7-dd43-4eab-9fc7-1370c4a2bfb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284233795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2284233795
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.521261871
Short name T656
Test name
Test status
Simulation time 111921220 ps
CPU time 5.17 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199880 kb
Host smart-5f8f96ca-1c1c-46dc-9dfb-92a2ff793ea0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521261871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.521261871
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4198697209
Short name T533
Test name
Test status
Simulation time 57591163 ps
CPU time 0.86 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 199296 kb
Host smart-39b03c30-2752-472f-a483-c2dccb705845
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198697209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4198697209
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3299739811
Short name T540
Test name
Test status
Simulation time 93228769 ps
CPU time 2.19 seconds
Started Jul 22 06:59:36 PM PDT 24
Finished Jul 22 06:59:55 PM PDT 24
Peak memory 199912 kb
Host smart-aef50323-41ba-4eb2-9a9b-f6a703d1d75e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299739811 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3299739811
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4048268118
Short name T615
Test name
Test status
Simulation time 68367207 ps
CPU time 1.01 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 199648 kb
Host smart-bddc2b46-ef92-4672-944e-de53fef312bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048268118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4048268118
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.108408444
Short name T655
Test name
Test status
Simulation time 40277151 ps
CPU time 0.59 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 194828 kb
Host smart-69af578c-cb60-4cfa-9926-51eb3cebd8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108408444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.108408444
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1466135648
Short name T647
Test name
Test status
Simulation time 195374621 ps
CPU time 1.14 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 199832 kb
Host smart-5586c10f-68b0-4db0-a701-3e3cc2c5ff2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466135648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1466135648
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1606864378
Short name T629
Test name
Test status
Simulation time 229368486 ps
CPU time 4.12 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199892 kb
Host smart-b90ba0bc-eeb0-4033-8deb-63859de0149e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606864378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1606864378
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3457419864
Short name T594
Test name
Test status
Simulation time 110866558 ps
CPU time 5.41 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:17 PM PDT 24
Peak memory 199812 kb
Host smart-be1eb5fc-5e5a-411c-9d87-141d03367538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457419864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3457419864
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4211542036
Short name T618
Test name
Test status
Simulation time 2689414285 ps
CPU time 5.4 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 199988 kb
Host smart-d1ee9038-2e48-49c2-b62e-b66b258d1ebd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211542036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4211542036
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1881154460
Short name T116
Test name
Test status
Simulation time 39509268 ps
CPU time 0.77 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 198016 kb
Host smart-5f63a820-3146-412c-8d9a-49f8f58d7680
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881154460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1881154460
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1425065221
Short name T612
Test name
Test status
Simulation time 37430027 ps
CPU time 1.23 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199708 kb
Host smart-37363aa2-e958-484b-8d8f-f193e3cfbfbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425065221 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1425065221
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3914056449
Short name T599
Test name
Test status
Simulation time 29213945 ps
CPU time 1.03 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 199396 kb
Host smart-04686460-1612-4389-90cf-9b7a803886c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914056449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3914056449
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4249458261
Short name T610
Test name
Test status
Simulation time 76805546 ps
CPU time 0.61 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 194824 kb
Host smart-50ff1268-ebff-47a2-a4b4-2d64c8e800f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249458261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4249458261
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1331705881
Short name T653
Test name
Test status
Simulation time 113646077 ps
CPU time 2.4 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199840 kb
Host smart-90734e69-14a6-46b6-90d0-831e1a12dbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331705881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1331705881
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2848313024
Short name T625
Test name
Test status
Simulation time 250543854 ps
CPU time 1.64 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199928 kb
Host smart-5aed8597-a6b9-43fc-9a45-4cc04bf7c2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848313024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2848313024
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3438475212
Short name T585
Test name
Test status
Simulation time 147705237 ps
CPU time 2.31 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 199932 kb
Host smart-6b59274a-11a6-4ac1-9d11-22d56779e3bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438475212 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3438475212
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.292485342
Short name T570
Test name
Test status
Simulation time 113212205 ps
CPU time 0.93 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 199728 kb
Host smart-5c4820fb-9adf-4116-abc9-7349d765e87e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292485342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.292485342
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3968917706
Short name T601
Test name
Test status
Simulation time 62677641 ps
CPU time 0.62 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:23 PM PDT 24
Peak memory 194972 kb
Host smart-eabc0406-7bb7-4ec1-b65c-36f59390136f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968917706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3968917706
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3837156526
Short name T636
Test name
Test status
Simulation time 150748428 ps
CPU time 2.48 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:34 PM PDT 24
Peak memory 199920 kb
Host smart-b89fc6c8-7959-4246-bda3-d11482414921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837156526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3837156526
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1177558917
Short name T560
Test name
Test status
Simulation time 126378730 ps
CPU time 2.76 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:29 PM PDT 24
Peak memory 199816 kb
Host smart-1eca0d1c-095e-475b-b605-e7c3156a9b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177558917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1177558917
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1628908653
Short name T635
Test name
Test status
Simulation time 584862117 ps
CPU time 2.94 seconds
Started Jul 22 06:59:29 PM PDT 24
Finished Jul 22 06:59:48 PM PDT 24
Peak memory 199908 kb
Host smart-01b46f8c-0117-4471-bdde-bd4c0cf53a80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628908653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1628908653
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1451468499
Short name T600
Test name
Test status
Simulation time 179951291 ps
CPU time 1.13 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 199668 kb
Host smart-83a27d94-dc50-4dbe-8a86-92317cbab55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451468499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1451468499
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.635160597
Short name T639
Test name
Test status
Simulation time 52452024 ps
CPU time 0.82 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:22 PM PDT 24
Peak memory 199256 kb
Host smart-ad5997f9-aadd-4a5d-922b-16db4552df91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635160597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.635160597
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1521830981
Short name T538
Test name
Test status
Simulation time 20176620 ps
CPU time 0.62 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:24 PM PDT 24
Peak memory 194888 kb
Host smart-7a79a008-67bc-42b0-8a94-7cb2878d9b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521830981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1521830981
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1329548933
Short name T591
Test name
Test status
Simulation time 64849902 ps
CPU time 1.64 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:28 PM PDT 24
Peak memory 199852 kb
Host smart-b5051eca-ad05-42bb-98e1-8ce29b05b93c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329548933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1329548933
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.320192289
Short name T582
Test name
Test status
Simulation time 289601357 ps
CPU time 2.98 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:45 PM PDT 24
Peak memory 199880 kb
Host smart-cc4f8044-539f-4ffe-b830-d9342c470a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320192289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.320192289
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.517720094
Short name T586
Test name
Test status
Simulation time 20296296 ps
CPU time 1.05 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 199732 kb
Host smart-cdfedf6c-0588-4fa9-bbd6-99176d00b3c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517720094 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.517720094
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3247705090
Short name T125
Test name
Test status
Simulation time 32978669 ps
CPU time 0.93 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:22 PM PDT 24
Peak memory 199780 kb
Host smart-d63c2b57-7e76-4348-a92f-b43979c38e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247705090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3247705090
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.641820660
Short name T609
Test name
Test status
Simulation time 13558632 ps
CPU time 0.57 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:24 PM PDT 24
Peak memory 194716 kb
Host smart-1505906b-8f6f-42d0-8a59-e3d228458a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641820660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.641820660
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3724891067
Short name T645
Test name
Test status
Simulation time 67326262 ps
CPU time 1.55 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 199788 kb
Host smart-cd1cd06e-ed79-494f-a688-1f9afc974f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724891067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3724891067
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.103301025
Short name T550
Test name
Test status
Simulation time 235806882 ps
CPU time 1.39 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 199972 kb
Host smart-b1f73e92-6c2e-4441-9b10-a830e62b52a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103301025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.103301025
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2801086732
Short name T613
Test name
Test status
Simulation time 1475746101 ps
CPU time 4.52 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:47 PM PDT 24
Peak memory 199860 kb
Host smart-6cc1c8a6-d6fd-4614-b09a-5f8e4dfa67cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801086732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2801086732
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3872924187
Short name T632
Test name
Test status
Simulation time 40068799 ps
CPU time 1.24 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 199764 kb
Host smart-ee3c227c-0d21-42d0-98ce-c9cc513b796e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872924187 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3872924187
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2515099744
Short name T532
Test name
Test status
Simulation time 18878601 ps
CPU time 0.76 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:33 PM PDT 24
Peak memory 197284 kb
Host smart-dbcaf3d8-ff3d-4968-b573-1f22089fdbf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515099744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2515099744
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.352257908
Short name T576
Test name
Test status
Simulation time 14549284 ps
CPU time 0.62 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:48 PM PDT 24
Peak memory 194856 kb
Host smart-bf4afe09-32c0-4b79-8e22-2db766c94bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352257908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.352257908
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2689746831
Short name T654
Test name
Test status
Simulation time 96667605 ps
CPU time 1.65 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 199920 kb
Host smart-3b317563-7dbc-4628-aeb0-8dbd9d0814cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689746831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2689746831
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1258356177
Short name T545
Test name
Test status
Simulation time 346823774 ps
CPU time 2.16 seconds
Started Jul 22 06:59:11 PM PDT 24
Finished Jul 22 06:59:22 PM PDT 24
Peak memory 199868 kb
Host smart-f0e448d7-dee6-4fcd-9f9f-7db6fb3a9039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258356177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1258356177
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3241270874
Short name T139
Test name
Test status
Simulation time 72446549 ps
CPU time 1.84 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:34 PM PDT 24
Peak memory 199892 kb
Host smart-00d4dba2-4934-475c-8970-c50d95ca3731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241270874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3241270874
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2729374452
Short name T621
Test name
Test status
Simulation time 60237350 ps
CPU time 1.56 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:42 PM PDT 24
Peak memory 199972 kb
Host smart-436eb522-8e47-4fc9-9886-c22fc103987d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729374452 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2729374452
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3972054799
Short name T114
Test name
Test status
Simulation time 125285011 ps
CPU time 0.77 seconds
Started Jul 22 06:59:11 PM PDT 24
Finished Jul 22 06:59:20 PM PDT 24
Peak memory 197848 kb
Host smart-e8b19cc2-dddd-4edb-afbe-efc330e1dca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972054799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3972054799
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.780304688
Short name T640
Test name
Test status
Simulation time 11939741 ps
CPU time 0.57 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 194792 kb
Host smart-27afaab3-7922-42c4-8c08-126382250899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780304688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.780304688
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1562599892
Short name T606
Test name
Test status
Simulation time 127822827 ps
CPU time 1.58 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 199892 kb
Host smart-1bc80db6-159f-4990-a834-76a1d3b3db23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562599892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1562599892
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2084468573
Short name T583
Test name
Test status
Simulation time 32905260 ps
CPU time 1.66 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 06:59:51 PM PDT 24
Peak memory 199920 kb
Host smart-d4c87a08-f111-489d-974a-02d3cad62444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084468573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2084468573
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2777601024
Short name T558
Test name
Test status
Simulation time 68909546 ps
CPU time 1.98 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 200056 kb
Host smart-f604ee25-1949-4539-aa37-eea6abb0a287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777601024 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2777601024
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.263744138
Short name T117
Test name
Test status
Simulation time 63777539 ps
CPU time 0.9 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 199172 kb
Host smart-3afeead5-e7c3-4ef4-abf5-f6a58088c1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263744138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.263744138
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2773664022
Short name T543
Test name
Test status
Simulation time 10317531 ps
CPU time 0.57 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194892 kb
Host smart-0bf8b195-bdb3-4502-bb41-4864595a7562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773664022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2773664022
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3004235607
Short name T646
Test name
Test status
Simulation time 416383743 ps
CPU time 1.79 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:44 PM PDT 24
Peak memory 199896 kb
Host smart-c1bbd13a-8666-4ea7-abe6-2f27c5d5dc37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004235607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3004235607
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3243303623
Short name T623
Test name
Test status
Simulation time 52463550 ps
CPU time 2.58 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 199920 kb
Host smart-d23fc416-be31-4abc-ab73-a81cbc25cf71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243303623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3243303623
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.877082437
Short name T142
Test name
Test status
Simulation time 904070212 ps
CPU time 2.73 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 199872 kb
Host smart-01af7c84-ff75-4db3-a886-b97d07eaffde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877082437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.877082437
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1577367762
Short name T605
Test name
Test status
Simulation time 42518377 ps
CPU time 1.2 seconds
Started Jul 22 07:00:31 PM PDT 24
Finished Jul 22 07:00:46 PM PDT 24
Peak memory 199732 kb
Host smart-311b8d8e-6b64-42e8-be63-309834d7c7d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577367762 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1577367762
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.834662751
Short name T626
Test name
Test status
Simulation time 64196207 ps
CPU time 0.95 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:43 PM PDT 24
Peak memory 199644 kb
Host smart-68966d88-d537-46b5-8d42-da3da78db73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834662751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.834662751
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.878360513
Short name T598
Test name
Test status
Simulation time 50078159 ps
CPU time 0.63 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:49 PM PDT 24
Peak memory 194816 kb
Host smart-2ef2377e-c9d1-48da-84d8-50643979e9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878360513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.878360513
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2999311132
Short name T611
Test name
Test status
Simulation time 42041767 ps
CPU time 1.07 seconds
Started Jul 22 07:00:31 PM PDT 24
Finished Jul 22 07:00:46 PM PDT 24
Peak memory 198524 kb
Host smart-f5dc2aa5-53b8-4dd7-8675-cf8ca57ea564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999311132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2999311132
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3548030353
Short name T548
Test name
Test status
Simulation time 51969515 ps
CPU time 2.78 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:46 PM PDT 24
Peak memory 199936 kb
Host smart-aebb93a3-3fbe-4101-8dcf-6727d523e5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548030353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3548030353
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3730587502
Short name T73
Test name
Test status
Simulation time 1305725689 ps
CPU time 2.97 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:24 PM PDT 24
Peak memory 199844 kb
Host smart-16027aa6-a827-4c1c-abff-db4f1f090785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730587502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3730587502
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.691261200
Short name T617
Test name
Test status
Simulation time 884580181 ps
CPU time 1.9 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:00:31 PM PDT 24
Peak memory 199888 kb
Host smart-74c375d6-b157-470b-8330-ac4b213b8320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691261200 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.691261200
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2017196207
Short name T607
Test name
Test status
Simulation time 57169970 ps
CPU time 0.72 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:00:13 PM PDT 24
Peak memory 197920 kb
Host smart-195a8905-3b24-4026-ab15-4d831170fa78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017196207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2017196207
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1437092166
Short name T566
Test name
Test status
Simulation time 57874900 ps
CPU time 0.58 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:00:44 PM PDT 24
Peak memory 194748 kb
Host smart-d7815f2c-29df-4f7e-b0cd-d567b379a425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437092166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1437092166
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4145549328
Short name T126
Test name
Test status
Simulation time 512039001 ps
CPU time 1.8 seconds
Started Jul 22 07:00:31 PM PDT 24
Finished Jul 22 07:00:46 PM PDT 24
Peak memory 199848 kb
Host smart-94531d4e-25f4-44a5-bf89-44c670e8dcf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145549328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4145549328
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1055336212
Short name T569
Test name
Test status
Simulation time 304622783 ps
CPU time 4.05 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:00:16 PM PDT 24
Peak memory 199880 kb
Host smart-de4b2c08-c50f-4841-a3c4-94d97fbc8da3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055336212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1055336212
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2959157044
Short name T145
Test name
Test status
Simulation time 200627881 ps
CPU time 1.77 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:00:14 PM PDT 24
Peak memory 199764 kb
Host smart-b7942a31-9a67-4551-b62c-ea5cf42ccb56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959157044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2959157044
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.843760436
Short name T544
Test name
Test status
Simulation time 100506420 ps
CPU time 3.17 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:42 PM PDT 24
Peak memory 208196 kb
Host smart-59a24f28-b648-457a-bfd1-8ffd0e4498e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843760436 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.843760436
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2749669809
Short name T130
Test name
Test status
Simulation time 19402673 ps
CPU time 0.71 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:38 PM PDT 24
Peak memory 197388 kb
Host smart-0cc84619-db66-459c-b71e-a6e8163eca14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749669809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2749669809
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1991886085
Short name T579
Test name
Test status
Simulation time 13191398 ps
CPU time 0.6 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194924 kb
Host smart-3aebf477-d55a-435f-a853-bda3e2c851ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991886085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1991886085
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.897180337
Short name T642
Test name
Test status
Simulation time 63021637 ps
CPU time 1.62 seconds
Started Jul 22 06:59:20 PM PDT 24
Finished Jul 22 06:59:36 PM PDT 24
Peak memory 199868 kb
Host smart-6f210131-9539-490a-8270-1c5fb5961fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897180337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.897180337
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1319030190
Short name T551
Test name
Test status
Simulation time 336118107 ps
CPU time 1.85 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 199876 kb
Host smart-9c980098-550c-4354-b45f-8b9826320afb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319030190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1319030190
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4134294693
Short name T137
Test name
Test status
Simulation time 490761856 ps
CPU time 4.01 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:45 PM PDT 24
Peak memory 199900 kb
Host smart-7ab796c6-25aa-4f5e-9e0b-d4e2677c568c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134294693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4134294693
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2604870220
Short name T78
Test name
Test status
Simulation time 40366315789 ps
CPU time 188.71 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 07:02:56 PM PDT 24
Peak memory 216284 kb
Host smart-783d0f72-0221-4440-b609-d2c1ceb29a88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604870220 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2604870220
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2633278681
Short name T119
Test name
Test status
Simulation time 26957672 ps
CPU time 0.81 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:38 PM PDT 24
Peak memory 199472 kb
Host smart-d56e2fe3-804d-4e02-8bb3-99303ed7faec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633278681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2633278681
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3726033630
Short name T581
Test name
Test status
Simulation time 13516835 ps
CPU time 0.6 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194680 kb
Host smart-757378fa-3cd3-4ccc-84e3-72ee5e7223fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726033630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3726033630
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3329642225
Short name T619
Test name
Test status
Simulation time 506799109 ps
CPU time 1.73 seconds
Started Jul 22 06:59:29 PM PDT 24
Finished Jul 22 06:59:47 PM PDT 24
Peak memory 199852 kb
Host smart-ba7e2dca-f399-4c13-8e7c-c761476c9cf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329642225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3329642225
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3050839577
Short name T563
Test name
Test status
Simulation time 66946309 ps
CPU time 1.71 seconds
Started Jul 22 06:59:21 PM PDT 24
Finished Jul 22 06:59:37 PM PDT 24
Peak memory 199884 kb
Host smart-c69519ef-8231-448e-b9e8-954ca3dc8cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050839577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3050839577
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.134599170
Short name T140
Test name
Test status
Simulation time 682836489 ps
CPU time 4.05 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:52 PM PDT 24
Peak memory 199860 kb
Host smart-d5da12a0-4037-45ce-9b1a-c0436199e87e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134599170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.134599170
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2693328093
Short name T113
Test name
Test status
Simulation time 109905904 ps
CPU time 5.78 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:14 PM PDT 24
Peak memory 199856 kb
Host smart-59796049-5a2e-4797-adec-78fe40d3874b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693328093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2693328093
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.908669790
Short name T121
Test name
Test status
Simulation time 4587673483 ps
CPU time 11.28 seconds
Started Jul 22 06:59:04 PM PDT 24
Finished Jul 22 06:59:23 PM PDT 24
Peak memory 199812 kb
Host smart-9e0d8039-5c09-432a-a8d1-96c88463d0ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908669790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.908669790
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2796637238
Short name T118
Test name
Test status
Simulation time 247723596 ps
CPU time 0.88 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 199684 kb
Host smart-8d7ea8ac-2536-4bce-b710-6b8f904afd99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796637238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2796637238
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4038511825
Short name T564
Test name
Test status
Simulation time 19147937 ps
CPU time 1.26 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 199772 kb
Host smart-3959f03a-3a2a-4f9e-bacf-ec3eac9341f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038511825 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4038511825
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.384308264
Short name T652
Test name
Test status
Simulation time 18337695 ps
CPU time 0.74 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:08 PM PDT 24
Peak memory 197368 kb
Host smart-069d80b7-68dc-4f32-a41b-6311f9d16b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384308264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.384308264
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4028512451
Short name T628
Test name
Test status
Simulation time 13438156 ps
CPU time 0.58 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:07 PM PDT 24
Peak memory 194756 kb
Host smart-203022b1-38ec-4089-aef6-a8a36460c227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028512451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4028512451
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1781296472
Short name T127
Test name
Test status
Simulation time 19924030 ps
CPU time 1.05 seconds
Started Jul 22 06:59:04 PM PDT 24
Finished Jul 22 06:59:13 PM PDT 24
Peak memory 199568 kb
Host smart-077480fe-1d09-4ad4-9283-ece7bca26598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781296472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1781296472
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2462622112
Short name T650
Test name
Test status
Simulation time 206272228 ps
CPU time 3.65 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:13 PM PDT 24
Peak memory 199852 kb
Host smart-d732ea89-643d-402a-ba2e-53ab7ecb7de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462622112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2462622112
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.84242163
Short name T565
Test name
Test status
Simulation time 53492042 ps
CPU time 1.64 seconds
Started Jul 22 06:59:07 PM PDT 24
Finished Jul 22 06:59:17 PM PDT 24
Peak memory 199868 kb
Host smart-393464ad-b313-4b52-b7cf-f9aa1062f088
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84242163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.84242163
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.747198812
Short name T559
Test name
Test status
Simulation time 17071165 ps
CPU time 0.6 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:00:46 PM PDT 24
Peak memory 194748 kb
Host smart-7adc7c8d-15fd-451e-8fa2-6d466169fc3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747198812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.747198812
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3557427787
Short name T627
Test name
Test status
Simulation time 25122096 ps
CPU time 0.61 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 193972 kb
Host smart-ddd2e7ce-d36b-4c99-8bca-bf886c8289b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557427787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3557427787
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3952669701
Short name T575
Test name
Test status
Simulation time 35667050 ps
CPU time 0.59 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194828 kb
Host smart-c1ac0fa0-d178-4bec-a4f3-430a526d444a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952669701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3952669701
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2545047272
Short name T614
Test name
Test status
Simulation time 23820188 ps
CPU time 0.58 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:38 PM PDT 24
Peak memory 194732 kb
Host smart-bc87e3b8-4218-48f5-a9c1-c6fdbe61dbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545047272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2545047272
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.644186897
Short name T608
Test name
Test status
Simulation time 11662076 ps
CPU time 0.59 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194764 kb
Host smart-e48d6c45-7c90-4d95-b725-853707b5f02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644186897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.644186897
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.877413648
Short name T578
Test name
Test status
Simulation time 49007808 ps
CPU time 0.59 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 194788 kb
Host smart-0c78339f-a11a-480d-907a-c240f740d861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877413648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.877413648
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1928951787
Short name T557
Test name
Test status
Simulation time 37688094 ps
CPU time 0.58 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 06:59:51 PM PDT 24
Peak memory 194728 kb
Host smart-1762cc53-60e1-480d-970f-74afe8faebb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928951787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1928951787
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4102797726
Short name T567
Test name
Test status
Simulation time 23060783 ps
CPU time 0.63 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194872 kb
Host smart-95f6738c-c003-4336-8a55-cb1814cf4ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102797726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4102797726
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.505663570
Short name T537
Test name
Test status
Simulation time 11611867 ps
CPU time 0.61 seconds
Started Jul 22 06:59:21 PM PDT 24
Finished Jul 22 06:59:37 PM PDT 24
Peak memory 194840 kb
Host smart-172b5cd7-38db-472e-8a37-64301aaaa947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505663570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.505663570
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2116344371
Short name T604
Test name
Test status
Simulation time 12304914 ps
CPU time 0.6 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194760 kb
Host smart-820c3942-8fae-4e82-9064-cf0c340c9c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116344371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2116344371
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3452089961
Short name T122
Test name
Test status
Simulation time 2623983193 ps
CPU time 3.41 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:10 PM PDT 24
Peak memory 199880 kb
Host smart-03c4da9d-08c3-4030-bdf3-ebb36cf2d36d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452089961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3452089961
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1057939620
Short name T592
Test name
Test status
Simulation time 431868989 ps
CPU time 9.48 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:14 PM PDT 24
Peak memory 199860 kb
Host smart-fa3ca5c2-a81c-438c-a176-2e8050c92e02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057939620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1057939620
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.521422358
Short name T648
Test name
Test status
Simulation time 51674165 ps
CPU time 0.78 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 198132 kb
Host smart-16b72eaf-9d1c-49fd-964b-0ee7955ec386
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521422358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.521422358
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4022654612
Short name T589
Test name
Test status
Simulation time 939748639 ps
CPU time 1.68 seconds
Started Jul 22 06:59:20 PM PDT 24
Finished Jul 22 06:59:36 PM PDT 24
Peak memory 199892 kb
Host smart-5c4824df-f930-4e1b-90e6-f7cdb7ace5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022654612 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.4022654612
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3827768979
Short name T123
Test name
Test status
Simulation time 91140564 ps
CPU time 0.82 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 199676 kb
Host smart-ee817620-eab3-4657-98af-7a02480f541b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827768979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3827768979
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3344861602
Short name T633
Test name
Test status
Simulation time 35953156 ps
CPU time 0.58 seconds
Started Jul 22 06:59:04 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 194672 kb
Host smart-307a341f-6b77-45f4-bd9c-c5298241a5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344861602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3344861602
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3765501567
Short name T622
Test name
Test status
Simulation time 172139773 ps
CPU time 2.03 seconds
Started Jul 22 06:59:08 PM PDT 24
Finished Jul 22 06:59:19 PM PDT 24
Peak memory 199804 kb
Host smart-e7925a03-40a8-407f-8052-cd2f5ea47fef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765501567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3765501567
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1756538232
Short name T624
Test name
Test status
Simulation time 58353480 ps
CPU time 1.7 seconds
Started Jul 22 06:58:58 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 199824 kb
Host smart-8c70edfe-d597-4aa4-adda-dfe47711107d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756538232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1756538232
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3702504628
Short name T143
Test name
Test status
Simulation time 667757855 ps
CPU time 3.13 seconds
Started Jul 22 06:59:20 PM PDT 24
Finished Jul 22 06:59:38 PM PDT 24
Peak memory 199936 kb
Host smart-afc79167-674c-4424-80c3-24140d1d327c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702504628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3702504628
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1963269242
Short name T638
Test name
Test status
Simulation time 18760728 ps
CPU time 0.63 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 194848 kb
Host smart-5560e766-6c0f-4b2c-954e-550efb31601b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963269242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1963269242
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.576915307
Short name T572
Test name
Test status
Simulation time 13271976 ps
CPU time 0.61 seconds
Started Jul 22 07:00:14 PM PDT 24
Finished Jul 22 07:00:30 PM PDT 24
Peak memory 194748 kb
Host smart-64686cbe-9362-4a2d-b4a6-e11e186e1d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576915307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.576915307
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3350062878
Short name T597
Test name
Test status
Simulation time 16558674 ps
CPU time 0.6 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194896 kb
Host smart-9cdeee3d-83b7-418e-a55f-9a9d11cca31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350062878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3350062878
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3453067907
Short name T530
Test name
Test status
Simulation time 50297925 ps
CPU time 0.61 seconds
Started Jul 22 06:59:40 PM PDT 24
Finished Jul 22 06:59:56 PM PDT 24
Peak memory 194876 kb
Host smart-b88241bf-e36a-4574-948b-1ba051a63857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453067907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3453067907
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1035314933
Short name T542
Test name
Test status
Simulation time 15422923 ps
CPU time 0.6 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:37 PM PDT 24
Peak memory 194848 kb
Host smart-c6f6ee57-7f19-47aa-a350-4cf442bdefc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035314933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1035314933
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1826966866
Short name T641
Test name
Test status
Simulation time 49373237 ps
CPU time 0.62 seconds
Started Jul 22 06:59:27 PM PDT 24
Finished Jul 22 06:59:44 PM PDT 24
Peak memory 194800 kb
Host smart-fbf850cf-ac95-47c7-a7b9-ca347b13b3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826966866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1826966866
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.406988678
Short name T531
Test name
Test status
Simulation time 89437279 ps
CPU time 0.6 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194800 kb
Host smart-3755f012-82cc-4fc4-989a-85b76c5c35f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406988678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.406988678
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3137156669
Short name T643
Test name
Test status
Simulation time 43149989 ps
CPU time 0.57 seconds
Started Jul 22 06:59:28 PM PDT 24
Finished Jul 22 06:59:45 PM PDT 24
Peak memory 194756 kb
Host smart-696e5fc4-f1ff-4c73-9966-a1cbe9d2bf31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137156669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3137156669
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2594978850
Short name T574
Test name
Test status
Simulation time 48235129 ps
CPU time 0.64 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:43 PM PDT 24
Peak memory 194748 kb
Host smart-a7ee7780-8113-4db6-8f58-d24de0b435af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594978850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2594978850
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.801983854
Short name T549
Test name
Test status
Simulation time 10795507 ps
CPU time 0.57 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194720 kb
Host smart-ab542f08-5fb0-42ac-ba78-154d5fb5a782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801983854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.801983854
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.350638980
Short name T657
Test name
Test status
Simulation time 643855881 ps
CPU time 3.29 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 199892 kb
Host smart-302be8c3-06c3-47e0-b39e-37d46c35022e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350638980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.350638980
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1733438219
Short name T120
Test name
Test status
Simulation time 1542071366 ps
CPU time 14.48 seconds
Started Jul 22 06:59:08 PM PDT 24
Finished Jul 22 06:59:32 PM PDT 24
Peak memory 199880 kb
Host smart-1712375a-3120-4730-ae11-8bacc7b3db8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733438219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1733438219
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4016307586
Short name T529
Test name
Test status
Simulation time 27152244 ps
CPU time 0.74 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 06:59:54 PM PDT 24
Peak memory 198244 kb
Host smart-afe3a330-fc2a-4c21-af3c-4ac93e33a16e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016307586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4016307586
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3677744558
Short name T588
Test name
Test status
Simulation time 618246635 ps
CPU time 2.27 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:45 PM PDT 24
Peak memory 199996 kb
Host smart-f0401e5e-3491-4d1d-bc62-7bb6975eee09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677744558 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3677744558
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1814038729
Short name T568
Test name
Test status
Simulation time 13797174 ps
CPU time 0.6 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 194776 kb
Host smart-64ec40c3-5d87-4cfb-b913-711626953a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814038729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1814038729
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3212639082
Short name T128
Test name
Test status
Simulation time 44445353 ps
CPU time 1.11 seconds
Started Jul 22 06:59:08 PM PDT 24
Finished Jul 22 06:59:17 PM PDT 24
Peak memory 198316 kb
Host smart-ed070e7a-b92b-4398-947f-b1d80b5ecaf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212639082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3212639082
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.741410825
Short name T590
Test name
Test status
Simulation time 222073919 ps
CPU time 2 seconds
Started Jul 22 06:59:08 PM PDT 24
Finished Jul 22 06:59:19 PM PDT 24
Peak memory 199844 kb
Host smart-66021067-4dfc-4113-826a-02ef77b2d904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741410825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.741410825
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3310606283
Short name T603
Test name
Test status
Simulation time 106108397 ps
CPU time 2.83 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:36 PM PDT 24
Peak memory 199880 kb
Host smart-694890da-e45b-4b1a-a0d5-890a1bd87f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310606283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3310606283
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1990003645
Short name T577
Test name
Test status
Simulation time 16990946 ps
CPU time 0.66 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:44 PM PDT 24
Peak memory 194896 kb
Host smart-67df5069-1f10-42bd-9372-67bd6829bdb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990003645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1990003645
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2761189397
Short name T536
Test name
Test status
Simulation time 51953790 ps
CPU time 0.58 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:41 PM PDT 24
Peak memory 194788 kb
Host smart-66e367c4-78ce-4474-be6b-05651143e245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761189397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2761189397
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3544444543
Short name T541
Test name
Test status
Simulation time 13721765 ps
CPU time 0.58 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:00:47 PM PDT 24
Peak memory 194876 kb
Host smart-12ec0763-a016-40aa-8cab-20bacfe55120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544444543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3544444543
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3577586937
Short name T553
Test name
Test status
Simulation time 101995715 ps
CPU time 0.62 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194812 kb
Host smart-dfbf4dfc-54c2-49e0-ba06-25da8461891f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577586937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3577586937
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2397821307
Short name T554
Test name
Test status
Simulation time 212850048 ps
CPU time 0.62 seconds
Started Jul 22 06:59:27 PM PDT 24
Finished Jul 22 06:59:44 PM PDT 24
Peak memory 194912 kb
Host smart-4237382f-a846-42ff-a80a-a40ca97c4124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397821307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2397821307
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1740176787
Short name T649
Test name
Test status
Simulation time 35781429 ps
CPU time 0.59 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:48 PM PDT 24
Peak memory 194740 kb
Host smart-578c6edd-5451-476f-a96b-15ed231599db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740176787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1740176787
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3495629029
Short name T546
Test name
Test status
Simulation time 32517587 ps
CPU time 0.58 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 193832 kb
Host smart-3b8f526b-3ab1-4a79-b8ed-073be6eabcc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495629029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3495629029
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3897029551
Short name T584
Test name
Test status
Simulation time 14994535 ps
CPU time 0.6 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 194876 kb
Host smart-7b9d919a-a42f-4a1a-99ea-fc5730bf3fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897029551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3897029551
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4080583256
Short name T651
Test name
Test status
Simulation time 28975186 ps
CPU time 0.61 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:38 PM PDT 24
Peak memory 194792 kb
Host smart-21d1045d-42fc-483a-b574-87e9f82a048a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080583256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4080583256
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.649540563
Short name T587
Test name
Test status
Simulation time 50710051 ps
CPU time 0.64 seconds
Started Jul 22 06:59:26 PM PDT 24
Finished Jul 22 06:59:43 PM PDT 24
Peak memory 194812 kb
Host smart-c2b259dd-347e-4d08-b30a-02c8c73083e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649540563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.649540563
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2262462261
Short name T630
Test name
Test status
Simulation time 93592712 ps
CPU time 2.97 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:29 PM PDT 24
Peak memory 199936 kb
Host smart-ae219362-dd5b-46dd-8ec6-444d8e72de76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262462261 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2262462261
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.777071506
Short name T534
Test name
Test status
Simulation time 24484175 ps
CPU time 0.81 seconds
Started Jul 22 06:59:12 PM PDT 24
Finished Jul 22 06:59:21 PM PDT 24
Peak memory 199012 kb
Host smart-42d4c18a-bfbc-4a11-80c5-7891b43c5ca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777071506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.777071506
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1214821915
Short name T535
Test name
Test status
Simulation time 13616840 ps
CPU time 0.58 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 194696 kb
Host smart-6bc43c8b-b673-4a72-ad9d-548f6afb97a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214821915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1214821915
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4191997816
Short name T631
Test name
Test status
Simulation time 254066062 ps
CPU time 1.67 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:23 PM PDT 24
Peak memory 199876 kb
Host smart-e16e74ac-2920-4682-9108-85b5db92bb3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191997816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4191997816
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.848918636
Short name T644
Test name
Test status
Simulation time 120263334 ps
CPU time 3.5 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:36 PM PDT 24
Peak memory 199888 kb
Host smart-aa6c8776-dfcf-4d1a-b52d-a3ce1e756314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848918636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.848918636
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1309850773
Short name T552
Test name
Test status
Simulation time 1830428442 ps
CPU time 1.82 seconds
Started Jul 22 07:00:24 PM PDT 24
Finished Jul 22 07:00:41 PM PDT 24
Peak memory 199840 kb
Host smart-7166d412-e2ad-4d72-9713-0d675c6c1d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309850773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1309850773
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3022383399
Short name T555
Test name
Test status
Simulation time 144011006 ps
CPU time 1.18 seconds
Started Jul 22 06:59:12 PM PDT 24
Finished Jul 22 06:59:22 PM PDT 24
Peak memory 199752 kb
Host smart-b8adf49c-81f8-4f5c-af41-7c7953b638d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022383399 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3022383399
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4247017513
Short name T131
Test name
Test status
Simulation time 20233414 ps
CPU time 0.68 seconds
Started Jul 22 06:59:22 PM PDT 24
Finished Jul 22 06:59:39 PM PDT 24
Peak memory 197488 kb
Host smart-c80b8ae8-6a57-4365-9e29-5ef887951737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247017513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4247017513
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2483212885
Short name T602
Test name
Test status
Simulation time 11819448 ps
CPU time 0.63 seconds
Started Jul 22 06:59:18 PM PDT 24
Finished Jul 22 06:59:31 PM PDT 24
Peak memory 194780 kb
Host smart-b730480d-b043-4e89-a99d-4c59704f0c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483212885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2483212885
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.462808900
Short name T634
Test name
Test status
Simulation time 87072581 ps
CPU time 1.74 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:43 PM PDT 24
Peak memory 199864 kb
Host smart-3d1436bd-4d18-408f-b5a9-025431945cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462808900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.462808900
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3790155461
Short name T573
Test name
Test status
Simulation time 140609346 ps
CPU time 2.96 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 199888 kb
Host smart-dacf520a-16b2-48fa-8248-0ecfa82895e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790155461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3790155461
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.951520346
Short name T144
Test name
Test status
Simulation time 162394250 ps
CPU time 3.19 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:00:16 PM PDT 24
Peak memory 199812 kb
Host smart-aea8b162-c25f-4ec2-be85-6e2c1df8984b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951520346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.951520346
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1078043878
Short name T596
Test name
Test status
Simulation time 67663287 ps
CPU time 1.9 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:50 PM PDT 24
Peak memory 199876 kb
Host smart-9b430a92-364f-4dcc-bf00-2ec423c942c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078043878 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1078043878
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1962734356
Short name T556
Test name
Test status
Simulation time 23806297 ps
CPU time 0.81 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 06:59:48 PM PDT 24
Peak memory 199420 kb
Host smart-26b3ff50-e20e-4768-812f-be543f4d79de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962734356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1962734356
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3131498137
Short name T539
Test name
Test status
Simulation time 16680193 ps
CPU time 0.68 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 194780 kb
Host smart-f185370a-81d9-45f6-8cef-0e79ce15308f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131498137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3131498137
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3755831619
Short name T616
Test name
Test status
Simulation time 897428459 ps
CPU time 1.76 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:28 PM PDT 24
Peak memory 199692 kb
Host smart-4ce5e1ee-71d3-43ad-bb70-f3b66157f3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755831619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3755831619
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1284644735
Short name T94
Test name
Test status
Simulation time 330349442 ps
CPU time 3.17 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 199836 kb
Host smart-5de66871-fc0d-4090-a088-825541d31fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284644735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1284644735
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1690060558
Short name T620
Test name
Test status
Simulation time 3489499761 ps
CPU time 4.23 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 06:59:30 PM PDT 24
Peak memory 199888 kb
Host smart-3a1547ad-20d7-4221-92a4-c92869b5f6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690060558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1690060558
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.512847459
Short name T562
Test name
Test status
Simulation time 49034663 ps
CPU time 1.31 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 199928 kb
Host smart-e0f7df63-4c28-4ad7-b726-3214c66f3b69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512847459 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.512847459
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.173101161
Short name T112
Test name
Test status
Simulation time 45092442 ps
CPU time 0.83 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 06:59:42 PM PDT 24
Peak memory 199524 kb
Host smart-43946c74-afb3-44d6-8640-004d9af4fa68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173101161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.173101161
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2352228009
Short name T595
Test name
Test status
Simulation time 21686708 ps
CPU time 0.62 seconds
Started Jul 22 06:59:18 PM PDT 24
Finished Jul 22 06:59:31 PM PDT 24
Peak memory 194736 kb
Host smart-f43a7cd1-5e66-4457-9a57-a4a02bce0f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352228009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2352228009
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2689348630
Short name T129
Test name
Test status
Simulation time 383542243 ps
CPU time 1.69 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 199836 kb
Host smart-d59325f0-ed84-4ceb-ac0e-a4c732761467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689348630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2689348630
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.84500465
Short name T547
Test name
Test status
Simulation time 166022995 ps
CPU time 1.69 seconds
Started Jul 22 06:59:18 PM PDT 24
Finished Jul 22 06:59:32 PM PDT 24
Peak memory 199676 kb
Host smart-fb029b41-d191-4387-a728-5079279e0ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84500465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.84500465
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.175305700
Short name T75
Test name
Test status
Simulation time 192219810 ps
CPU time 3.04 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:35 PM PDT 24
Peak memory 199948 kb
Host smart-225610ce-5e38-45ab-8f17-b23e984df48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175305700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.175305700
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1029834730
Short name T571
Test name
Test status
Simulation time 189498324 ps
CPU time 2.43 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 200172 kb
Host smart-92d69962-7db8-4684-ae4a-c96a4703b3ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029834730 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1029834730
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2892474609
Short name T561
Test name
Test status
Simulation time 24901483 ps
CPU time 0.81 seconds
Started Jul 22 06:59:12 PM PDT 24
Finished Jul 22 06:59:21 PM PDT 24
Peak memory 199092 kb
Host smart-df6fa8ed-40b4-414e-aa84-de314709caf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892474609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2892474609
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1144098368
Short name T593
Test name
Test status
Simulation time 69077747 ps
CPU time 0.61 seconds
Started Jul 22 06:59:13 PM PDT 24
Finished Jul 22 06:59:23 PM PDT 24
Peak memory 194824 kb
Host smart-9cd60a86-0ec3-48a3-b53f-6f220c59bf2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144098368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1144098368
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2078595059
Short name T580
Test name
Test status
Simulation time 431472324 ps
CPU time 1.76 seconds
Started Jul 22 06:59:28 PM PDT 24
Finished Jul 22 06:59:46 PM PDT 24
Peak memory 199876 kb
Host smart-6b7671aa-1dc4-4f75-abc4-e1f4a029c771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078595059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2078595059
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3921097723
Short name T637
Test name
Test status
Simulation time 186298170 ps
CPU time 1.17 seconds
Started Jul 22 06:59:12 PM PDT 24
Finished Jul 22 06:59:22 PM PDT 24
Peak memory 198788 kb
Host smart-1872ddb8-d30f-421f-af39-e0623e4da8ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921097723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3921097723
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.903003507
Short name T138
Test name
Test status
Simulation time 228911566 ps
CPU time 4.42 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:43 PM PDT 24
Peak memory 199924 kb
Host smart-eaaa7888-a2f5-49a2-bedd-d9342b0be588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903003507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.903003507
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4137407379
Short name T475
Test name
Test status
Simulation time 17170650 ps
CPU time 0.62 seconds
Started Jul 22 06:27:34 PM PDT 24
Finished Jul 22 06:27:36 PM PDT 24
Peak memory 196152 kb
Host smart-c7dd593a-513f-4323-84b0-5050d49328e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137407379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4137407379
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.311315867
Short name T329
Test name
Test status
Simulation time 6003014290 ps
CPU time 83.85 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:29:01 PM PDT 24
Peak memory 216652 kb
Host smart-561a60ff-f0b6-44ab-a537-9434c789aa2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311315867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.311315867
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.979805832
Short name T365
Test name
Test status
Simulation time 11226934988 ps
CPU time 49.21 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:28:23 PM PDT 24
Peak memory 216860 kb
Host smart-fe62eafb-4a6b-4656-b014-8bce2d81b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979805832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.979805832
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.817244655
Short name T216
Test name
Test status
Simulation time 16356798564 ps
CPU time 771.12 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:40:27 PM PDT 24
Peak memory 702704 kb
Host smart-a62ce47a-865b-4ea5-9d74-9979df606d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817244655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.817244655
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1660474796
Short name T440
Test name
Test status
Simulation time 800617600 ps
CPU time 41.36 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:28:17 PM PDT 24
Peak memory 200268 kb
Host smart-cfab633d-5d70-4a52-a599-8b3d0d6c9bd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660474796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1660474796
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.223083460
Short name T456
Test name
Test status
Simulation time 45177844297 ps
CPU time 148.2 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:29:57 PM PDT 24
Peak memory 200372 kb
Host smart-7b87cc9d-dc35-46ba-b5fe-ab83eb9d9103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223083460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.223083460
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2527952075
Short name T60
Test name
Test status
Simulation time 623788553 ps
CPU time 0.93 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:27:29 PM PDT 24
Peak memory 218588 kb
Host smart-042bb6d4-7d6e-4cfc-869d-fd8a41818070
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527952075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2527952075
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2652955019
Short name T348
Test name
Test status
Simulation time 282910144 ps
CPU time 12.21 seconds
Started Jul 22 06:27:27 PM PDT 24
Finished Jul 22 06:27:39 PM PDT 24
Peak memory 200252 kb
Host smart-fc282e28-8ec2-4dde-8d2a-89d0d9d263ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652955019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2652955019
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1487569536
Short name T79
Test name
Test status
Simulation time 17085508272 ps
CPU time 591.73 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:37:31 PM PDT 24
Peak memory 701208 kb
Host smart-27c3f9d7-5e79-4aa4-bc4e-b4d62ff95e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487569536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1487569536
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.596854796
Short name T377
Test name
Test status
Simulation time 6638314273 ps
CPU time 66.44 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:28:37 PM PDT 24
Peak memory 200348 kb
Host smart-a68feea4-fd16-4488-a9dd-fdcc4cdb7ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=596854796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.596854796
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4106750601
Short name T64
Test name
Test status
Simulation time 9731508540 ps
CPU time 109.74 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:29:21 PM PDT 24
Peak memory 200248 kb
Host smart-29556c21-00f3-413d-9a31-e0e1343143ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4106750601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4106750601
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3328443881
Short name T194
Test name
Test status
Simulation time 9428443996 ps
CPU time 76.3 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:28:47 PM PDT 24
Peak memory 200348 kb
Host smart-1dd6fc59-c1ab-4ac2-9fde-4c0dac287186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3328443881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3328443881
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.381148487
Short name T397
Test name
Test status
Simulation time 268183847956 ps
CPU time 2382.02 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 07:07:16 PM PDT 24
Peak memory 215616 kb
Host smart-3120a47e-0da4-4730-8542-e8d6cb27bd09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=381148487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.381148487
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3700355371
Short name T438
Test name
Test status
Simulation time 215138635908 ps
CPU time 2752.94 seconds
Started Jul 22 06:27:34 PM PDT 24
Finished Jul 22 07:13:29 PM PDT 24
Peak memory 216680 kb
Host smart-030cb539-0317-43c1-aa4d-a4674f25a2f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3700355371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3700355371
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.646604563
Short name T102
Test name
Test status
Simulation time 4655972833 ps
CPU time 125.54 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:29:41 PM PDT 24
Peak memory 200316 kb
Host smart-d16bb17d-b03a-4230-be7b-fcfd84de5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646604563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.646604563
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2701475286
Short name T464
Test name
Test status
Simulation time 18979749 ps
CPU time 0.54 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:27:38 PM PDT 24
Peak memory 195784 kb
Host smart-cb254626-2cb8-4735-a33e-3f20cf03dcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701475286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2701475286
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1616313184
Short name T172
Test name
Test status
Simulation time 1061665486 ps
CPU time 29.93 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:28:01 PM PDT 24
Peak memory 200224 kb
Host smart-b4ff40a2-2cdc-4fa0-8889-817907e34968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616313184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1616313184
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3003341878
Short name T220
Test name
Test status
Simulation time 676827059 ps
CPU time 10.03 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:27:47 PM PDT 24
Peak memory 200288 kb
Host smart-52569db2-248c-4409-8921-d463767b9105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003341878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3003341878
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2755252816
Short name T233
Test name
Test status
Simulation time 889692575 ps
CPU time 102.16 seconds
Started Jul 22 06:27:34 PM PDT 24
Finished Jul 22 06:29:17 PM PDT 24
Peak memory 352300 kb
Host smart-6beca555-f170-4a6d-95a0-e242ea805633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755252816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2755252816
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3928534836
Short name T171
Test name
Test status
Simulation time 5128177965 ps
CPU time 91.52 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:29:51 PM PDT 24
Peak memory 200300 kb
Host smart-d03a2f18-faa9-41f8-8c75-c5c9f99ffcd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928534836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3928534836
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4204208694
Short name T230
Test name
Test status
Simulation time 38574740234 ps
CPU time 114.09 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:28 PM PDT 24
Peak memory 200468 kb
Host smart-23a03348-e3b8-4042-899a-526cc05f79bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204208694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4204208694
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.131639523
Short name T63
Test name
Test status
Simulation time 145771177 ps
CPU time 0.97 seconds
Started Jul 22 06:27:26 PM PDT 24
Finished Jul 22 06:27:27 PM PDT 24
Peak memory 219612 kb
Host smart-cf9554b5-45a2-4b9d-bf33-a0d7756862b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131639523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.131639523
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2600942159
Short name T380
Test name
Test status
Simulation time 204224097 ps
CPU time 2.71 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:27:31 PM PDT 24
Peak memory 200216 kb
Host smart-d15b4431-20e3-44ef-b588-94bfcc9701fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600942159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2600942159
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1794525738
Short name T198
Test name
Test status
Simulation time 15549272995 ps
CPU time 43.71 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:28:15 PM PDT 24
Peak memory 200276 kb
Host smart-c55513ce-9541-4bfa-a72c-b2ea63179c88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1794525738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1794525738
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2602793827
Short name T356
Test name
Test status
Simulation time 6739518552 ps
CPU time 110.2 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:25 PM PDT 24
Peak memory 200296 kb
Host smart-2f0461a3-e4e8-4e73-962a-791e0102433c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2602793827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2602793827
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1944351183
Short name T426
Test name
Test status
Simulation time 34294265595 ps
CPU time 139.29 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:29:53 PM PDT 24
Peak memory 200276 kb
Host smart-708d3635-e4b1-49a6-8769-f0a402c8ba3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944351183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1944351183
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3431000083
Short name T370
Test name
Test status
Simulation time 144817242924 ps
CPU time 632.15 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:38:03 PM PDT 24
Peak memory 200368 kb
Host smart-63e45f59-71e9-4bea-afb8-a5f5f6b2e27c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3431000083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3431000083
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3383836928
Short name T296
Test name
Test status
Simulation time 312468334831 ps
CPU time 2548.95 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 07:10:10 PM PDT 24
Peak memory 215904 kb
Host smart-493a461d-4d9b-46ff-adbb-edc1064939ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3383836928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3383836928
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2474891129
Short name T344
Test name
Test status
Simulation time 149472785130 ps
CPU time 2161.75 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 07:03:34 PM PDT 24
Peak memory 216372 kb
Host smart-5f30fb6a-0a2b-49bf-a48e-48aa3e9f6e5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474891129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2474891129
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.825426469
Short name T373
Test name
Test status
Simulation time 643562616 ps
CPU time 2.58 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:27:39 PM PDT 24
Peak memory 200280 kb
Host smart-848271b1-fd6d-4f69-9e92-0478455ba979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825426469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.825426469
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2907214220
Short name T285
Test name
Test status
Simulation time 65105545 ps
CPU time 0.56 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 196204 kb
Host smart-9019c718-6fd1-4a96-ada5-4f9617cafffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907214220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2907214220
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3349690202
Short name T284
Test name
Test status
Simulation time 5147689364 ps
CPU time 69.17 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:28:50 PM PDT 24
Peak memory 208552 kb
Host smart-95984413-cb43-4e81-8a1a-f590345dd057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349690202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3349690202
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.767987679
Short name T445
Test name
Test status
Simulation time 736893523 ps
CPU time 40.6 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:28:21 PM PDT 24
Peak memory 200248 kb
Host smart-aab0dcfc-95a1-488c-868e-ebe8641b4781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767987679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.767987679
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3333196947
Short name T201
Test name
Test status
Simulation time 21115323570 ps
CPU time 1013.82 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:44:39 PM PDT 24
Peak memory 699900 kb
Host smart-555c9a95-aa0f-40b1-98a6-3779718c9fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333196947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3333196947
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3722141114
Short name T203
Test name
Test status
Simulation time 1273796754 ps
CPU time 23.88 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:09 PM PDT 24
Peak memory 200184 kb
Host smart-55a60dd4-df4c-4722-8a8e-523e5214a2b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722141114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3722141114
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2267927476
Short name T467
Test name
Test status
Simulation time 5836116710 ps
CPU time 20.64 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:28:06 PM PDT 24
Peak memory 200304 kb
Host smart-2edcbf87-912e-44d1-bbc0-c581b8a59ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267927476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2267927476
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1366079792
Short name T508
Test name
Test status
Simulation time 1679382041 ps
CPU time 5.15 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:49 PM PDT 24
Peak memory 200280 kb
Host smart-c1dd0b76-2055-480c-b9b0-9d2b29d3107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366079792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1366079792
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1716635725
Short name T388
Test name
Test status
Simulation time 87045775645 ps
CPU time 826.72 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:41:31 PM PDT 24
Peak memory 711604 kb
Host smart-f6d16aeb-abdb-414e-bc8c-460feb3dc580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716635725 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1716635725
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1090006491
Short name T316
Test name
Test status
Simulation time 9556842302 ps
CPU time 37.3 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:22 PM PDT 24
Peak memory 200164 kb
Host smart-07f35cc6-524d-48f3-8f1a-313306bcf472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090006491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1090006491
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2497325748
Short name T16
Test name
Test status
Simulation time 29867729 ps
CPU time 0.57 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 195572 kb
Host smart-9e77101e-7085-4494-9bb3-1891b07b4f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497325748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2497325748
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3183071516
Short name T415
Test name
Test status
Simulation time 695185476 ps
CPU time 12.29 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:01 PM PDT 24
Peak memory 200232 kb
Host smart-470856ff-3b66-437d-8880-fd15179302b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183071516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3183071516
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2952072663
Short name T297
Test name
Test status
Simulation time 337094153 ps
CPU time 1.11 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:27:33 PM PDT 24
Peak memory 200168 kb
Host smart-31a95bbd-2d1a-4dbd-8e82-b74594f128be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952072663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2952072663
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1867485801
Short name T305
Test name
Test status
Simulation time 14847714289 ps
CPU time 1226.35 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:48:14 PM PDT 24
Peak memory 746864 kb
Host smart-fb5e4776-ef0f-4c95-8649-c09d7bab6e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867485801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1867485801
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1942346282
Short name T162
Test name
Test status
Simulation time 603379914 ps
CPU time 15.87 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:01 PM PDT 24
Peak memory 200208 kb
Host smart-0ecaeb34-fb8e-48b1-b434-61c5ab20d44a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942346282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1942346282
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.100078667
Short name T161
Test name
Test status
Simulation time 50954677034 ps
CPU time 161.63 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:30:22 PM PDT 24
Peak memory 200312 kb
Host smart-e6f14b48-e823-4f22-8bfc-33cf09844b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100078667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.100078667
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.898286448
Short name T248
Test name
Test status
Simulation time 1839772605 ps
CPU time 14.5 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:58 PM PDT 24
Peak memory 200288 kb
Host smart-135938b5-6da2-4407-b1a7-e49cf8fc60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898286448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.898286448
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3624553776
Short name T386
Test name
Test status
Simulation time 87923938547 ps
CPU time 2005.71 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 07:01:07 PM PDT 24
Peak memory 739328 kb
Host smart-bb8386f4-f5f2-4522-ab4f-6aec7365ac12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624553776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3624553776
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.564388173
Short name T260
Test name
Test status
Simulation time 4185201066 ps
CPU time 94.96 seconds
Started Jul 22 06:27:39 PM PDT 24
Finished Jul 22 06:29:15 PM PDT 24
Peak memory 200316 kb
Host smart-7b8ad3f4-e5c1-4d61-976c-3535ec8b1519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564388173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.564388173
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.15303123
Short name T342
Test name
Test status
Simulation time 41966346 ps
CPU time 0.58 seconds
Started Jul 22 06:27:52 PM PDT 24
Finished Jul 22 06:27:53 PM PDT 24
Peak memory 195128 kb
Host smart-5efe012b-0b25-4d09-af76-6ac9bf9a9cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15303123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.15303123
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3710902772
Short name T319
Test name
Test status
Simulation time 55716833 ps
CPU time 2.19 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 200244 kb
Host smart-a1f61c12-b6fb-412b-81ac-087feeef16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710902772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3710902772
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1880324707
Short name T449
Test name
Test status
Simulation time 2990185913 ps
CPU time 391.9 seconds
Started Jul 22 06:28:39 PM PDT 24
Finished Jul 22 06:35:12 PM PDT 24
Peak memory 650460 kb
Host smart-7f70b3b1-e460-4dd3-8031-147d41297253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880324707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1880324707
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1897643380
Short name T351
Test name
Test status
Simulation time 3520025014 ps
CPU time 99.54 seconds
Started Jul 22 06:27:45 PM PDT 24
Finished Jul 22 06:29:26 PM PDT 24
Peak memory 200264 kb
Host smart-a09c2994-00c4-4364-a6b7-6489955152e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897643380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1897643380
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3442893486
Short name T332
Test name
Test status
Simulation time 5431462597 ps
CPU time 102.04 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:29:30 PM PDT 24
Peak memory 200072 kb
Host smart-2034e30f-8d7b-49b4-81fa-ad6d9b606191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442893486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3442893486
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1278792583
Short name T308
Test name
Test status
Simulation time 202165853 ps
CPU time 9.06 seconds
Started Jul 22 06:27:39 PM PDT 24
Finished Jul 22 06:27:48 PM PDT 24
Peak memory 200248 kb
Host smart-1ffc926c-02bd-4c69-b9b6-3829bd80cacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278792583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1278792583
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2432540910
Short name T111
Test name
Test status
Simulation time 989935994 ps
CPU time 15.54 seconds
Started Jul 22 06:27:39 PM PDT 24
Finished Jul 22 06:27:55 PM PDT 24
Peak memory 200544 kb
Host smart-a61cb893-9143-4885-ad87-809ff65953af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432540910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2432540910
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2838340738
Short name T49
Test name
Test status
Simulation time 6296894535 ps
CPU time 118.76 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:29:43 PM PDT 24
Peak memory 200288 kb
Host smart-5d935319-af7a-4934-8cf6-edc8cfc80494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838340738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2838340738
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2265871056
Short name T257
Test name
Test status
Simulation time 21971338 ps
CPU time 0.56 seconds
Started Jul 22 06:27:45 PM PDT 24
Finished Jul 22 06:27:46 PM PDT 24
Peak memory 196148 kb
Host smart-7ec1e348-4a24-4a1f-bc9c-458943ae13f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265871056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2265871056
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1576700741
Short name T13
Test name
Test status
Simulation time 4163495609 ps
CPU time 60.13 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:45 PM PDT 24
Peak memory 200268 kb
Host smart-6adf4811-0e38-4713-bfa5-5dd81777f4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576700741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1576700741
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3596849101
Short name T263
Test name
Test status
Simulation time 661315843 ps
CPU time 3.33 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:27:47 PM PDT 24
Peak memory 200248 kb
Host smart-3c2f9d92-1e04-4a8f-aed8-b02a93edb6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596849101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3596849101
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2061732998
Short name T306
Test name
Test status
Simulation time 4613747281 ps
CPU time 381.48 seconds
Started Jul 22 06:27:46 PM PDT 24
Finished Jul 22 06:34:09 PM PDT 24
Peak memory 615084 kb
Host smart-b0d11276-8f81-488e-ada7-69e7592e2a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061732998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2061732998
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2817239638
Short name T447
Test name
Test status
Simulation time 53195475461 ps
CPU time 236.35 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:31:39 PM PDT 24
Peak memory 200296 kb
Host smart-9d27419b-ae6b-4ab8-8693-7cc07515899f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817239638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2817239638
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1580595461
Short name T366
Test name
Test status
Simulation time 23802174979 ps
CPU time 106.17 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:29:29 PM PDT 24
Peak memory 200512 kb
Host smart-5b05cf18-3245-40a7-ba36-a277d6fe18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580595461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1580595461
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1317509135
Short name T418
Test name
Test status
Simulation time 782808359 ps
CPU time 8.57 seconds
Started Jul 22 06:27:45 PM PDT 24
Finished Jul 22 06:27:55 PM PDT 24
Peak memory 200212 kb
Host smart-9a9bed39-969a-42af-9107-16c657d53443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317509135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1317509135
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.4060712329
Short name T18
Test name
Test status
Simulation time 24630557 ps
CPU time 0.66 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:27:46 PM PDT 24
Peak memory 195900 kb
Host smart-da1dd421-9870-45c8-927e-936a290e3e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060712329 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.4060712329
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2849876060
Short name T428
Test name
Test status
Simulation time 25685857733 ps
CPU time 72.11 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200292 kb
Host smart-0b6ee171-00e8-4aaa-9fe1-75b33427cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849876060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2849876060
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2023969531
Short name T205
Test name
Test status
Simulation time 22154837 ps
CPU time 0.58 seconds
Started Jul 22 06:27:50 PM PDT 24
Finished Jul 22 06:27:51 PM PDT 24
Peak memory 195164 kb
Host smart-28f3271f-3344-4960-b8c5-38fc3a3010b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023969531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2023969531
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2807105549
Short name T236
Test name
Test status
Simulation time 592624959 ps
CPU time 18.33 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:06 PM PDT 24
Peak memory 200264 kb
Host smart-3e12c9f6-561f-42fe-b362-52b8077dc8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807105549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2807105549
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.615956792
Short name T210
Test name
Test status
Simulation time 2362845250 ps
CPU time 42.73 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:31 PM PDT 24
Peak memory 200340 kb
Host smart-31d138f0-1025-48e0-a3bf-bf260e92a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615956792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.615956792
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.387157492
Short name T287
Test name
Test status
Simulation time 2648949056 ps
CPU time 572.73 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:37:21 PM PDT 24
Peak memory 713108 kb
Host smart-a7063d31-397c-4b18-832a-bbd157f3c379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387157492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.387157492
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2961330663
Short name T335
Test name
Test status
Simulation time 9089174243 ps
CPU time 30.98 seconds
Started Jul 22 06:28:40 PM PDT 24
Finished Jul 22 06:29:12 PM PDT 24
Peak memory 200340 kb
Host smart-4f13a219-65c7-4a3a-83f2-fa4210c40abe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961330663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2961330663
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2955787879
Short name T72
Test name
Test status
Simulation time 23771831315 ps
CPU time 51.39 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:39 PM PDT 24
Peak memory 200324 kb
Host smart-b4d1af8e-2d7c-47d4-863e-98233c64729e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955787879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2955787879
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3302212779
Short name T262
Test name
Test status
Simulation time 41742019 ps
CPU time 1.98 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:27:50 PM PDT 24
Peak memory 200276 kb
Host smart-c375c856-eb0c-4030-b04b-e12570fa9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302212779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3302212779
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1342762593
Short name T156
Test name
Test status
Simulation time 95288666967 ps
CPU time 3422.19 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 07:24:51 PM PDT 24
Peak memory 821936 kb
Host smart-91caf53c-88f3-46ff-920a-b5e996786114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342762593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1342762593
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4156390361
Short name T419
Test name
Test status
Simulation time 28960855255 ps
CPU time 21.14 seconds
Started Jul 22 06:27:58 PM PDT 24
Finished Jul 22 06:28:20 PM PDT 24
Peak memory 200320 kb
Host smart-1feae069-bb98-43b7-a2f3-de1c0bb20ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156390361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4156390361
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2792123221
Short name T321
Test name
Test status
Simulation time 27941484 ps
CPU time 0.57 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:29:41 PM PDT 24
Peak memory 196024 kb
Host smart-43c62d8e-4324-40cd-a1dc-6893e35686a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792123221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2792123221
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3527876806
Short name T432
Test name
Test status
Simulation time 3037634079 ps
CPU time 82.04 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:29:13 PM PDT 24
Peak memory 200308 kb
Host smart-b536c092-b2d6-458f-b35f-c15c9c1fa3e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527876806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3527876806
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.120316512
Short name T520
Test name
Test status
Simulation time 4968669997 ps
CPU time 48.08 seconds
Started Jul 22 06:28:40 PM PDT 24
Finished Jul 22 06:29:29 PM PDT 24
Peak memory 208544 kb
Host smart-6c93e441-080b-4c36-b652-9832c6acd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120316512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.120316512
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3735939095
Short name T106
Test name
Test status
Simulation time 6082370520 ps
CPU time 540.41 seconds
Started Jul 22 06:28:44 PM PDT 24
Finished Jul 22 06:37:45 PM PDT 24
Peak memory 675508 kb
Host smart-e6095b02-f5c8-4348-8d90-48094fe3d2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735939095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3735939095
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2990014159
Short name T247
Test name
Test status
Simulation time 43528295398 ps
CPU time 200.2 seconds
Started Jul 22 06:28:09 PM PDT 24
Finished Jul 22 06:31:29 PM PDT 24
Peak memory 200252 kb
Host smart-6568e9ac-fa8e-41a3-a31a-75d08a2f7570
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990014159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2990014159
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.936301086
Short name T259
Test name
Test status
Simulation time 2966344906 ps
CPU time 161.39 seconds
Started Jul 22 06:28:13 PM PDT 24
Finished Jul 22 06:30:55 PM PDT 24
Peak memory 200292 kb
Host smart-13bc3019-a4fa-4598-b130-a54f20b26fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936301086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.936301086
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1869567117
Short name T252
Test name
Test status
Simulation time 975355861 ps
CPU time 8.7 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:28:27 PM PDT 24
Peak memory 200244 kb
Host smart-1982fba9-38c5-4ad9-8164-6e56f5a05d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869567117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1869567117
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1837634835
Short name T391
Test name
Test status
Simulation time 61783317336 ps
CPU time 1512.78 seconds
Started Jul 22 06:28:35 PM PDT 24
Finished Jul 22 06:53:49 PM PDT 24
Peak memory 755976 kb
Host smart-08374076-442f-49ba-8d40-6ffff0c0e129
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837634835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1837634835
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.983081775
Short name T107
Test name
Test status
Simulation time 68568689051 ps
CPU time 124.34 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:29:50 PM PDT 24
Peak memory 200300 kb
Host smart-73f6e8c8-6700-4a0d-bffe-c46a226123c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983081775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.983081775
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2123414280
Short name T328
Test name
Test status
Simulation time 24736995 ps
CPU time 0.58 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 196168 kb
Host smart-c55152ea-988d-4b31-93d6-7a6af6282db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123414280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2123414280
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2621188788
Short name T504
Test name
Test status
Simulation time 23063802294 ps
CPU time 68.93 seconds
Started Jul 22 06:27:58 PM PDT 24
Finished Jul 22 06:29:08 PM PDT 24
Peak memory 216756 kb
Host smart-f774ef08-81ef-41b7-95a3-8e4b37f8506e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621188788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2621188788
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2007716368
Short name T155
Test name
Test status
Simulation time 508718001 ps
CPU time 28.38 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:28:17 PM PDT 24
Peak memory 200188 kb
Host smart-cf4832d2-b799-422d-8cef-9e69497d9680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007716368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2007716368
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.713555927
Short name T519
Test name
Test status
Simulation time 4735593687 ps
CPU time 838.82 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:41:48 PM PDT 24
Peak memory 720628 kb
Host smart-9e7d6581-2781-4587-8cef-dcf4450f2b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713555927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.713555927
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1559059998
Short name T250
Test name
Test status
Simulation time 3067798381 ps
CPU time 161.49 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:30:31 PM PDT 24
Peak memory 200256 kb
Host smart-a8dc088d-afb0-4637-9a10-b43b5012adbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559059998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1559059998
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.373210119
Short name T292
Test name
Test status
Simulation time 4149116263 ps
CPU time 103.61 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:29:31 PM PDT 24
Peak memory 200388 kb
Host smart-8e6a40f1-6fa9-43db-8223-972d731ad6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373210119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.373210119
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1204950278
Short name T103
Test name
Test status
Simulation time 1463201296 ps
CPU time 6.38 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:27:52 PM PDT 24
Peak memory 200292 kb
Host smart-d252cf49-7775-4736-a0a4-7e1247c2d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204950278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1204950278
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3580853157
Short name T6
Test name
Test status
Simulation time 9826950742 ps
CPU time 44.82 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:28:35 PM PDT 24
Peak memory 200332 kb
Host smart-bd93f968-97c5-49f2-a9ae-98391ea042a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580853157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3580853157
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.694089033
Short name T167
Test name
Test status
Simulation time 101307934 ps
CPU time 0.6 seconds
Started Jul 22 06:28:02 PM PDT 24
Finished Jul 22 06:28:03 PM PDT 24
Peak memory 195172 kb
Host smart-e30cbb1d-e246-4614-8931-281d3ff9c3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694089033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.694089033
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2675289992
Short name T497
Test name
Test status
Simulation time 1399854961 ps
CPU time 21.99 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:28:14 PM PDT 24
Peak memory 200024 kb
Host smart-67cef5a7-e78b-46f5-b22f-efe81c4c8949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675289992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2675289992
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.130806920
Short name T359
Test name
Test status
Simulation time 2640278093 ps
CPU time 13.41 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:28:03 PM PDT 24
Peak memory 200324 kb
Host smart-1fa93f4b-161b-4812-bb9b-085911c85440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130806920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.130806920
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2047549325
Short name T494
Test name
Test status
Simulation time 13026096823 ps
CPU time 478.26 seconds
Started Jul 22 06:27:55 PM PDT 24
Finished Jul 22 06:35:53 PM PDT 24
Peak memory 687180 kb
Host smart-14dad656-321b-456d-a49b-4a93971572e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047549325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2047549325
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.187535121
Short name T421
Test name
Test status
Simulation time 34821135829 ps
CPU time 106.37 seconds
Started Jul 22 06:27:57 PM PDT 24
Finished Jul 22 06:29:44 PM PDT 24
Peak memory 200296 kb
Host smart-b32deb0f-c3c6-4e12-a751-0927d6e9e112
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187535121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.187535121
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4040528018
Short name T175
Test name
Test status
Simulation time 2146947903 ps
CPU time 119.03 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:29:49 PM PDT 24
Peak memory 200184 kb
Host smart-1fd1ced9-7ed2-4b01-ad0f-81d33c562084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040528018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4040528018
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.863538239
Short name T491
Test name
Test status
Simulation time 1378361306 ps
CPU time 8.28 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:27:57 PM PDT 24
Peak memory 200252 kb
Host smart-45d2e1b2-e1de-48df-ba7d-b274c8056a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863538239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.863538239
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.896634405
Short name T463
Test name
Test status
Simulation time 26649185324 ps
CPU time 475 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:35:38 PM PDT 24
Peak memory 446560 kb
Host smart-5006407f-f76f-401b-9c39-70cbceaf080d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896634405 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.896634405
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3608694263
Short name T465
Test name
Test status
Simulation time 1664225627 ps
CPU time 24.3 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 200188 kb
Host smart-8117b098-ffb4-49e9-8e13-4d6071e023b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608694263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3608694263
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.326780621
Short name T459
Test name
Test status
Simulation time 44069622 ps
CPU time 0.62 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:27:42 PM PDT 24
Peak memory 196204 kb
Host smart-7c82850f-4ac1-4d5a-9438-df23cd0dc2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326780621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.326780621
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2301628050
Short name T206
Test name
Test status
Simulation time 206356453 ps
CPU time 8.81 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:28:00 PM PDT 24
Peak memory 200296 kb
Host smart-6b8a5011-baec-4ed1-83ec-918d799d45dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301628050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2301628050
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1984098978
Short name T439
Test name
Test status
Simulation time 5341107043 ps
CPU time 67.75 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:52 PM PDT 24
Peak memory 200448 kb
Host smart-cde8054b-0f38-450d-bdfa-3842742988b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984098978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1984098978
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.671235260
Short name T427
Test name
Test status
Simulation time 2114897366 ps
CPU time 309.45 seconds
Started Jul 22 06:27:52 PM PDT 24
Finished Jul 22 06:33:02 PM PDT 24
Peak memory 623404 kb
Host smart-4df683b1-3bab-441d-ac3c-a593581f7266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671235260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.671235260
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3414964514
Short name T487
Test name
Test status
Simulation time 1885028901 ps
CPU time 95.94 seconds
Started Jul 22 06:27:54 PM PDT 24
Finished Jul 22 06:29:31 PM PDT 24
Peak memory 200232 kb
Host smart-0314ee4a-5321-42fb-b4f2-03b9b6319ea8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414964514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3414964514
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2260715711
Short name T489
Test name
Test status
Simulation time 3875288720 ps
CPU time 69.71 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:29:02 PM PDT 24
Peak memory 200384 kb
Host smart-e09e30a1-a3af-405c-80a9-5215aec8b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260715711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2260715711
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2032869446
Short name T275
Test name
Test status
Simulation time 822433756 ps
CPU time 11.54 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:06 PM PDT 24
Peak memory 200236 kb
Host smart-2b3463a9-6b35-4b12-8697-70ef658a22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032869446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2032869446
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3094114028
Short name T336
Test name
Test status
Simulation time 15632571704 ps
CPU time 1201.31 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:47:51 PM PDT 24
Peak memory 724980 kb
Host smart-c6078feb-7137-4520-8d15-3de586c71ad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094114028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3094114028
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2002873030
Short name T163
Test name
Test status
Simulation time 1502602496 ps
CPU time 22.45 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:28:08 PM PDT 24
Peak memory 200276 kb
Host smart-5e30ec8b-360b-4338-a2d1-931d8f8ed896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002873030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2002873030
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2397380418
Short name T478
Test name
Test status
Simulation time 83821334 ps
CPU time 0.57 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:27:50 PM PDT 24
Peak memory 195188 kb
Host smart-afb5986f-7b6e-4c7f-a794-c0e2cdbceb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397380418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2397380418
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2443135812
Short name T38
Test name
Test status
Simulation time 13073416862 ps
CPU time 54.87 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:49 PM PDT 24
Peak memory 200312 kb
Host smart-0647b348-d3e8-4749-8e45-45bf52ce72b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443135812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2443135812
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.977239743
Short name T317
Test name
Test status
Simulation time 10681372705 ps
CPU time 72.53 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:29:01 PM PDT 24
Peak memory 200340 kb
Host smart-5ae65fe3-5eeb-4490-8bd7-8e80274d2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977239743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.977239743
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2360818033
Short name T214
Test name
Test status
Simulation time 384094743 ps
CPU time 16.37 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:28:00 PM PDT 24
Peak memory 236036 kb
Host smart-9dbdc49a-0dc1-4bd8-aa6c-3f30ee78d01e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360818033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2360818033
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2129920091
Short name T505
Test name
Test status
Simulation time 18273789354 ps
CPU time 151.53 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:30:53 PM PDT 24
Peak memory 200228 kb
Host smart-df17a226-97ab-4300-813b-f57e4fff35b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129920091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2129920091
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_smoke.2570931683
Short name T493
Test name
Test status
Simulation time 4097776189 ps
CPU time 11.93 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:06 PM PDT 24
Peak memory 200332 kb
Host smart-b6c463d7-3ae6-4e4f-9466-0ff1f016a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570931683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2570931683
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3205462155
Short name T293
Test name
Test status
Simulation time 19087199468 ps
CPU time 1110.07 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:46:18 PM PDT 24
Peak memory 692428 kb
Host smart-9a32695f-244c-4595-8ed3-aa993d3ebf81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205462155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3205462155
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1979190672
Short name T133
Test name
Test status
Simulation time 35438373980 ps
CPU time 119.22 seconds
Started Jul 22 06:27:54 PM PDT 24
Finished Jul 22 06:29:54 PM PDT 24
Peak memory 200296 kb
Host smart-4d1bb8e6-ba68-4034-869b-751a2672633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979190672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1979190672
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3499787610
Short name T46
Test name
Test status
Simulation time 37527876 ps
CPU time 0.6 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:27:38 PM PDT 24
Peak memory 196852 kb
Host smart-1922f89e-e998-4215-a9cd-809b938ce5b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499787610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3499787610
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2803290702
Short name T381
Test name
Test status
Simulation time 1754287963 ps
CPU time 48.28 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:28:24 PM PDT 24
Peak memory 200228 kb
Host smart-18b6d1ec-613e-4dec-af39-28e3e7b9ffdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803290702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2803290702
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.184288054
Short name T267
Test name
Test status
Simulation time 8148957100 ps
CPU time 31.6 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:28:56 PM PDT 24
Peak memory 200348 kb
Host smart-2cf5d2e2-3c4a-4260-bd44-f77967e4c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184288054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.184288054
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3089580682
Short name T249
Test name
Test status
Simulation time 5958194395 ps
CPU time 436.95 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:34:53 PM PDT 24
Peak memory 630728 kb
Host smart-22729fa9-0d85-4f7a-aaaf-c6ca26ae0224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089580682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3089580682
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.817887321
Short name T52
Test name
Test status
Simulation time 3725336660 ps
CPU time 106.89 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:29:16 PM PDT 24
Peak memory 200336 kb
Host smart-7d58bafd-f0b6-4bed-82ea-4c8f055c7531
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817887321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.817887321
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.881445249
Short name T343
Test name
Test status
Simulation time 51108621791 ps
CPU time 189.32 seconds
Started Jul 22 06:27:35 PM PDT 24
Finished Jul 22 06:30:45 PM PDT 24
Peak memory 216672 kb
Host smart-bd3fbe5c-2d02-46a2-9f05-9d97f31cfdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881445249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.881445249
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.464506246
Short name T61
Test name
Test status
Simulation time 120232749 ps
CPU time 0.77 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:27:33 PM PDT 24
Peak memory 218500 kb
Host smart-474e1085-e284-420d-958f-b17311d389ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464506246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.464506246
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.582148034
Short name T434
Test name
Test status
Simulation time 1529752857 ps
CPU time 10.64 seconds
Started Jul 22 06:27:29 PM PDT 24
Finished Jul 22 06:27:40 PM PDT 24
Peak memory 200244 kb
Host smart-9e954773-d97e-4d8a-bf53-fb6e6953ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582148034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.582148034
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1563993352
Short name T318
Test name
Test status
Simulation time 38253759441 ps
CPU time 1489.74 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:52:21 PM PDT 24
Peak memory 709720 kb
Host smart-365003cb-1697-4ef2-9c61-6591e865b2b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563993352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1563993352
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1919132757
Short name T23
Test name
Test status
Simulation time 694507619521 ps
CPU time 4220.82 seconds
Started Jul 22 06:27:37 PM PDT 24
Finished Jul 22 07:37:59 PM PDT 24
Peak memory 783284 kb
Host smart-9f449e7d-025d-4074-a894-571d5973cd72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919132757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1919132757
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2674600758
Short name T202
Test name
Test status
Simulation time 6129824433 ps
CPU time 66.24 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:28:45 PM PDT 24
Peak memory 200340 kb
Host smart-b9daf637-f7f5-45d5-b402-48b272df0a0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2674600758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2674600758
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3185435725
Short name T174
Test name
Test status
Simulation time 8736174363 ps
CPU time 106.97 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:21 PM PDT 24
Peak memory 200252 kb
Host smart-f919560d-abc2-42c4-a28f-b2362a796ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3185435725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3185435725
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1150405851
Short name T303
Test name
Test status
Simulation time 30468526612 ps
CPU time 116.93 seconds
Started Jul 22 06:27:27 PM PDT 24
Finished Jul 22 06:29:25 PM PDT 24
Peak memory 200268 kb
Host smart-a42320f3-645b-41a7-8f5b-c64f4f342758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1150405851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1150405851
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1647455241
Short name T251
Test name
Test status
Simulation time 35283645064 ps
CPU time 589.83 seconds
Started Jul 22 06:27:31 PM PDT 24
Finished Jul 22 06:37:21 PM PDT 24
Peak memory 200308 kb
Host smart-a90497ec-9dd1-4ec7-be89-3ba1958b2fb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1647455241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1647455241
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1391785117
Short name T403
Test name
Test status
Simulation time 758985970984 ps
CPU time 2566.93 seconds
Started Jul 22 06:27:27 PM PDT 24
Finished Jul 22 07:10:15 PM PDT 24
Peak memory 215768 kb
Host smart-f040bec6-066f-4f2b-8d3e-7f9f8465b86c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391785117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1391785117
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3298964591
Short name T334
Test name
Test status
Simulation time 165478639263 ps
CPU time 2262.39 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 07:05:21 PM PDT 24
Peak memory 215748 kb
Host smart-fac42692-3c36-4699-b390-eb0d95a22118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3298964591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3298964591
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1781798757
Short name T341
Test name
Test status
Simulation time 5396190213 ps
CPU time 70.11 seconds
Started Jul 22 06:27:37 PM PDT 24
Finished Jul 22 06:28:48 PM PDT 24
Peak memory 200296 kb
Host smart-39b75cec-2d29-42c9-9bd6-9bb0229af06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781798757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1781798757
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4292932289
Short name T238
Test name
Test status
Simulation time 13509597 ps
CPU time 0.57 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 06:27:50 PM PDT 24
Peak memory 195748 kb
Host smart-336ed5d0-1bf3-4306-9223-2b2bbd6ec644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292932289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4292932289
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.759133523
Short name T361
Test name
Test status
Simulation time 664508349 ps
CPU time 19.52 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:28:12 PM PDT 24
Peak memory 200296 kb
Host smart-14f17108-5a32-4ee0-bdec-ff392736f98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759133523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.759133523
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3155337179
Short name T158
Test name
Test status
Simulation time 5130733637 ps
CPU time 33.77 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:28 PM PDT 24
Peak memory 200336 kb
Host smart-1bff74cf-dde0-4d2e-9a9d-9a0cd20fb210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155337179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3155337179
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2666843747
Short name T182
Test name
Test status
Simulation time 12178689894 ps
CPU time 516.33 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:36:28 PM PDT 24
Peak memory 509224 kb
Host smart-45ade839-2b11-4f11-ad68-3dfcdd436b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666843747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2666843747
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1314638027
Short name T509
Test name
Test status
Simulation time 2606006340 ps
CPU time 33.33 seconds
Started Jul 22 06:28:05 PM PDT 24
Finished Jul 22 06:28:39 PM PDT 24
Peak memory 200268 kb
Host smart-823c4197-2aef-425d-90b2-a96344e28a40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314638027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1314638027
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.327607703
Short name T298
Test name
Test status
Simulation time 8508187310 ps
CPU time 23.29 seconds
Started Jul 22 06:27:51 PM PDT 24
Finished Jul 22 06:28:15 PM PDT 24
Peak memory 200312 kb
Host smart-fb1c8d55-adee-4e96-a8c3-4828c93bc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327607703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.327607703
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1468838557
Short name T442
Test name
Test status
Simulation time 221830560 ps
CPU time 2.12 seconds
Started Jul 22 06:27:56 PM PDT 24
Finished Jul 22 06:27:59 PM PDT 24
Peak memory 200248 kb
Host smart-822205b3-84b7-4dac-b1ce-77c352d714f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468838557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1468838557
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1771832365
Short name T160
Test name
Test status
Simulation time 201405651038 ps
CPU time 1025.58 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:44:56 PM PDT 24
Peak memory 234004 kb
Host smart-3a654461-36db-49b1-a64d-c15037693576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771832365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1771832365
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.689711297
Short name T302
Test name
Test status
Simulation time 41316514314 ps
CPU time 124.45 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:29:46 PM PDT 24
Peak memory 200308 kb
Host smart-8fc0b15b-807d-4fb9-93d1-e91c95572fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689711297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.689711297
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2706030101
Short name T188
Test name
Test status
Simulation time 16019072 ps
CPU time 0.62 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 196168 kb
Host smart-13c9e9d4-542f-4a33-8c29-dbebd7f2aac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706030101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2706030101
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2878067872
Short name T70
Test name
Test status
Simulation time 3914347832 ps
CPU time 63.67 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:30:45 PM PDT 24
Peak memory 200324 kb
Host smart-8c2ec508-a8da-420b-83a1-9d1240371553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878067872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2878067872
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3714403970
Short name T279
Test name
Test status
Simulation time 5622210719 ps
CPU time 30.85 seconds
Started Jul 22 06:28:11 PM PDT 24
Finished Jul 22 06:28:42 PM PDT 24
Peak memory 200372 kb
Host smart-14b8d844-4dea-4763-8042-1146f4cae433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714403970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3714403970
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3806444459
Short name T485
Test name
Test status
Simulation time 6754040472 ps
CPU time 1256.63 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:48:51 PM PDT 24
Peak memory 702776 kb
Host smart-08935508-a3d7-49ab-895a-a80b84fb5b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806444459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3806444459
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3492036848
Short name T48
Test name
Test status
Simulation time 62817985836 ps
CPU time 220.92 seconds
Started Jul 22 06:27:55 PM PDT 24
Finished Jul 22 06:31:37 PM PDT 24
Peak memory 200340 kb
Host smart-e905c75b-80f2-4321-bb0e-6fd17de57226
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492036848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3492036848
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_smoke.2140130357
Short name T213
Test name
Test status
Simulation time 2059787016 ps
CPU time 9.04 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:28:03 PM PDT 24
Peak memory 200296 kb
Host smart-5781e3c3-377e-4ae9-8d18-e74c5ed81891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140130357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2140130357
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3045408877
Short name T150
Test name
Test status
Simulation time 374624983885 ps
CPU time 4594 seconds
Started Jul 22 06:27:48 PM PDT 24
Finished Jul 22 07:44:24 PM PDT 24
Peak memory 841424 kb
Host smart-ccd66bba-fd32-42d9-a181-a8777d38c813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045408877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3045408877
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2027738739
Short name T286
Test name
Test status
Simulation time 23713188047 ps
CPU time 102.88 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:30:09 PM PDT 24
Peak memory 200324 kb
Host smart-5f595fc4-ca83-482a-9bbb-0e3ad469a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027738739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2027738739
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3464270997
Short name T376
Test name
Test status
Simulation time 23071936 ps
CPU time 0.57 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:27:51 PM PDT 24
Peak memory 196200 kb
Host smart-45aa3859-5363-455e-8efb-30cb155e657a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464270997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3464270997
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2331430291
Short name T243
Test name
Test status
Simulation time 157985277 ps
CPU time 8.86 seconds
Started Jul 22 06:27:46 PM PDT 24
Finished Jul 22 06:27:55 PM PDT 24
Peak memory 200272 kb
Host smart-82bbf3a9-5f1d-467b-8161-6c5594d33a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331430291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2331430291
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1123235395
Short name T383
Test name
Test status
Simulation time 2969350148 ps
CPU time 51.27 seconds
Started Jul 22 06:27:58 PM PDT 24
Finished Jul 22 06:28:50 PM PDT 24
Peak memory 200328 kb
Host smart-ee40344d-b57a-471c-a1c5-12ba44a2bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123235395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1123235395
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3630351757
Short name T56
Test name
Test status
Simulation time 5291234373 ps
CPU time 946.37 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:44:03 PM PDT 24
Peak memory 672108 kb
Host smart-25e123e2-eb28-4f70-b9a5-7d1518a498a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630351757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3630351757
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2557076781
Short name T320
Test name
Test status
Simulation time 9013602338 ps
CPU time 139.67 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:32:01 PM PDT 24
Peak memory 200256 kb
Host smart-4298a98f-762e-463a-9624-403228f8fded
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557076781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2557076781
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2632596783
Short name T510
Test name
Test status
Simulation time 18918138840 ps
CPU time 168.54 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:30:43 PM PDT 24
Peak memory 200312 kb
Host smart-eb689c84-72db-44bd-b709-4a324690ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632596783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2632596783
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3793507248
Short name T149
Test name
Test status
Simulation time 1226824784 ps
CPU time 5.29 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:27:53 PM PDT 24
Peak memory 200236 kb
Host smart-365d6bb5-d4ea-4d63-80c3-4022df7fd8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793507248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3793507248
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2054700880
Short name T40
Test name
Test status
Simulation time 22346205079 ps
CPU time 1566.1 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:54:14 PM PDT 24
Peak memory 753976 kb
Host smart-9ffa5c4c-bbf6-4aac-a80e-9d91e95af2ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054700880 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2054700880
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.704061078
Short name T99
Test name
Test status
Simulation time 26736729226 ps
CPU time 93.63 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:29:49 PM PDT 24
Peak memory 200336 kb
Host smart-a23997d1-e853-4dec-8949-a18b0a9a719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704061078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.704061078
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.160428771
Short name T265
Test name
Test status
Simulation time 25366043 ps
CPU time 0.56 seconds
Started Jul 22 06:27:53 PM PDT 24
Finished Jul 22 06:27:55 PM PDT 24
Peak memory 196144 kb
Host smart-b83b4ece-99b9-48f6-8461-1e908e34755e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160428771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.160428771
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.819899412
Short name T360
Test name
Test status
Simulation time 1676590704 ps
CPU time 85.52 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 200220 kb
Host smart-b785a5cc-c0e0-471b-b439-4c02be1f13a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819899412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.819899412
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1931007414
Short name T289
Test name
Test status
Simulation time 21008512406 ps
CPU time 46.02 seconds
Started Jul 22 06:30:01 PM PDT 24
Finished Jul 22 06:30:48 PM PDT 24
Peak memory 200236 kb
Host smart-6600e7cb-717e-48aa-af05-5f0b193aba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931007414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1931007414
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.980719621
Short name T169
Test name
Test status
Simulation time 3427112431 ps
CPU time 564.44 seconds
Started Jul 22 06:28:40 PM PDT 24
Finished Jul 22 06:38:05 PM PDT 24
Peak memory 639336 kb
Host smart-af75951b-2c31-4769-ac8d-8792d554ffda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980719621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.980719621
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3562115257
Short name T68
Test name
Test status
Simulation time 35074627981 ps
CPU time 134.05 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:30:31 PM PDT 24
Peak memory 200292 kb
Host smart-6d69a489-bc57-4bfc-8c53-8e82f27390ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562115257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3562115257
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2974414206
Short name T184
Test name
Test status
Simulation time 33570888586 ps
CPU time 149.55 seconds
Started Jul 22 06:28:01 PM PDT 24
Finished Jul 22 06:30:32 PM PDT 24
Peak memory 200568 kb
Host smart-48179871-5c89-43ed-9538-a9360d36132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974414206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2974414206
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3689188155
Short name T355
Test name
Test status
Simulation time 120412840 ps
CPU time 5.52 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:27:56 PM PDT 24
Peak memory 200232 kb
Host smart-8d43d654-7bb9-4cbd-a100-ea7f26c18b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689188155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3689188155
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3013824915
Short name T404
Test name
Test status
Simulation time 87242583148 ps
CPU time 1628.54 seconds
Started Jul 22 06:28:00 PM PDT 24
Finished Jul 22 06:55:09 PM PDT 24
Peak memory 703728 kb
Host smart-4bf13413-538c-4dfd-94f9-90250b162747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013824915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3013824915
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4015123391
Short name T282
Test name
Test status
Simulation time 1946816064 ps
CPU time 36.15 seconds
Started Jul 22 06:28:00 PM PDT 24
Finished Jul 22 06:28:36 PM PDT 24
Peak memory 200300 kb
Host smart-1395fe5b-3429-4e7a-b960-76981da0f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015123391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4015123391
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3691758415
Short name T85
Test name
Test status
Simulation time 14865179 ps
CPU time 0.61 seconds
Started Jul 22 06:28:04 PM PDT 24
Finished Jul 22 06:28:05 PM PDT 24
Peak memory 196204 kb
Host smart-5f28b66f-0917-45f0-a2fa-a6ce80232e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691758415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3691758415
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3324403167
Short name T492
Test name
Test status
Simulation time 907700012 ps
CPU time 14.95 seconds
Started Jul 22 06:28:08 PM PDT 24
Finished Jul 22 06:28:24 PM PDT 24
Peak memory 200244 kb
Host smart-a6585b21-459a-48c0-9715-9716ca235867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324403167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3324403167
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.185008942
Short name T338
Test name
Test status
Simulation time 7263736766 ps
CPU time 19.43 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:28:27 PM PDT 24
Peak memory 200348 kb
Host smart-cd68ded7-21f8-4e27-a37b-242b70361a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185008942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.185008942
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2088738663
Short name T412
Test name
Test status
Simulation time 1165360223 ps
CPU time 205.78 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:31:43 PM PDT 24
Peak memory 592000 kb
Host smart-016d8a8b-5edb-4ef2-9398-caab3bff9dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088738663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2088738663
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.716977626
Short name T517
Test name
Test status
Simulation time 6468146969 ps
CPU time 76.93 seconds
Started Jul 22 06:28:02 PM PDT 24
Finished Jul 22 06:29:19 PM PDT 24
Peak memory 200300 kb
Host smart-3bba40da-79a5-4cd1-b265-15fb47a94a2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716977626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.716977626
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1297370764
Short name T215
Test name
Test status
Simulation time 38792762584 ps
CPU time 47.15 seconds
Started Jul 22 06:28:06 PM PDT 24
Finished Jul 22 06:28:53 PM PDT 24
Peak memory 200292 kb
Host smart-28c4c196-e481-46d5-8bfd-c5a8b3d6a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297370764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1297370764
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2986169866
Short name T408
Test name
Test status
Simulation time 1946792972 ps
CPU time 6.84 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:28:24 PM PDT 24
Peak memory 200256 kb
Host smart-02d72a00-726e-4d34-88d5-e895a30187a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986169866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2986169866
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3749206305
Short name T382
Test name
Test status
Simulation time 4166478191 ps
CPU time 13.3 seconds
Started Jul 22 06:28:04 PM PDT 24
Finished Jul 22 06:28:18 PM PDT 24
Peak memory 200316 kb
Host smart-14eb539d-4760-44ba-8252-9eb417746da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749206305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3749206305
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.247401724
Short name T294
Test name
Test status
Simulation time 127583007 ps
CPU time 0.58 seconds
Started Jul 22 06:27:49 PM PDT 24
Finished Jul 22 06:27:51 PM PDT 24
Peak memory 195844 kb
Host smart-fbd4c51c-04ea-4ae1-a2d5-8474d5eaa2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247401724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.247401724
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2532568826
Short name T506
Test name
Test status
Simulation time 5018491448 ps
CPU time 68.52 seconds
Started Jul 22 06:29:40 PM PDT 24
Finished Jul 22 06:30:49 PM PDT 24
Peak memory 200316 kb
Host smart-ff530c52-ad42-4aec-b1aa-bd6b98971c4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532568826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2532568826
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3247800507
Short name T416
Test name
Test status
Simulation time 1772934774 ps
CPU time 34.43 seconds
Started Jul 22 06:28:24 PM PDT 24
Finished Jul 22 06:28:59 PM PDT 24
Peak memory 200248 kb
Host smart-35a0df03-4ec4-45c8-90a3-7b3e14346b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247800507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3247800507
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.997461490
Short name T448
Test name
Test status
Simulation time 2269171528 ps
CPU time 63.08 seconds
Started Jul 22 06:30:01 PM PDT 24
Finished Jul 22 06:31:05 PM PDT 24
Peak memory 325356 kb
Host smart-042da15d-dff3-4ce1-a95b-6720a2f06a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997461490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.997461490
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.124135715
Short name T237
Test name
Test status
Simulation time 4671148742 ps
CPU time 61.98 seconds
Started Jul 22 06:28:01 PM PDT 24
Finished Jul 22 06:29:03 PM PDT 24
Peak memory 200224 kb
Host smart-ad94fca0-b928-4bef-a9a6-5727729bd82f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124135715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.124135715
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3252982651
Short name T322
Test name
Test status
Simulation time 6218488442 ps
CPU time 99.04 seconds
Started Jul 22 06:27:57 PM PDT 24
Finished Jul 22 06:29:36 PM PDT 24
Peak memory 216624 kb
Host smart-82726cba-7cba-4a5f-943e-0fe7a5bce49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252982651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3252982651
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4187407384
Short name T375
Test name
Test status
Simulation time 2949369289 ps
CPU time 10.38 seconds
Started Jul 22 06:28:08 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 200364 kb
Host smart-95977c0d-57e5-41c8-879d-7b6a31046a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187407384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4187407384
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2625990952
Short name T462
Test name
Test status
Simulation time 10058409239 ps
CPU time 49.61 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:28:57 PM PDT 24
Peak memory 200312 kb
Host smart-dfdcaf68-f02a-451e-87b4-852dee96e5a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625990952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2625990952
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.48205504
Short name T371
Test name
Test status
Simulation time 62832397157 ps
CPU time 72.47 seconds
Started Jul 22 06:28:01 PM PDT 24
Finished Jul 22 06:29:14 PM PDT 24
Peak memory 200328 kb
Host smart-a00dac92-e1d3-48a1-8049-4c9f7babdbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48205504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.48205504
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4166003040
Short name T245
Test name
Test status
Simulation time 11113904 ps
CPU time 0.62 seconds
Started Jul 22 06:30:01 PM PDT 24
Finished Jul 22 06:30:03 PM PDT 24
Peak memory 195104 kb
Host smart-72436c0a-d8cb-4eea-846b-1115f6df4bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166003040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4166003040
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2695149621
Short name T521
Test name
Test status
Simulation time 21528424300 ps
CPU time 64.14 seconds
Started Jul 22 06:27:58 PM PDT 24
Finished Jul 22 06:29:02 PM PDT 24
Peak memory 200560 kb
Host smart-546135d9-3407-4228-9fe6-7841a47ac765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695149621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2695149621
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.745840600
Short name T270
Test name
Test status
Simulation time 13124496741 ps
CPU time 65.56 seconds
Started Jul 22 06:28:02 PM PDT 24
Finished Jul 22 06:29:08 PM PDT 24
Peak memory 208520 kb
Host smart-31fa189e-2455-43dd-b960-848e9afcb844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745840600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.745840600
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1538024813
Short name T291
Test name
Test status
Simulation time 29425472 ps
CPU time 0.72 seconds
Started Jul 22 06:27:55 PM PDT 24
Finished Jul 22 06:27:57 PM PDT 24
Peak memory 198544 kb
Host smart-343cf4ca-397b-4018-99ca-2f123d4c7b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538024813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1538024813
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.876292664
Short name T315
Test name
Test status
Simulation time 11015160931 ps
CPU time 137.31 seconds
Started Jul 22 06:28:04 PM PDT 24
Finished Jul 22 06:30:22 PM PDT 24
Peak memory 200268 kb
Host smart-66407fdc-7dcc-4b75-8919-59578e945574
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876292664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.876292664
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1414707346
Short name T364
Test name
Test status
Simulation time 3438639715 ps
CPU time 16.4 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:28:30 PM PDT 24
Peak memory 200252 kb
Host smart-283c5f30-f95b-4802-b584-430a971194b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414707346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1414707346
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2820310
Short name T481
Test name
Test status
Simulation time 128973906 ps
CPU time 3.23 seconds
Started Jul 22 06:28:08 PM PDT 24
Finished Jul 22 06:28:12 PM PDT 24
Peak memory 200304 kb
Host smart-742887b9-7d7a-40b3-9cd9-f789788d8ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2820310
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2377468220
Short name T42
Test name
Test status
Simulation time 71500244571 ps
CPU time 216.31 seconds
Started Jul 22 06:28:03 PM PDT 24
Finished Jul 22 06:31:40 PM PDT 24
Peak memory 411848 kb
Host smart-c91e66cf-4dfc-4270-acb7-5ae66f6dce00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377468220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2377468220
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1954133689
Short name T101
Test name
Test status
Simulation time 812751916 ps
CPU time 44.95 seconds
Started Jul 22 06:28:12 PM PDT 24
Finished Jul 22 06:28:58 PM PDT 24
Peak memory 200244 kb
Host smart-16065c37-5482-4e2b-8678-4f92bb16efbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954133689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1954133689
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1530603561
Short name T514
Test name
Test status
Simulation time 13293630 ps
CPU time 0.61 seconds
Started Jul 22 06:28:13 PM PDT 24
Finished Jul 22 06:28:14 PM PDT 24
Peak memory 196868 kb
Host smart-f5986dc6-2e12-4050-a103-9c12fd0c1ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530603561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1530603561
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2472367693
Short name T417
Test name
Test status
Simulation time 3806070334 ps
CPU time 109.35 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:30:06 PM PDT 24
Peak memory 200476 kb
Host smart-ba27fc60-d149-475e-98ee-c19fcbbc2787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472367693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2472367693
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3552622166
Short name T212
Test name
Test status
Simulation time 2169641112 ps
CPU time 27.7 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:28:35 PM PDT 24
Peak memory 200292 kb
Host smart-efefeef1-0f9c-402e-beab-e065dc26e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552622166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3552622166
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1748037885
Short name T268
Test name
Test status
Simulation time 2104034197 ps
CPU time 154.21 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:30:51 PM PDT 24
Peak memory 458516 kb
Host smart-7e24ab9a-f1a4-4e81-8f1d-2b0630937bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748037885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1748037885
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3279219568
Short name T256
Test name
Test status
Simulation time 860042376 ps
CPU time 16.87 seconds
Started Jul 22 06:28:13 PM PDT 24
Finished Jul 22 06:28:30 PM PDT 24
Peak memory 200188 kb
Host smart-b33b2dbd-0de3-47bc-a2ee-2b5ca83c294a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279219568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3279219568
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2162697671
Short name T193
Test name
Test status
Simulation time 16179684979 ps
CPU time 159.57 seconds
Started Jul 22 06:28:11 PM PDT 24
Finished Jul 22 06:30:51 PM PDT 24
Peak memory 200272 kb
Host smart-8c18e4b1-b06a-4158-a730-e36816326ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162697671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2162697671
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1567108728
Short name T197
Test name
Test status
Simulation time 772012604 ps
CPU time 6.12 seconds
Started Jul 22 06:28:12 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 200252 kb
Host smart-3a94483b-6d94-4adc-8800-99489cb7930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567108728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1567108728
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1659443925
Short name T226
Test name
Test status
Simulation time 25013244324 ps
CPU time 120.27 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:31:42 PM PDT 24
Peak memory 200312 kb
Host smart-359d65c1-d30f-46b5-901a-dca3824b0ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659443925 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1659443925
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4165867160
Short name T277
Test name
Test status
Simulation time 779621410 ps
CPU time 10.63 seconds
Started Jul 22 06:28:12 PM PDT 24
Finished Jul 22 06:28:22 PM PDT 24
Peak memory 200232 kb
Host smart-8553ceec-11ea-41f0-93f1-58df5ac08189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165867160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4165867160
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2823210667
Short name T44
Test name
Test status
Simulation time 12802110 ps
CPU time 0.59 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:28:08 PM PDT 24
Peak memory 195140 kb
Host smart-c927bd05-f29f-4e5f-bc46-af5503f58a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823210667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2823210667
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2470385835
Short name T468
Test name
Test status
Simulation time 545368047 ps
CPU time 31.38 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:28:53 PM PDT 24
Peak memory 200268 kb
Host smart-951cef6b-489a-4c11-b879-4a6ae0f6b5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470385835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2470385835
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2397741951
Short name T518
Test name
Test status
Simulation time 453733299 ps
CPU time 23.67 seconds
Started Jul 22 06:28:11 PM PDT 24
Finished Jul 22 06:28:35 PM PDT 24
Peak memory 200228 kb
Host smart-70a4878e-9a31-4811-92d9-69b12200fe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397741951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2397741951
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2196651603
Short name T5
Test name
Test status
Simulation time 8890770608 ps
CPU time 1084.74 seconds
Started Jul 22 06:28:06 PM PDT 24
Finished Jul 22 06:46:11 PM PDT 24
Peak memory 736252 kb
Host smart-36dc8159-52b1-4e89-b9b4-4040b18f3861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196651603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2196651603
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3427222235
Short name T353
Test name
Test status
Simulation time 2695363708 ps
CPU time 44 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:29:05 PM PDT 24
Peak memory 200336 kb
Host smart-067dafd2-20ca-4c7d-aaa3-153f23d86911
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427222235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3427222235
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1570585046
Short name T26
Test name
Test status
Simulation time 506914252 ps
CPU time 9.45 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:28:17 PM PDT 24
Peak memory 200240 kb
Host smart-fe01c453-4664-41cf-a3cd-b471fa1d64c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570585046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1570585046
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.996119135
Short name T444
Test name
Test status
Simulation time 158842158 ps
CPU time 7.41 seconds
Started Jul 22 06:28:11 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 200256 kb
Host smart-7a4323de-f971-48b1-b870-12ad16685db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996119135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.996119135
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2365025441
Short name T347
Test name
Test status
Simulation time 55963771890 ps
CPU time 2129.68 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 07:03:51 PM PDT 24
Peak memory 755200 kb
Host smart-692ca097-5289-4131-94c9-23c871b75f0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365025441 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2365025441
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2517699340
Short name T326
Test name
Test status
Simulation time 1183422520 ps
CPU time 16.66 seconds
Started Jul 22 06:28:11 PM PDT 24
Finished Jul 22 06:28:28 PM PDT 24
Peak memory 200296 kb
Host smart-d39b726d-d99f-4c77-943c-662a0c51a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517699340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2517699340
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2293543805
Short name T87
Test name
Test status
Simulation time 141287941 ps
CPU time 0.63 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:28:17 PM PDT 24
Peak memory 195796 kb
Host smart-0325428a-236b-4bba-92fd-44e43ec3adda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293543805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2293543805
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1514960817
Short name T436
Test name
Test status
Simulation time 2672936335 ps
CPU time 34.03 seconds
Started Jul 22 06:28:03 PM PDT 24
Finished Jul 22 06:28:38 PM PDT 24
Peak memory 200288 kb
Host smart-485776ef-27bc-4b9d-875e-b61ac1ef0527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514960817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1514960817
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.368317309
Short name T460
Test name
Test status
Simulation time 1062129029 ps
CPU time 19.33 seconds
Started Jul 22 06:28:10 PM PDT 24
Finished Jul 22 06:28:30 PM PDT 24
Peak memory 200280 kb
Host smart-c30be8ab-4edf-49a6-a002-19906a7ac8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368317309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.368317309
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.590218606
Short name T152
Test name
Test status
Simulation time 11744955945 ps
CPU time 810.62 seconds
Started Jul 22 06:28:10 PM PDT 24
Finished Jul 22 06:41:41 PM PDT 24
Peak memory 653220 kb
Host smart-bbd42ea0-3168-48a9-b1c1-ac820e9eb697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590218606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.590218606
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1502497442
Short name T525
Test name
Test status
Simulation time 11936768374 ps
CPU time 157.19 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:30:58 PM PDT 24
Peak memory 200268 kb
Host smart-aa74c854-da73-47d7-b75b-53b3c17584b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502497442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1502497442
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1919902405
Short name T304
Test name
Test status
Simulation time 2021420417 ps
CPU time 111.02 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:30:12 PM PDT 24
Peak memory 200196 kb
Host smart-c778bbe0-a825-4e63-ad0c-612449e190d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919902405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1919902405
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.638146363
Short name T221
Test name
Test status
Simulation time 1278591053 ps
CPU time 6.04 seconds
Started Jul 22 06:28:06 PM PDT 24
Finished Jul 22 06:28:13 PM PDT 24
Peak memory 200248 kb
Host smart-8c67bdac-8860-4c86-87d1-3d5e8dad97b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638146363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.638146363
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.293007411
Short name T92
Test name
Test status
Simulation time 47810121224 ps
CPU time 881.87 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:42:59 PM PDT 24
Peak memory 617892 kb
Host smart-465445aa-b9ae-4780-a2e8-97d61cad6402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293007411 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.293007411
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3096757199
Short name T452
Test name
Test status
Simulation time 28009458 ps
CPU time 0.84 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:28:21 PM PDT 24
Peak memory 198988 kb
Host smart-736f63e1-ccb4-4c53-b359-c5d1d56a6f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096757199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3096757199
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4170513404
Short name T253
Test name
Test status
Simulation time 15327513 ps
CPU time 0.61 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:27:35 PM PDT 24
Peak memory 196160 kb
Host smart-6726b7cf-ead5-405b-b7c1-21efaeba9f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170513404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4170513404
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3832859661
Short name T346
Test name
Test status
Simulation time 5745501397 ps
CPU time 79.2 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:28:53 PM PDT 24
Peak memory 200332 kb
Host smart-d201ba10-5000-4c97-9112-4e034be6a0d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832859661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3832859661
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2687778384
Short name T378
Test name
Test status
Simulation time 1039789072 ps
CPU time 27.8 seconds
Started Jul 22 06:28:03 PM PDT 24
Finished Jul 22 06:28:32 PM PDT 24
Peak memory 200216 kb
Host smart-5d573bb2-fbf0-46b9-9245-462f61de28a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687778384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2687778384
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1799680377
Short name T372
Test name
Test status
Simulation time 5638598371 ps
CPU time 519.31 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:36:18 PM PDT 24
Peak memory 661424 kb
Host smart-e635cb2e-ff03-4cf6-9141-73c43f61c6f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799680377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1799680377
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3075054316
Short name T430
Test name
Test status
Simulation time 655037370 ps
CPU time 33.56 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:28:12 PM PDT 24
Peak memory 200276 kb
Host smart-14eab665-967b-44a9-a523-4a54af1fa636
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075054316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3075054316
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4045587143
Short name T290
Test name
Test status
Simulation time 14041542184 ps
CPU time 127.89 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 200332 kb
Host smart-574dd273-2450-4085-a6f7-791190112485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045587143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4045587143
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.2975246161
Short name T96
Test name
Test status
Simulation time 2119179182 ps
CPU time 9.45 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:27:40 PM PDT 24
Peak memory 200288 kb
Host smart-f1202c33-5223-4c03-abe7-ee1e55608a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975246161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2975246161
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1725842608
Short name T15
Test name
Test status
Simulation time 489256297089 ps
CPU time 2650.98 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 07:11:44 PM PDT 24
Peak memory 761024 kb
Host smart-d33cf4a9-66d0-41ca-a182-641b64fb3710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725842608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1725842608
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2904601062
Short name T180
Test name
Test status
Simulation time 5350932239 ps
CPU time 42.61 seconds
Started Jul 22 06:27:37 PM PDT 24
Finished Jul 22 06:28:21 PM PDT 24
Peak memory 200280 kb
Host smart-d9e0731b-4c90-48dc-b17d-137bf7f9aee5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2904601062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2904601062
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2476251012
Short name T299
Test name
Test status
Simulation time 17645535150 ps
CPU time 93.65 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:29:07 PM PDT 24
Peak memory 200340 kb
Host smart-3fe68fe9-13d5-45a4-984c-a7552745586d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2476251012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2476251012
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3385964691
Short name T165
Test name
Test status
Simulation time 7109968294 ps
CPU time 69.01 seconds
Started Jul 22 06:27:34 PM PDT 24
Finished Jul 22 06:28:44 PM PDT 24
Peak memory 200236 kb
Host smart-273a4dac-901b-4a29-92a3-855715a85871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3385964691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3385964691
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1023560322
Short name T337
Test name
Test status
Simulation time 233006896134 ps
CPU time 708.24 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:39:21 PM PDT 24
Peak memory 200288 kb
Host smart-ef8bcfa8-e9bf-45c8-9531-0fb4c991a5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1023560322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1023560322
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.203991625
Short name T19
Test name
Test status
Simulation time 139041342809 ps
CPU time 2436.37 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 07:08:07 PM PDT 24
Peak memory 215916 kb
Host smart-e7a3bc68-a3fd-4e98-97cd-ec65b09adc9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=203991625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.203991625
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2538869749
Short name T435
Test name
Test status
Simulation time 37355314102 ps
CPU time 1971.54 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 07:00:26 PM PDT 24
Peak memory 216364 kb
Host smart-0a574005-793e-4072-9484-1120f5ef6825
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2538869749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2538869749
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1988168201
Short name T479
Test name
Test status
Simulation time 15016748764 ps
CPU time 67.4 seconds
Started Jul 22 06:27:36 PM PDT 24
Finished Jul 22 06:28:44 PM PDT 24
Peak memory 200296 kb
Host smart-744f89a2-e292-44ee-9ae7-3243f0cf54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988168201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1988168201
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1691623317
Short name T222
Test name
Test status
Simulation time 25730147 ps
CPU time 0.63 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:28:23 PM PDT 24
Peak memory 196112 kb
Host smart-4f0a2533-f689-4dd9-92d3-714d07226ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691623317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1691623317
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4031683521
Short name T190
Test name
Test status
Simulation time 2239902410 ps
CPU time 30.87 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:28:49 PM PDT 24
Peak memory 200312 kb
Host smart-4174e1bc-3f16-4e3e-b00a-df26bf5c4624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031683521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4031683521
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4102463706
Short name T266
Test name
Test status
Simulation time 1667348312 ps
CPU time 31.44 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200224 kb
Host smart-522b8abf-921e-4a3a-8d90-9211dd6d28a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102463706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4102463706
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1726105198
Short name T516
Test name
Test status
Simulation time 2433202733 ps
CPU time 460.72 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:35:58 PM PDT 24
Peak memory 631504 kb
Host smart-13a375b9-99d2-4095-b01e-260d723f0b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726105198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1726105198
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1631246403
Short name T217
Test name
Test status
Simulation time 4020419381 ps
CPU time 222.88 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:32:00 PM PDT 24
Peak memory 200300 kb
Host smart-20c6d9ee-ad63-4dfb-9fcd-b805d18999c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631246403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1631246403
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1468359874
Short name T31
Test name
Test status
Simulation time 24138675831 ps
CPU time 74.27 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:29:29 PM PDT 24
Peak memory 200312 kb
Host smart-0a6c0de7-5c1a-4618-bed5-942cc70778d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468359874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1468359874
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.819876273
Short name T490
Test name
Test status
Simulation time 3880661493 ps
CPU time 11.46 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:28:32 PM PDT 24
Peak memory 200308 kb
Host smart-8b8b2782-56ee-4c58-8091-1f31288a293d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819876273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.819876273
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.758522614
Short name T399
Test name
Test status
Simulation time 40235241903 ps
CPU time 2886.23 seconds
Started Jul 22 06:29:00 PM PDT 24
Finished Jul 22 07:17:07 PM PDT 24
Peak memory 820012 kb
Host smart-8b85c2fa-924c-44ce-90e4-616ec3ed84dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758522614 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.758522614
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2182137578
Short name T345
Test name
Test status
Simulation time 14024984016 ps
CPU time 35.47 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200308 kb
Host smart-f24879b1-60e3-4321-8611-837b2b903c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182137578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2182137578
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4118842707
Short name T496
Test name
Test status
Simulation time 43659817 ps
CPU time 0.61 seconds
Started Jul 22 06:28:10 PM PDT 24
Finished Jul 22 06:28:11 PM PDT 24
Peak memory 196168 kb
Host smart-f692ff11-fbb0-4bcf-bf6a-ff53195e5362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118842707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4118842707
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3450399838
Short name T283
Test name
Test status
Simulation time 1598001083 ps
CPU time 17.52 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:28:35 PM PDT 24
Peak memory 200284 kb
Host smart-37380997-48b6-4f3c-a4b9-78ac9a58db9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450399838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3450399838
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4285783557
Short name T310
Test name
Test status
Simulation time 27860703898 ps
CPU time 65.76 seconds
Started Jul 22 06:28:09 PM PDT 24
Finished Jul 22 06:29:15 PM PDT 24
Peak memory 200228 kb
Host smart-ea79317c-1215-4140-972e-e742d07bc224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285783557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4285783557
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3081526041
Short name T43
Test name
Test status
Simulation time 49283601708 ps
CPU time 746.46 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:40:45 PM PDT 24
Peak memory 715540 kb
Host smart-1a5b721a-fe2f-4be7-a0fc-93f453dfa8ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081526041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3081526041
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.280664644
Short name T527
Test name
Test status
Simulation time 3364162879 ps
CPU time 55.48 seconds
Started Jul 22 06:29:40 PM PDT 24
Finished Jul 22 06:30:36 PM PDT 24
Peak memory 200232 kb
Host smart-6a02d3c2-bbe9-4425-8975-e540096d5fe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280664644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.280664644
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3703386475
Short name T309
Test name
Test status
Simulation time 51382123342 ps
CPU time 234.66 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:32:10 PM PDT 24
Peak memory 208528 kb
Host smart-686466e5-9372-4b13-a2f6-515ca24ded03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703386475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3703386475
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1816622006
Short name T41
Test name
Test status
Simulation time 319740167 ps
CPU time 1.86 seconds
Started Jul 22 06:28:12 PM PDT 24
Finished Jul 22 06:28:14 PM PDT 24
Peak memory 200280 kb
Host smart-ca229aae-a156-4794-a9eb-321fc1e1a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816622006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1816622006
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2079157571
Short name T199
Test name
Test status
Simulation time 5577190986 ps
CPU time 76.96 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:29:32 PM PDT 24
Peak memory 200332 kb
Host smart-0059a7e6-1872-4a72-9a8f-7c1b6dd91a05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079157571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2079157571
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2860960399
Short name T451
Test name
Test status
Simulation time 1710687021 ps
CPU time 85.19 seconds
Started Jul 22 06:29:51 PM PDT 24
Finished Jul 22 06:31:18 PM PDT 24
Peak memory 200252 kb
Host smart-02cf09ca-efac-48e6-b7e5-c6c6b43851bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860960399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2860960399
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3740702237
Short name T502
Test name
Test status
Simulation time 15967642 ps
CPU time 0.6 seconds
Started Jul 22 06:28:18 PM PDT 24
Finished Jul 22 06:28:20 PM PDT 24
Peak memory 196412 kb
Host smart-5138b66e-cfb3-44d8-8325-20423c43089b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740702237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3740702237
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2296056509
Short name T54
Test name
Test status
Simulation time 1271551795 ps
CPU time 72.82 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:29:34 PM PDT 24
Peak memory 200204 kb
Host smart-2c016cae-3dad-4f46-b06e-6cca19cc7e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296056509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2296056509
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1879541391
Short name T178
Test name
Test status
Simulation time 203419653 ps
CPU time 2.96 seconds
Started Jul 22 06:29:00 PM PDT 24
Finished Jul 22 06:29:03 PM PDT 24
Peak memory 200228 kb
Host smart-74e08aee-be8c-43ee-b291-a9b428138e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879541391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1879541391
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3541120578
Short name T80
Test name
Test status
Simulation time 2806170789 ps
CPU time 491.99 seconds
Started Jul 22 06:28:13 PM PDT 24
Finished Jul 22 06:36:25 PM PDT 24
Peak memory 669000 kb
Host smart-c10e9927-ce77-438d-b61f-d7f80fcb5ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541120578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3541120578
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3883606943
Short name T422
Test name
Test status
Simulation time 2034258014 ps
CPU time 34.51 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200208 kb
Host smart-6d06ee3a-8e97-4aaa-a856-de597c863246
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883606943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3883606943
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3805887738
Short name T313
Test name
Test status
Simulation time 1779904202 ps
CPU time 101.72 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:30:00 PM PDT 24
Peak memory 200320 kb
Host smart-04792b67-3d25-4fa7-bb08-e46b6798419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805887738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3805887738
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3366886790
Short name T288
Test name
Test status
Simulation time 61956226 ps
CPU time 0.73 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 196868 kb
Host smart-f8deb328-2db0-491c-b2c8-8bb8e3917e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366886790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3366886790
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1236035545
Short name T240
Test name
Test status
Simulation time 54608742869 ps
CPU time 287.71 seconds
Started Jul 22 06:28:09 PM PDT 24
Finished Jul 22 06:32:57 PM PDT 24
Peak memory 200300 kb
Host smart-55eb5f68-7510-482a-8803-63b664eb72f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236035545 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1236035545
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1988262917
Short name T228
Test name
Test status
Simulation time 332196934 ps
CPU time 6.17 seconds
Started Jul 22 06:28:18 PM PDT 24
Finished Jul 22 06:28:25 PM PDT 24
Peak memory 200156 kb
Host smart-8ac92d91-66cf-4a76-9129-738bf9acab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988262917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1988262917
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.718130237
Short name T84
Test name
Test status
Simulation time 31169011 ps
CPU time 0.58 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:28:17 PM PDT 24
Peak memory 195824 kb
Host smart-4a7842e8-41f6-4f69-b81c-d68afa8b4240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718130237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.718130237
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.601052084
Short name T354
Test name
Test status
Simulation time 834819188 ps
CPU time 23.07 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:28:46 PM PDT 24
Peak memory 200212 kb
Host smart-d3ae5564-2e6d-4319-8e45-209ee6ff18c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601052084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.601052084
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2908138471
Short name T474
Test name
Test status
Simulation time 14053698435 ps
CPU time 56.85 seconds
Started Jul 22 06:28:27 PM PDT 24
Finished Jul 22 06:29:24 PM PDT 24
Peak memory 200332 kb
Host smart-30b1c533-1a8d-40e9-9ae7-787bcd384615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908138471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2908138471
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.271438276
Short name T407
Test name
Test status
Simulation time 9710374080 ps
CPU time 518.34 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:36:54 PM PDT 24
Peak memory 691764 kb
Host smart-d14e062f-2348-4d08-9455-a36bc33622c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271438276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.271438276
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3189105983
Short name T269
Test name
Test status
Simulation time 21541899861 ps
CPU time 161.3 seconds
Started Jul 22 06:28:38 PM PDT 24
Finished Jul 22 06:31:20 PM PDT 24
Peak memory 200288 kb
Host smart-813af6f6-20fc-438f-9629-9dcad9e05e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189105983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3189105983
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.76040245
Short name T7
Test name
Test status
Simulation time 786264708 ps
CPU time 43.29 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:29:01 PM PDT 24
Peak memory 200272 kb
Host smart-e4470bd4-54b6-41f2-aef4-945824ffd504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76040245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.76040245
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3267741354
Short name T225
Test name
Test status
Simulation time 667123970 ps
CPU time 8.27 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:28:25 PM PDT 24
Peak memory 200232 kb
Host smart-a3901026-d3e5-4489-810f-eb24789d42b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267741354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3267741354
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2768291520
Short name T429
Test name
Test status
Simulation time 49653144673 ps
CPU time 1915.74 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 07:00:20 PM PDT 24
Peak memory 770144 kb
Host smart-c1210f1d-a94b-4190-9f7c-678e76dc648c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768291520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2768291520
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.78199483
Short name T454
Test name
Test status
Simulation time 26742122701 ps
CPU time 108.7 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:30:10 PM PDT 24
Peak memory 200316 kb
Host smart-8e020ea9-deb7-4966-850d-cdd2ebbeeea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78199483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.78199483
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3481228
Short name T455
Test name
Test status
Simulation time 13005697 ps
CPU time 0.62 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:28:18 PM PDT 24
Peak memory 196832 kb
Host smart-1ff92718-be35-4034-8078-f92c08658e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3481228
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3677329998
Short name T20
Test name
Test status
Simulation time 1017386706 ps
CPU time 56.68 seconds
Started Jul 22 06:29:37 PM PDT 24
Finished Jul 22 06:30:34 PM PDT 24
Peak memory 200312 kb
Host smart-1285045e-6633-413d-9385-66a190b4d4fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677329998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3677329998
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1284773585
Short name T368
Test name
Test status
Simulation time 903735583 ps
CPU time 24.07 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:28:46 PM PDT 24
Peak memory 200156 kb
Host smart-2249a3b8-cc59-4805-a814-3a8dbebe0bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284773585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1284773585
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1775423298
Short name T367
Test name
Test status
Simulation time 1933244928 ps
CPU time 374.33 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:34:31 PM PDT 24
Peak memory 655432 kb
Host smart-321ea7c3-3b67-483b-9e46-078092482030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775423298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1775423298
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1684283986
Short name T65
Test name
Test status
Simulation time 22202790634 ps
CPU time 90.37 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:29:51 PM PDT 24
Peak memory 200292 kb
Host smart-f78a0bb5-2f59-41fe-b116-fe839a98c6e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684283986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1684283986
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3876898929
Short name T82
Test name
Test status
Simulation time 240514395 ps
CPU time 14.07 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:28:58 PM PDT 24
Peak memory 200236 kb
Host smart-0332ef83-a15d-4e65-9009-c79447ffc23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876898929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3876898929
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1873946090
Short name T503
Test name
Test status
Simulation time 1041484760 ps
CPU time 12.01 seconds
Started Jul 22 06:30:01 PM PDT 24
Finished Jul 22 06:30:14 PM PDT 24
Peak memory 200068 kb
Host smart-6737d2fe-4156-4adb-90ac-53b32945a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873946090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1873946090
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.25313013
Short name T90
Test name
Test status
Simulation time 160131773611 ps
CPU time 897.91 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:43:20 PM PDT 24
Peak memory 702232 kb
Host smart-1377fb63-b2f8-42c0-83c2-f5e2c79d0d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25313013 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.25313013
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.675634619
Short name T495
Test name
Test status
Simulation time 1216096635 ps
CPU time 13.29 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:28:33 PM PDT 24
Peak memory 200228 kb
Host smart-6f6e7cae-a88d-430b-b84e-222e3eca1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675634619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.675634619
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.719898320
Short name T363
Test name
Test status
Simulation time 11259122 ps
CPU time 0.6 seconds
Started Jul 22 06:29:37 PM PDT 24
Finished Jul 22 06:29:38 PM PDT 24
Peak memory 195172 kb
Host smart-fd7c7af7-97c8-4545-89e0-b48945a4a580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719898320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.719898320
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1614230059
Short name T22
Test name
Test status
Simulation time 811385193 ps
CPU time 44.32 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:29:08 PM PDT 24
Peak memory 200236 kb
Host smart-2014cfa0-5e34-416e-af8d-6a88a102bf89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614230059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1614230059
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1514083697
Short name T406
Test name
Test status
Simulation time 526588367 ps
CPU time 5.2 seconds
Started Jul 22 06:28:27 PM PDT 24
Finished Jul 22 06:28:33 PM PDT 24
Peak memory 200296 kb
Host smart-20f42cdb-d145-4c5f-a9dd-c575ff344765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514083697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1514083697
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1709878881
Short name T4
Test name
Test status
Simulation time 3833091588 ps
CPU time 154.46 seconds
Started Jul 22 06:28:38 PM PDT 24
Finished Jul 22 06:31:13 PM PDT 24
Peak memory 481560 kb
Host smart-405c6239-9695-490a-9e49-3af0f427b73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709878881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1709878881
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.370375726
Short name T323
Test name
Test status
Simulation time 370258986 ps
CPU time 1.7 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:28:23 PM PDT 24
Peak memory 200212 kb
Host smart-6a942f59-51ba-4810-ab45-1e04a951ddf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370375726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.370375726
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4086160000
Short name T450
Test name
Test status
Simulation time 1932208478 ps
CPU time 32.78 seconds
Started Jul 22 06:28:18 PM PDT 24
Finished Jul 22 06:28:52 PM PDT 24
Peak memory 200216 kb
Host smart-fd422c11-c766-4df9-9dc1-151b6401079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086160000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4086160000
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2928354973
Short name T146
Test name
Test status
Simulation time 2453417520 ps
CPU time 11.2 seconds
Started Jul 22 06:28:30 PM PDT 24
Finished Jul 22 06:28:42 PM PDT 24
Peak memory 200308 kb
Host smart-e18eb29c-3aaf-4161-ba88-f3b8ffc6df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928354973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2928354973
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3195017925
Short name T89
Test name
Test status
Simulation time 171321026408 ps
CPU time 2113.66 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 07:03:38 PM PDT 24
Peak memory 707200 kb
Host smart-ae048d64-0e26-42ea-b60a-6140342af005
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195017925 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3195017925
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1354694042
Short name T132
Test name
Test status
Simulation time 15310741079 ps
CPU time 96.92 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:30:00 PM PDT 24
Peak memory 200316 kb
Host smart-c7295ab8-0852-4838-b702-b462c65ad669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354694042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1354694042
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1203276014
Short name T453
Test name
Test status
Simulation time 13065014 ps
CPU time 0.58 seconds
Started Jul 22 06:29:41 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 196140 kb
Host smart-cf31de9f-70d1-4a1b-b365-ab1ad6d99d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203276014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1203276014
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4194693324
Short name T333
Test name
Test status
Simulation time 2635505180 ps
CPU time 77 seconds
Started Jul 22 06:28:16 PM PDT 24
Finished Jul 22 06:29:35 PM PDT 24
Peak memory 200324 kb
Host smart-30790e3f-9aaa-4148-81f0-bfeec45cf12b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194693324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4194693324
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.720149511
Short name T340
Test name
Test status
Simulation time 2062371544 ps
CPU time 28.26 seconds
Started Jul 22 06:28:24 PM PDT 24
Finished Jul 22 06:28:53 PM PDT 24
Peak memory 200436 kb
Host smart-69146b8c-9c23-4f08-bdae-c694f4490164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720149511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.720149511
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1381923359
Short name T362
Test name
Test status
Simulation time 84477125631 ps
CPU time 1264.65 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:49:26 PM PDT 24
Peak memory 761692 kb
Host smart-39847a6e-6957-4964-a7d5-04a814198128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381923359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1381923359
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1947780535
Short name T278
Test name
Test status
Simulation time 11047406335 ps
CPU time 91.68 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:29:53 PM PDT 24
Peak memory 200336 kb
Host smart-ac5b67d3-5db3-4162-9ce9-61ed283ab7c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947780535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1947780535
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.470338237
Short name T515
Test name
Test status
Simulation time 7868946009 ps
CPU time 62.69 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:29:25 PM PDT 24
Peak memory 200300 kb
Host smart-53e469df-7810-403a-9e97-b0845862cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470338237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.470338237
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.888596721
Short name T274
Test name
Test status
Simulation time 343740889 ps
CPU time 12.84 seconds
Started Jul 22 06:29:40 PM PDT 24
Finished Jul 22 06:29:53 PM PDT 24
Peak memory 200300 kb
Host smart-5f75cb44-5551-423e-b8cd-3221c4897146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888596721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.888596721
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.828734666
Short name T223
Test name
Test status
Simulation time 20673642998 ps
CPU time 265.01 seconds
Started Jul 22 06:28:58 PM PDT 24
Finished Jul 22 06:33:24 PM PDT 24
Peak memory 200332 kb
Host smart-96504837-024b-4c18-b596-ae3131690e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828734666 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.828734666
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1137665178
Short name T272
Test name
Test status
Simulation time 2859216372 ps
CPU time 99.76 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:30:06 PM PDT 24
Peak memory 200284 kb
Host smart-bbb72c1f-3711-45d0-984b-9c1f92c989c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137665178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1137665178
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3927891543
Short name T523
Test name
Test status
Simulation time 40407747 ps
CPU time 0.62 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:28:27 PM PDT 24
Peak memory 196196 kb
Host smart-a09e8ff7-b464-4ccb-8714-3fa0e832c428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927891543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3927891543
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.741640761
Short name T21
Test name
Test status
Simulation time 890863203 ps
CPU time 55.91 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:29:15 PM PDT 24
Peak memory 200276 kb
Host smart-5c1d5c5b-2844-4990-85df-c326807b5b17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741640761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.741640761
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2206970704
Short name T295
Test name
Test status
Simulation time 11551104716 ps
CPU time 17.51 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:28:41 PM PDT 24
Peak memory 200352 kb
Host smart-921ef61d-c1fc-4411-b551-a125365ea57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206970704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2206970704
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1504538664
Short name T1
Test name
Test status
Simulation time 5108364303 ps
CPU time 142.78 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:30:44 PM PDT 24
Peak memory 341708 kb
Host smart-1b90e887-7d6c-4ef4-9b41-89379007b1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504538664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1504538664
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3861211104
Short name T424
Test name
Test status
Simulation time 10175318971 ps
CPU time 180.16 seconds
Started Jul 22 06:28:15 PM PDT 24
Finished Jul 22 06:31:16 PM PDT 24
Peak memory 200340 kb
Host smart-9dcd6711-6c1e-4a54-a405-373aba0d0507
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861211104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3861211104
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3359107362
Short name T324
Test name
Test status
Simulation time 1096174775 ps
CPU time 8.78 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:28:32 PM PDT 24
Peak memory 200244 kb
Host smart-f922936f-937b-4fb7-b1b8-9382f3841320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359107362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3359107362
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2519268251
Short name T409
Test name
Test status
Simulation time 2330720658 ps
CPU time 12.14 seconds
Started Jul 22 06:28:28 PM PDT 24
Finished Jul 22 06:28:41 PM PDT 24
Peak memory 200296 kb
Host smart-8194b7a5-cd6a-40f8-93c3-31e9978b4b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519268251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2519268251
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2306010564
Short name T93
Test name
Test status
Simulation time 334274993297 ps
CPU time 1242.09 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:49:02 PM PDT 24
Peak memory 678040 kb
Host smart-d4ff34b6-c774-4881-911c-91c582d79df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306010564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2306010564
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2712166280
Short name T32
Test name
Test status
Simulation time 1029044080 ps
CPU time 53.31 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:29:19 PM PDT 24
Peak memory 200248 kb
Host smart-ef957a9f-c325-49a8-b83f-3e905427e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712166280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2712166280
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1385359962
Short name T170
Test name
Test status
Simulation time 48124026 ps
CPU time 0.58 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:28:26 PM PDT 24
Peak memory 195096 kb
Host smart-a39131e5-91a9-465e-8e54-0b6d2f2536cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385359962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1385359962
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.15736748
Short name T512
Test name
Test status
Simulation time 6039269097 ps
CPU time 70.54 seconds
Started Jul 22 06:28:22 PM PDT 24
Finished Jul 22 06:29:33 PM PDT 24
Peak memory 200348 kb
Host smart-ab88bad1-bbdb-4b4b-bbb5-ac2891707355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15736748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.15736748
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2414930497
Short name T312
Test name
Test status
Simulation time 344065440 ps
CPU time 9.15 seconds
Started Jul 22 06:28:18 PM PDT 24
Finished Jul 22 06:28:28 PM PDT 24
Peak memory 200228 kb
Host smart-3f31993b-f73e-4f08-a3bb-d11f3b634537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414930497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2414930497
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3421995256
Short name T300
Test name
Test status
Simulation time 1943093973 ps
CPU time 99.32 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:29:58 PM PDT 24
Peak memory 549572 kb
Host smart-c091aede-5a1b-4716-97d9-3fbac67b4080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421995256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3421995256
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.247403409
Short name T500
Test name
Test status
Simulation time 9175369553 ps
CPU time 69.15 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:29:31 PM PDT 24
Peak memory 200296 kb
Host smart-6b947e82-6ddb-45af-bad2-1a468dbb7f55
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247403409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.247403409
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3965878573
Short name T185
Test name
Test status
Simulation time 4556937224 ps
CPU time 73.82 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:29:32 PM PDT 24
Peak memory 200320 kb
Host smart-79ccdbc3-7b5c-4e4c-a0c3-3e84b9b049cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965878573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3965878573
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.992338036
Short name T219
Test name
Test status
Simulation time 678419998 ps
CPU time 16.71 seconds
Started Jul 22 06:28:37 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200288 kb
Host smart-43e89f6b-40b7-490d-9077-5af1d069633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992338036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.992338036
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1221859918
Short name T91
Test name
Test status
Simulation time 524421058998 ps
CPU time 2650.21 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 07:12:32 PM PDT 24
Peak memory 735960 kb
Host smart-d507d1aa-d139-4239-abfc-81ce8c337787
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221859918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1221859918
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4156915974
Short name T357
Test name
Test status
Simulation time 465111543 ps
CPU time 6.57 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:28:31 PM PDT 24
Peak memory 200248 kb
Host smart-d1229599-7f71-4871-a3f2-00e50a12ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156915974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4156915974
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1816740186
Short name T45
Test name
Test status
Simulation time 103346556 ps
CPU time 0.56 seconds
Started Jul 22 06:28:37 PM PDT 24
Finished Jul 22 06:28:39 PM PDT 24
Peak memory 196180 kb
Host smart-8f0ac966-1cc7-4df8-b015-027909e6fdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816740186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1816740186
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2155248699
Short name T11
Test name
Test status
Simulation time 2896277515 ps
CPU time 77.04 seconds
Started Jul 22 06:28:14 PM PDT 24
Finished Jul 22 06:29:32 PM PDT 24
Peak memory 200304 kb
Host smart-62c9e63e-e0fd-44ea-8a76-4571462d83fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155248699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2155248699
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1277779724
Short name T86
Test name
Test status
Simulation time 12096375086 ps
CPU time 40.87 seconds
Started Jul 22 06:28:24 PM PDT 24
Finished Jul 22 06:29:06 PM PDT 24
Peak memory 200508 kb
Host smart-c457de7f-6f26-46e6-b8a6-73bac954c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277779724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1277779724
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4237135691
Short name T189
Test name
Test status
Simulation time 2964065206 ps
CPU time 117.81 seconds
Started Jul 22 06:28:37 PM PDT 24
Finished Jul 22 06:30:36 PM PDT 24
Peak memory 431232 kb
Host smart-58bb662e-07b8-47f2-80ab-33493b3cf7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237135691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4237135691
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3996286277
Short name T2
Test name
Test status
Simulation time 4793174726 ps
CPU time 82.32 seconds
Started Jul 22 06:30:01 PM PDT 24
Finished Jul 22 06:31:24 PM PDT 24
Peak memory 200292 kb
Host smart-bfb04595-cecd-4cc0-96e7-01a377bfbccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996286277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3996286277
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.460344833
Short name T528
Test name
Test status
Simulation time 6062940330 ps
CPU time 163.69 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:31:07 PM PDT 24
Peak memory 200312 kb
Host smart-9c66f279-4968-489b-973d-88724e9c8efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460344833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.460344833
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.477319559
Short name T95
Test name
Test status
Simulation time 436044719 ps
CPU time 4.16 seconds
Started Jul 22 06:28:21 PM PDT 24
Finished Jul 22 06:28:26 PM PDT 24
Peak memory 200172 kb
Host smart-6fd5175d-4690-435e-97e5-3b880bf5e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477319559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.477319559
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.191047468
Short name T511
Test name
Test status
Simulation time 133662038782 ps
CPU time 501.71 seconds
Started Jul 22 06:28:20 PM PDT 24
Finished Jul 22 06:36:42 PM PDT 24
Peak memory 370076 kb
Host smart-344529d1-c2b2-46f6-b9be-96aabefacc3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191047468 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.191047468
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4253762270
Short name T66
Test name
Test status
Simulation time 2862912660 ps
CPU time 40.61 seconds
Started Jul 22 06:28:37 PM PDT 24
Finished Jul 22 06:29:18 PM PDT 24
Peak memory 200312 kb
Host smart-56a4a905-ee13-446a-aef6-38f34b71a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253762270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4253762270
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.567429060
Short name T166
Test name
Test status
Simulation time 14252424 ps
CPU time 0.6 seconds
Started Jul 22 06:27:28 PM PDT 24
Finished Jul 22 06:27:29 PM PDT 24
Peak memory 196108 kb
Host smart-f59cf06c-4561-4540-b9be-2c7a8104cfec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567429060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.567429060
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2774806093
Short name T35
Test name
Test status
Simulation time 3297792098 ps
CPU time 92.49 seconds
Started Jul 22 06:27:29 PM PDT 24
Finished Jul 22 06:29:02 PM PDT 24
Peak memory 208520 kb
Host smart-5337b271-b5e1-47a4-960f-883289112bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774806093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2774806093
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.707848933
Short name T469
Test name
Test status
Simulation time 9502879597 ps
CPU time 49.85 seconds
Started Jul 22 06:27:29 PM PDT 24
Finished Jul 22 06:28:19 PM PDT 24
Peak memory 200300 kb
Host smart-4c7b9b8a-9175-4da7-9463-f60aa62aecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707848933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.707848933
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2178989481
Short name T420
Test name
Test status
Simulation time 22859164 ps
CPU time 0.69 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:27:34 PM PDT 24
Peak memory 198544 kb
Host smart-cf07a502-db69-482e-ab92-1b898ed59097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178989481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2178989481
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3634510859
Short name T471
Test name
Test status
Simulation time 83788998363 ps
CPU time 166.68 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:30:32 PM PDT 24
Peak memory 200236 kb
Host smart-09964557-d4a7-4b60-871c-5e8935a8d468
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634510859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3634510859
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4000937285
Short name T264
Test name
Test status
Simulation time 7072404761 ps
CPU time 121.96 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:29:32 PM PDT 24
Peak memory 200364 kb
Host smart-3c08eba6-98fc-4c36-bcaa-ca22433c7203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000937285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4000937285
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3959304238
Short name T62
Test name
Test status
Simulation time 81155365 ps
CPU time 0.9 seconds
Started Jul 22 06:29:36 PM PDT 24
Finished Jul 22 06:29:37 PM PDT 24
Peak memory 218684 kb
Host smart-416a3633-1396-44e9-8410-6b752e664c15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959304238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3959304238
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3868156426
Short name T327
Test name
Test status
Simulation time 880631448 ps
CPU time 7.27 seconds
Started Jul 22 06:27:37 PM PDT 24
Finished Jul 22 06:27:45 PM PDT 24
Peak memory 200228 kb
Host smart-a09bf05c-3e40-4a9c-9bfa-8026e813af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868156426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3868156426
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2454076613
Short name T281
Test name
Test status
Simulation time 44415585307 ps
CPU time 1627.82 seconds
Started Jul 22 06:27:39 PM PDT 24
Finished Jul 22 06:54:48 PM PDT 24
Peak memory 780984 kb
Host smart-a6c7294b-21fb-4d2c-9961-417e59ccb92f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454076613 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2454076613
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.274021893
Short name T77
Test name
Test status
Simulation time 5581197810 ps
CPU time 171.79 seconds
Started Jul 22 06:29:39 PM PDT 24
Finished Jul 22 06:32:31 PM PDT 24
Peak memory 444024 kb
Host smart-e22c1c9d-54bc-4a90-a15f-92f73e3c3f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274021893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.274021893
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3197632476
Short name T405
Test name
Test status
Simulation time 17022360228 ps
CPU time 70.37 seconds
Started Jul 22 06:27:27 PM PDT 24
Finished Jul 22 06:28:38 PM PDT 24
Peak memory 200264 kb
Host smart-a378f544-cef2-4d10-abf9-9812683362f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3197632476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3197632476
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.185507150
Short name T177
Test name
Test status
Simulation time 14049428374 ps
CPU time 97.66 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:12 PM PDT 24
Peak memory 200296 kb
Host smart-e3cb2a1c-9ae0-4c92-9561-8fd7b285742e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=185507150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.185507150
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1260326920
Short name T179
Test name
Test status
Simulation time 11893910708 ps
CPU time 111.71 seconds
Started Jul 22 06:27:30 PM PDT 24
Finished Jul 22 06:29:22 PM PDT 24
Peak memory 200332 kb
Host smart-076ae00f-718a-4797-927a-c9dd8f1f440b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1260326920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1260326920
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1275728386
Short name T411
Test name
Test status
Simulation time 72994539129 ps
CPU time 601.26 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:37:36 PM PDT 24
Peak memory 200288 kb
Host smart-aa06a1b8-2a54-48fd-9315-410a68db969b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1275728386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1275728386
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.10103765
Short name T394
Test name
Test status
Simulation time 136977617267 ps
CPU time 2293.33 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 07:05:46 PM PDT 24
Peak memory 215992 kb
Host smart-31bc4a91-48f3-4d2b-9019-b03b80621373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=10103765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.10103765
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.751968965
Short name T104
Test name
Test status
Simulation time 1480933741096 ps
CPU time 2509.53 seconds
Started Jul 22 06:27:34 PM PDT 24
Finished Jul 22 07:09:25 PM PDT 24
Peak memory 215764 kb
Host smart-b36fb008-fa7e-4226-abd0-06302b9057e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=751968965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.751968965
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2875425048
Short name T499
Test name
Test status
Simulation time 7125019789 ps
CPU time 91.6 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:29:05 PM PDT 24
Peak memory 200340 kb
Host smart-4bfaaa1f-4cdf-4def-a506-1253cd3eb2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875425048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2875425048
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3370005956
Short name T466
Test name
Test status
Simulation time 30192577 ps
CPU time 0.57 seconds
Started Jul 22 06:28:28 PM PDT 24
Finished Jul 22 06:28:29 PM PDT 24
Peak memory 195096 kb
Host smart-4bc24689-7b6c-40c9-a4c2-48c4508cdec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370005956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3370005956
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.103761784
Short name T369
Test name
Test status
Simulation time 429309533 ps
CPU time 23.49 seconds
Started Jul 22 06:28:17 PM PDT 24
Finished Jul 22 06:28:42 PM PDT 24
Peak memory 200300 kb
Host smart-af1e430a-f200-477d-a7af-7f316edde1b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103761784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.103761784
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3586950201
Short name T159
Test name
Test status
Simulation time 2210793678 ps
CPU time 30.67 seconds
Started Jul 22 06:28:30 PM PDT 24
Finished Jul 22 06:29:02 PM PDT 24
Peak memory 200376 kb
Host smart-b0b8bc40-7118-4b7e-b642-834cb4267bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586950201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3586950201
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.828033684
Short name T501
Test name
Test status
Simulation time 1856567284 ps
CPU time 98.53 seconds
Started Jul 22 06:28:28 PM PDT 24
Finished Jul 22 06:30:07 PM PDT 24
Peak memory 463596 kb
Host smart-6a59277b-d82a-452d-97ea-aa52c15fa1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828033684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.828033684
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3819087455
Short name T229
Test name
Test status
Simulation time 16724928513 ps
CPU time 155.79 seconds
Started Jul 22 06:28:46 PM PDT 24
Finished Jul 22 06:31:22 PM PDT 24
Peak memory 200268 kb
Host smart-468826d0-f407-44b5-99c3-1281b0a305f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819087455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3819087455
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1050733578
Short name T280
Test name
Test status
Simulation time 485245524 ps
CPU time 9.52 seconds
Started Jul 22 06:28:24 PM PDT 24
Finished Jul 22 06:28:34 PM PDT 24
Peak memory 200292 kb
Host smart-3ff474f0-9bed-4a74-9631-5e6fd55d39b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050733578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1050733578
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2667262746
Short name T484
Test name
Test status
Simulation time 100267042 ps
CPU time 4.95 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:28:30 PM PDT 24
Peak memory 200248 kb
Host smart-b36073ea-2ff0-4205-9840-0b48862f40b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667262746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2667262746
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2288888149
Short name T67
Test name
Test status
Simulation time 63722401832 ps
CPU time 807.34 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:42:11 PM PDT 24
Peak memory 415248 kb
Host smart-fe3708c5-4f10-4f10-892b-30e1fba8bc95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288888149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2288888149
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3777473526
Short name T232
Test name
Test status
Simulation time 1619936949 ps
CPU time 3.35 seconds
Started Jul 22 06:29:22 PM PDT 24
Finished Jul 22 06:29:25 PM PDT 24
Peak memory 200244 kb
Host smart-f1e8bcf7-d146-4031-9650-1898010e2b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777473526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3777473526
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1745164270
Short name T181
Test name
Test status
Simulation time 20710560 ps
CPU time 0.61 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:28:26 PM PDT 24
Peak memory 196152 kb
Host smart-7d40ecc6-25db-4e25-bf35-dcfea8b5fa1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745164270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1745164270
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1330781679
Short name T47
Test name
Test status
Simulation time 3779571494 ps
CPU time 102.81 seconds
Started Jul 22 06:28:27 PM PDT 24
Finished Jul 22 06:30:10 PM PDT 24
Peak memory 200324 kb
Host smart-0801226f-3a6c-489c-9131-cec50b8a5f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330781679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1330781679
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2672211474
Short name T204
Test name
Test status
Simulation time 958597847 ps
CPU time 25.94 seconds
Started Jul 22 06:28:29 PM PDT 24
Finished Jul 22 06:28:55 PM PDT 24
Peak memory 200224 kb
Host smart-86d4a95c-e6da-4906-b3f8-384d4ee48447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672211474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2672211474
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1191733053
Short name T423
Test name
Test status
Simulation time 5162192671 ps
CPU time 464.64 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:36:08 PM PDT 24
Peak memory 688364 kb
Host smart-a95627f7-3ef6-4f6a-84eb-2e970e451f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191733053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1191733053
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1207987368
Short name T458
Test name
Test status
Simulation time 8952437912 ps
CPU time 152.79 seconds
Started Jul 22 06:28:29 PM PDT 24
Finished Jul 22 06:31:02 PM PDT 24
Peak memory 200340 kb
Host smart-19e6ce8e-9e4f-4ff9-b275-0afa33fb2ae7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207987368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1207987368
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1266287700
Short name T261
Test name
Test status
Simulation time 4638829591 ps
CPU time 80.24 seconds
Started Jul 22 06:28:27 PM PDT 24
Finished Jul 22 06:29:48 PM PDT 24
Peak memory 200356 kb
Host smart-5ffbb37a-2874-4834-b6d5-528f43ee2e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266287700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1266287700
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1581589016
Short name T425
Test name
Test status
Simulation time 550698921 ps
CPU time 8.88 seconds
Started Jul 22 06:29:01 PM PDT 24
Finished Jul 22 06:29:11 PM PDT 24
Peak memory 200272 kb
Host smart-8ddf7605-9be8-4e04-b2ee-b4f53000db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581589016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1581589016
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.302376836
Short name T98
Test name
Test status
Simulation time 25141435988 ps
CPU time 144.52 seconds
Started Jul 22 06:29:21 PM PDT 24
Finished Jul 22 06:31:46 PM PDT 24
Peak memory 200268 kb
Host smart-321e2891-9a2f-4a34-8e16-c7168467c558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302376836 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.302376836
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2371818946
Short name T401
Test name
Test status
Simulation time 4070997236 ps
CPU time 14.04 seconds
Started Jul 22 06:28:46 PM PDT 24
Finished Jul 22 06:29:00 PM PDT 24
Peak memory 200316 kb
Host smart-5f661bf9-82b4-4a61-b27a-1367125862a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371818946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2371818946
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.844576591
Short name T513
Test name
Test status
Simulation time 13272772 ps
CPU time 0.6 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:28:34 PM PDT 24
Peak memory 196168 kb
Host smart-47424562-eee3-4ec5-816e-dd54af18049b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844576591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.844576591
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2013167467
Short name T477
Test name
Test status
Simulation time 4568702219 ps
CPU time 83.03 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:29:48 PM PDT 24
Peak memory 200456 kb
Host smart-be75c958-c659-40c4-bb81-df926a80dce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013167467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2013167467
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3611759206
Short name T186
Test name
Test status
Simulation time 3914720365 ps
CPU time 14.25 seconds
Started Jul 22 06:29:11 PM PDT 24
Finished Jul 22 06:29:25 PM PDT 24
Peak memory 200296 kb
Host smart-e0f81dbe-3c60-49ee-953a-6309cc05e8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611759206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3611759206
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1893771298
Short name T176
Test name
Test status
Simulation time 3771095747 ps
CPU time 133.99 seconds
Started Jul 22 06:28:30 PM PDT 24
Finished Jul 22 06:30:45 PM PDT 24
Peak memory 468864 kb
Host smart-7c7bacc5-e45e-482d-a334-9502445441f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893771298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1893771298
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3118775478
Short name T522
Test name
Test status
Simulation time 15506406977 ps
CPU time 97.01 seconds
Started Jul 22 06:28:23 PM PDT 24
Finished Jul 22 06:30:01 PM PDT 24
Peak memory 200268 kb
Host smart-94cf8892-413c-4e09-b08d-6a412d72aed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118775478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3118775478
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2174446683
Short name T241
Test name
Test status
Simulation time 1806238811 ps
CPU time 31.32 seconds
Started Jul 22 06:29:21 PM PDT 24
Finished Jul 22 06:29:53 PM PDT 24
Peak memory 200220 kb
Host smart-9f72c906-ee64-4730-a506-42fd930443c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174446683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2174446683
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.602436154
Short name T349
Test name
Test status
Simulation time 922013454 ps
CPU time 8.51 seconds
Started Jul 22 06:28:29 PM PDT 24
Finished Jul 22 06:28:38 PM PDT 24
Peak memory 200208 kb
Host smart-ee0adeb0-01c3-4ec0-8b3d-43cd84f401bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602436154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.602436154
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1690123768
Short name T135
Test name
Test status
Simulation time 73308324624 ps
CPU time 913.57 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 06:43:45 PM PDT 24
Peak memory 472148 kb
Host smart-b279244a-0efa-4662-b85e-16d92f403258
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690123768 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1690123768
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.205098675
Short name T207
Test name
Test status
Simulation time 3989402776 ps
CPU time 93.57 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:30:07 PM PDT 24
Peak memory 200296 kb
Host smart-6ce6c2b0-9c92-4946-890e-a63ae20f1232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205098675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.205098675
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.322662485
Short name T168
Test name
Test status
Simulation time 44409052 ps
CPU time 0.6 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 06:28:33 PM PDT 24
Peak memory 196208 kb
Host smart-a1063a0c-5263-46c5-8012-69706a284876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322662485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.322662485
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1357690237
Short name T431
Test name
Test status
Simulation time 1264247690 ps
CPU time 74.72 seconds
Started Jul 22 06:28:28 PM PDT 24
Finished Jul 22 06:29:43 PM PDT 24
Peak memory 200304 kb
Host smart-89c5ae6e-47f1-426f-8df3-9f7b458bce85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357690237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1357690237
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2311592789
Short name T235
Test name
Test status
Simulation time 3884651588 ps
CPU time 48.89 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:29:14 PM PDT 24
Peak memory 200368 kb
Host smart-77a9dacf-4937-4e59-935b-56c8280b5188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311592789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2311592789
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4158855647
Short name T153
Test name
Test status
Simulation time 3689704160 ps
CPU time 709.46 seconds
Started Jul 22 06:28:25 PM PDT 24
Finished Jul 22 06:40:15 PM PDT 24
Peak memory 679624 kb
Host smart-440b432f-489e-4a43-a239-49ca9e2fcff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158855647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4158855647
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4053545403
Short name T507
Test name
Test status
Simulation time 35722622460 ps
CPU time 46.54 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:29:21 PM PDT 24
Peak memory 200336 kb
Host smart-4f49a5ac-3f95-46c3-a530-9f304554d959
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053545403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4053545403
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1673013838
Short name T402
Test name
Test status
Simulation time 8062514269 ps
CPU time 149.41 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:31:13 PM PDT 24
Peak memory 200304 kb
Host smart-ac2b6950-218e-45ae-9e0f-75192829e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673013838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1673013838
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3353742204
Short name T224
Test name
Test status
Simulation time 795886719 ps
CPU time 12.14 seconds
Started Jul 22 06:28:27 PM PDT 24
Finished Jul 22 06:28:40 PM PDT 24
Peak memory 200164 kb
Host smart-00cffc0a-90f0-4c78-aba9-2737bfbc69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353742204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3353742204
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2389317335
Short name T330
Test name
Test status
Simulation time 76124259476 ps
CPU time 1386.84 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:51:42 PM PDT 24
Peak memory 749380 kb
Host smart-f6684faa-6298-4795-8c3a-33c7e990ae04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389317335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2389317335
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.467353211
Short name T100
Test name
Test status
Simulation time 22803618342 ps
CPU time 143.57 seconds
Started Jul 22 06:28:46 PM PDT 24
Finished Jul 22 06:31:10 PM PDT 24
Peak memory 200312 kb
Host smart-e146677c-eff6-4206-9034-e64012c3649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467353211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.467353211
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3219520805
Short name T358
Test name
Test status
Simulation time 36212117 ps
CPU time 0.6 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 06:28:33 PM PDT 24
Peak memory 196196 kb
Host smart-117dc332-468b-4554-a633-289c4b3b0319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219520805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3219520805
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1839287478
Short name T414
Test name
Test status
Simulation time 6750907383 ps
CPU time 71.75 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:29:46 PM PDT 24
Peak memory 200288 kb
Host smart-92c471a7-8ca6-4adb-aa0b-70610917550e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839287478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1839287478
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3418227892
Short name T488
Test name
Test status
Simulation time 13221401488 ps
CPU time 60.17 seconds
Started Jul 22 06:29:02 PM PDT 24
Finished Jul 22 06:30:03 PM PDT 24
Peak memory 200312 kb
Host smart-51c3e91b-52d0-487d-b9e1-179f14ce557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418227892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3418227892
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2784343196
Short name T301
Test name
Test status
Simulation time 8319389627 ps
CPU time 777.64 seconds
Started Jul 22 06:29:02 PM PDT 24
Finished Jul 22 06:42:01 PM PDT 24
Peak memory 683772 kb
Host smart-20730d78-cb5a-4239-98d6-daf8c0bc0219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784343196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2784343196
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1757885259
Short name T473
Test name
Test status
Simulation time 908922244 ps
CPU time 49.41 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:29:22 PM PDT 24
Peak memory 200240 kb
Host smart-173a0c9c-8361-4682-abe4-8a7e7bbb4bb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757885259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1757885259
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.235408729
Short name T311
Test name
Test status
Simulation time 7425746539 ps
CPU time 142.46 seconds
Started Jul 22 06:28:30 PM PDT 24
Finished Jul 22 06:30:53 PM PDT 24
Peak memory 200264 kb
Host smart-4b18bd3b-dee9-44dd-a51a-b0bc2ba5e30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235408729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.235408729
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2157665325
Short name T396
Test name
Test status
Simulation time 2757294202 ps
CPU time 12 seconds
Started Jul 22 06:28:24 PM PDT 24
Finished Jul 22 06:28:36 PM PDT 24
Peak memory 200368 kb
Host smart-915db122-261e-420f-a04c-72a88aa535c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157665325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2157665325
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1273276982
Short name T483
Test name
Test status
Simulation time 35082734870 ps
CPU time 2101.69 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 07:03:34 PM PDT 24
Peak memory 749976 kb
Host smart-a29e5acb-8c22-4bd9-9835-8053d788cd0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273276982 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1273276982
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1048619333
Short name T443
Test name
Test status
Simulation time 97811237592 ps
CPU time 123.35 seconds
Started Jul 22 06:28:29 PM PDT 24
Finished Jul 22 06:30:33 PM PDT 24
Peak memory 200292 kb
Host smart-9fcdf971-0b8c-4e9d-9206-8118243d0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048619333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1048619333
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2400596412
Short name T307
Test name
Test status
Simulation time 91970754 ps
CPU time 0.6 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:28:34 PM PDT 24
Peak memory 195972 kb
Host smart-75205ae2-719e-43b4-954e-498ce2f815d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400596412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2400596412
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1821633620
Short name T34
Test name
Test status
Simulation time 582453899 ps
CPU time 35.42 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:29:19 PM PDT 24
Peak memory 200264 kb
Host smart-cd633a55-98c3-4777-a513-8396081e5c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821633620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1821633620
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3676473313
Short name T239
Test name
Test status
Simulation time 12143129672 ps
CPU time 54.72 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:29:39 PM PDT 24
Peak memory 208568 kb
Host smart-df80375f-326e-4603-9f5f-a39a2ceeeed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676473313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3676473313
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1008011028
Short name T498
Test name
Test status
Simulation time 24695821047 ps
CPU time 997.32 seconds
Started Jul 22 06:32:02 PM PDT 24
Finished Jul 22 06:48:40 PM PDT 24
Peak memory 710672 kb
Host smart-d4bb84ba-a7e6-4cce-98e2-885740eeab04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008011028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1008011028
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3457508178
Short name T53
Test name
Test status
Simulation time 17611082999 ps
CPU time 210.33 seconds
Started Jul 22 06:28:40 PM PDT 24
Finished Jul 22 06:32:11 PM PDT 24
Peak memory 200324 kb
Host smart-4185d1e0-431c-433b-bbc6-76315376a683
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457508178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3457508178
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1719225210
Short name T97
Test name
Test status
Simulation time 5711927009 ps
CPU time 47.6 seconds
Started Jul 22 06:28:35 PM PDT 24
Finished Jul 22 06:29:23 PM PDT 24
Peak memory 200236 kb
Host smart-bd72eb7e-4b09-4674-a464-eefd9803c7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719225210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1719225210
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.597409351
Short name T385
Test name
Test status
Simulation time 909385603 ps
CPU time 6.29 seconds
Started Jul 22 06:28:34 PM PDT 24
Finished Jul 22 06:28:41 PM PDT 24
Peak memory 200296 kb
Host smart-cb461bee-6aed-4c31-843a-5b2e9a8e9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597409351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.597409351
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.488583308
Short name T55
Test name
Test status
Simulation time 59607556709 ps
CPU time 1131.72 seconds
Started Jul 22 06:28:34 PM PDT 24
Finished Jul 22 06:47:27 PM PDT 24
Peak memory 623560 kb
Host smart-368f107d-01fa-4b25-9d6d-c229458f47ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488583308 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.488583308
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.213647529
Short name T325
Test name
Test status
Simulation time 19325718345 ps
CPU time 93.9 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:30:07 PM PDT 24
Peak memory 200356 kb
Host smart-0f1e4f33-b94a-4fd7-a4ad-3da92bb52607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213647529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.213647529
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2561461331
Short name T476
Test name
Test status
Simulation time 34282541 ps
CPU time 0.57 seconds
Started Jul 22 06:28:31 PM PDT 24
Finished Jul 22 06:28:33 PM PDT 24
Peak memory 195116 kb
Host smart-63021587-9cc7-4b2d-9a45-579d6f087a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561461331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2561461331
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.502590862
Short name T200
Test name
Test status
Simulation time 6073920419 ps
CPU time 95.83 seconds
Started Jul 22 06:28:44 PM PDT 24
Finished Jul 22 06:30:20 PM PDT 24
Peak memory 200312 kb
Host smart-021da06c-41e8-4432-b5f3-cd4546e93bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502590862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.502590862
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2589713160
Short name T227
Test name
Test status
Simulation time 773128730 ps
CPU time 3.15 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:28:37 PM PDT 24
Peak memory 200244 kb
Host smart-0b568788-c5a2-4c32-9528-7f717d573acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589713160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2589713160
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.212451247
Short name T192
Test name
Test status
Simulation time 4861576895 ps
CPU time 827.29 seconds
Started Jul 22 06:29:07 PM PDT 24
Finished Jul 22 06:42:54 PM PDT 24
Peak memory 641132 kb
Host smart-575f84f0-ff15-4301-9d3e-557117704db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212451247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.212451247
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3145600267
Short name T437
Test name
Test status
Simulation time 668251066 ps
CPU time 9.29 seconds
Started Jul 22 06:28:42 PM PDT 24
Finished Jul 22 06:28:51 PM PDT 24
Peak memory 200164 kb
Host smart-e27e6791-cfd0-4744-8fea-ced4dadfb3fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145600267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3145600267
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1294570645
Short name T384
Test name
Test status
Simulation time 4453361153 ps
CPU time 118.87 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:30:33 PM PDT 24
Peak memory 216472 kb
Host smart-53ff3c2b-3207-422e-b214-92bb335f8e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294570645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1294570645
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.804040735
Short name T108
Test name
Test status
Simulation time 251336769 ps
CPU time 4.44 seconds
Started Jul 22 06:28:35 PM PDT 24
Finished Jul 22 06:28:40 PM PDT 24
Peak memory 200244 kb
Host smart-ede6c661-5012-4637-a8b6-7242fa144cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804040735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.804040735
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.743429868
Short name T134
Test name
Test status
Simulation time 7157511498 ps
CPU time 124.6 seconds
Started Jul 22 06:28:32 PM PDT 24
Finished Jul 22 06:30:38 PM PDT 24
Peak memory 200340 kb
Host smart-ce5abd84-8dfb-48c3-b211-2293a2c6417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743429868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.743429868
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4019806998
Short name T255
Test name
Test status
Simulation time 19807728 ps
CPU time 0.59 seconds
Started Jul 22 06:29:04 PM PDT 24
Finished Jul 22 06:29:05 PM PDT 24
Peak memory 196204 kb
Host smart-5a8b0f0c-3bd1-4ea3-9e18-16e38a83671d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019806998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4019806998
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1979547071
Short name T12
Test name
Test status
Simulation time 3810376186 ps
CPU time 52.67 seconds
Started Jul 22 06:32:02 PM PDT 24
Finished Jul 22 06:32:59 PM PDT 24
Peak memory 200016 kb
Host smart-95fc45d2-35ee-4829-b697-342bb71bb61c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979547071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1979547071
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1159816641
Short name T81
Test name
Test status
Simulation time 687802048 ps
CPU time 6.44 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:28:40 PM PDT 24
Peak memory 200292 kb
Host smart-ca836654-6d50-4fff-acf1-5358a4414481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159816641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1159816641
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1821946220
Short name T196
Test name
Test status
Simulation time 2345038886 ps
CPU time 424.36 seconds
Started Jul 22 06:29:04 PM PDT 24
Finished Jul 22 06:36:08 PM PDT 24
Peak memory 677752 kb
Host smart-02a440ce-3bf4-4c41-999e-28b0b763673e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821946220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1821946220
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2884010109
Short name T390
Test name
Test status
Simulation time 32553157244 ps
CPU time 114 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:30:28 PM PDT 24
Peak memory 200336 kb
Host smart-5d74d832-8266-4d16-b1a5-bf06aaa5d257
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884010109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2884010109
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2046155193
Short name T480
Test name
Test status
Simulation time 2183946630 ps
CPU time 36.93 seconds
Started Jul 22 06:28:34 PM PDT 24
Finished Jul 22 06:29:12 PM PDT 24
Peak memory 200312 kb
Host smart-941230cf-d3ed-4fff-be5f-f533bf29cb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046155193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2046155193
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1494881860
Short name T246
Test name
Test status
Simulation time 92086229 ps
CPU time 1.07 seconds
Started Jul 22 06:28:33 PM PDT 24
Finished Jul 22 06:28:36 PM PDT 24
Peak memory 200056 kb
Host smart-85e6b00b-bf62-4b63-964d-1ca502f38a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494881860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1494881860
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3478257316
Short name T39
Test name
Test status
Simulation time 23404903447 ps
CPU time 1933.78 seconds
Started Jul 22 06:28:42 PM PDT 24
Finished Jul 22 07:00:56 PM PDT 24
Peak memory 674448 kb
Host smart-004d2277-c2aa-4580-a9bb-373a901e13d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478257316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3478257316
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3026727724
Short name T183
Test name
Test status
Simulation time 3477583180 ps
CPU time 12.6 seconds
Started Jul 22 06:28:41 PM PDT 24
Finished Jul 22 06:28:54 PM PDT 24
Peak memory 200320 kb
Host smart-c687a11e-0c08-40be-ac16-6f36a13f5db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026727724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3026727724
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1146518114
Short name T218
Test name
Test status
Simulation time 17782478 ps
CPU time 0.6 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:28:44 PM PDT 24
Peak memory 195816 kb
Host smart-330c2a9f-1421-414b-b477-5e27be78ac19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146518114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1146518114
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2334643702
Short name T482
Test name
Test status
Simulation time 5455440892 ps
CPU time 71.46 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:29:55 PM PDT 24
Peak memory 215696 kb
Host smart-040b5158-8293-4e2a-8e99-3b7f53bcb525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334643702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2334643702
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1721075009
Short name T71
Test name
Test status
Simulation time 101379446 ps
CPU time 2.9 seconds
Started Jul 22 06:28:42 PM PDT 24
Finished Jul 22 06:28:46 PM PDT 24
Peak memory 200240 kb
Host smart-fb2b4da8-4fe4-4ca7-ba3b-e9fbaef61e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721075009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1721075009
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.12352319
Short name T208
Test name
Test status
Simulation time 1198703156 ps
CPU time 138.44 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:31:03 PM PDT 24
Peak memory 586288 kb
Host smart-baa42fa9-d911-4a6d-b7df-4fdf6a62697d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12352319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.12352319
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.4243729025
Short name T164
Test name
Test status
Simulation time 17562904398 ps
CPU time 97.43 seconds
Started Jul 22 06:29:45 PM PDT 24
Finished Jul 22 06:31:23 PM PDT 24
Peak memory 200340 kb
Host smart-c0244ab3-54b2-462e-9678-0a73cf4dac61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243729025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4243729025
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.847316500
Short name T379
Test name
Test status
Simulation time 699958038 ps
CPU time 37.56 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:29:21 PM PDT 24
Peak memory 200232 kb
Host smart-b70e331d-b0b6-4790-9d35-35af1837c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847316500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.847316500
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1591473530
Short name T393
Test name
Test status
Simulation time 454710146 ps
CPU time 6.46 seconds
Started Jul 22 06:28:34 PM PDT 24
Finished Jul 22 06:28:41 PM PDT 24
Peak memory 200212 kb
Host smart-948b5314-6d6b-4e39-8651-0fb8ebaa27bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591473530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1591473530
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4149022079
Short name T461
Test name
Test status
Simulation time 148944839861 ps
CPU time 1917.05 seconds
Started Jul 22 06:29:45 PM PDT 24
Finished Jul 22 07:01:45 PM PDT 24
Peak memory 732136 kb
Host smart-d75c8b5f-b17c-4d44-aad4-6d1cf21d9acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149022079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4149022079
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1839938646
Short name T276
Test name
Test status
Simulation time 56461855938 ps
CPU time 145.31 seconds
Started Jul 22 06:28:40 PM PDT 24
Finished Jul 22 06:31:06 PM PDT 24
Peak memory 200320 kb
Host smart-d8f7bca9-ee01-448f-84c3-38d29bb216a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839938646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1839938646
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2025854820
Short name T273
Test name
Test status
Simulation time 34030713 ps
CPU time 0.59 seconds
Started Jul 22 06:28:44 PM PDT 24
Finished Jul 22 06:28:45 PM PDT 24
Peak memory 195156 kb
Host smart-e346fafb-3745-4037-b865-6519ae1d2ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025854820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2025854820
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.465865794
Short name T37
Test name
Test status
Simulation time 3526121470 ps
CPU time 58.17 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:29:42 PM PDT 24
Peak memory 200328 kb
Host smart-31b5d734-809e-48b9-b8ab-b040386c6b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465865794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.465865794
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1814375806
Short name T339
Test name
Test status
Simulation time 8841796409 ps
CPU time 24.63 seconds
Started Jul 22 06:28:42 PM PDT 24
Finished Jul 22 06:29:07 PM PDT 24
Peak memory 200336 kb
Host smart-81ee8aee-4f90-446d-a761-65ef03f24593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814375806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1814375806
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2501617078
Short name T314
Test name
Test status
Simulation time 22058970614 ps
CPU time 831.6 seconds
Started Jul 22 06:28:44 PM PDT 24
Finished Jul 22 06:42:36 PM PDT 24
Peak memory 707020 kb
Host smart-8554f189-77a3-4b51-b60d-83fed6bbc560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501617078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2501617078
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1740385077
Short name T234
Test name
Test status
Simulation time 42071105931 ps
CPU time 149.44 seconds
Started Jul 22 06:28:42 PM PDT 24
Finished Jul 22 06:31:12 PM PDT 24
Peak memory 200292 kb
Host smart-54988286-75dd-421e-8e15-16b8b4934685
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740385077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1740385077
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1539939754
Short name T191
Test name
Test status
Simulation time 41096553468 ps
CPU time 175.61 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:31:40 PM PDT 24
Peak memory 200368 kb
Host smart-b2aa4f4a-8e92-4098-b6c8-fb967676d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539939754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1539939754
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.354320781
Short name T209
Test name
Test status
Simulation time 152239374 ps
CPU time 7.01 seconds
Started Jul 22 06:28:43 PM PDT 24
Finished Jul 22 06:28:51 PM PDT 24
Peak memory 200224 kb
Host smart-d7a598fd-6b53-438a-9c85-45d731537722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354320781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.354320781
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4269887791
Short name T389
Test name
Test status
Simulation time 97900715484 ps
CPU time 680.98 seconds
Started Jul 22 06:28:44 PM PDT 24
Finished Jul 22 06:40:06 PM PDT 24
Peak memory 663792 kb
Host smart-7c0cbc82-9a8e-43a9-bd60-15d33662f671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269887791 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4269887791
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3181676086
Short name T392
Test name
Test status
Simulation time 1436390177 ps
CPU time 93.75 seconds
Started Jul 22 06:28:45 PM PDT 24
Finished Jul 22 06:30:20 PM PDT 24
Peak memory 200212 kb
Host smart-75f1bacd-ec84-430b-8379-ca964b6cb078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181676086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3181676086
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3414155914
Short name T195
Test name
Test status
Simulation time 11111031 ps
CPU time 0.61 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 195584 kb
Host smart-b5d48927-91cb-4b3b-9a15-d7d769966d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414155914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3414155914
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2770364607
Short name T154
Test name
Test status
Simulation time 1341991731 ps
CPU time 79.66 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:28:59 PM PDT 24
Peak memory 200260 kb
Host smart-c1ab72b7-9e13-4f7a-bf49-396dd75a87f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770364607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2770364607
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3556246324
Short name T30
Test name
Test status
Simulation time 1084536871 ps
CPU time 28.83 seconds
Started Jul 22 06:27:38 PM PDT 24
Finished Jul 22 06:28:08 PM PDT 24
Peak memory 200248 kb
Host smart-fef6bef1-660e-41ed-95ca-33e2db3c8106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556246324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3556246324
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1890627005
Short name T441
Test name
Test status
Simulation time 9732542734 ps
CPU time 812.01 seconds
Started Jul 22 06:29:39 PM PDT 24
Finished Jul 22 06:43:11 PM PDT 24
Peak memory 750380 kb
Host smart-567d7b8c-9015-4176-86ee-871e3f44fba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890627005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1890627005
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3236569605
Short name T51
Test name
Test status
Simulation time 5358187767 ps
CPU time 94.6 seconds
Started Jul 22 06:27:32 PM PDT 24
Finished Jul 22 06:29:07 PM PDT 24
Peak memory 200328 kb
Host smart-d3fd5423-b6f0-4e72-9723-aaa8d0ecb18a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236569605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3236569605
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.765793188
Short name T352
Test name
Test status
Simulation time 10377763168 ps
CPU time 189.93 seconds
Started Jul 22 06:27:27 PM PDT 24
Finished Jul 22 06:30:37 PM PDT 24
Peak memory 200340 kb
Host smart-de79d484-a99c-4e0d-89e6-1f3c4c466bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765793188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.765793188
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3541638436
Short name T374
Test name
Test status
Simulation time 102040416 ps
CPU time 4.36 seconds
Started Jul 22 06:27:37 PM PDT 24
Finished Jul 22 06:27:43 PM PDT 24
Peak memory 200260 kb
Host smart-423f5073-dd3f-4b99-8705-cc7ec9768ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541638436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3541638436
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1604435631
Short name T147
Test name
Test status
Simulation time 11699102704 ps
CPU time 263.49 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:31:58 PM PDT 24
Peak memory 486260 kb
Host smart-b339d7e1-b312-4a76-ab9d-10a15b366a75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604435631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1604435631
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1028908887
Short name T14
Test name
Test status
Simulation time 70361711266 ps
CPU time 1282.23 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:49:07 PM PDT 24
Peak memory 614764 kb
Host smart-f126ca0c-2760-48e9-9639-87f583c04cef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028908887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1028908887
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.925335755
Short name T395
Test name
Test status
Simulation time 10096689797 ps
CPU time 116.92 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:29:31 PM PDT 24
Peak memory 200288 kb
Host smart-f377d165-9fed-41ba-a01e-4f3a00244232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925335755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.925335755
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1397900763
Short name T69
Test name
Test status
Simulation time 3024547465 ps
CPU time 20.58 seconds
Started Jul 22 06:27:39 PM PDT 24
Finished Jul 22 06:28:00 PM PDT 24
Peak memory 200292 kb
Host smart-44a17547-c152-4784-8f42-ced2ce7143af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397900763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1397900763
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2522754286
Short name T470
Test name
Test status
Simulation time 10743855119 ps
CPU time 48.16 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:28:29 PM PDT 24
Peak memory 216740 kb
Host smart-8b677373-c302-4b24-a58a-6de9d2cf810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522754286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2522754286
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1855443224
Short name T244
Test name
Test status
Simulation time 19341715237 ps
CPU time 820.01 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:41:25 PM PDT 24
Peak memory 726048 kb
Host smart-e07013f4-2ff1-4252-8fc1-8066f2a219d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855443224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1855443224
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1708434837
Short name T400
Test name
Test status
Simulation time 8717230378 ps
CPU time 154.19 seconds
Started Jul 22 06:27:46 PM PDT 24
Finished Jul 22 06:30:21 PM PDT 24
Peak memory 200296 kb
Host smart-1d573be8-25a8-4033-975a-8c1763c2b87c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708434837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1708434837
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.81055242
Short name T446
Test name
Test status
Simulation time 4048362947 ps
CPU time 77.23 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:28:58 PM PDT 24
Peak memory 200264 kb
Host smart-d2dce564-12cb-409d-ad2a-6430f53ff702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81055242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.81055242
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.711546542
Short name T486
Test name
Test status
Simulation time 111541274 ps
CPU time 1.04 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:27:46 PM PDT 24
Peak memory 200044 kb
Host smart-71269fcc-5249-4b8b-bd09-f3bc3a4adaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711546542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.711546542
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2383936180
Short name T10
Test name
Test status
Simulation time 189823723375 ps
CPU time 783.61 seconds
Started Jul 22 06:27:33 PM PDT 24
Finished Jul 22 06:40:38 PM PDT 24
Peak memory 589564 kb
Host smart-1d4ead4d-de85-4a4a-af5b-c909fa5889c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383936180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2383936180
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2049879820
Short name T271
Test name
Test status
Simulation time 9499643943 ps
CPU time 108.23 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:29:38 PM PDT 24
Peak memory 200372 kb
Host smart-ea07e931-783a-44a8-a98e-e0082f35b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049879820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2049879820
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.216350789
Short name T17
Test name
Test status
Simulation time 12574553 ps
CPU time 0.58 seconds
Started Jul 22 06:27:45 PM PDT 24
Finished Jul 22 06:27:47 PM PDT 24
Peak memory 196140 kb
Host smart-096496c4-c14b-4b44-82ef-5372c6530160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216350789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.216350789
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2663635182
Short name T109
Test name
Test status
Simulation time 4045506306 ps
CPU time 53.98 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:38 PM PDT 24
Peak memory 200300 kb
Host smart-c3d42fbf-7fd5-4ac8-b366-50e97dc9a3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663635182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2663635182
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3139825590
Short name T350
Test name
Test status
Simulation time 64281996933 ps
CPU time 56.36 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:44 PM PDT 24
Peak memory 200312 kb
Host smart-8f04baaf-3b20-497a-ab40-d75759a1db30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139825590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3139825590
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3831365705
Short name T50
Test name
Test status
Simulation time 182243402 ps
CPU time 21.33 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:09 PM PDT 24
Peak memory 235996 kb
Host smart-1a414579-b8dd-479a-9814-6fae7907f5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831365705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3831365705
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1969245183
Short name T457
Test name
Test status
Simulation time 7298364544 ps
CPU time 97.35 seconds
Started Jul 22 06:27:40 PM PDT 24
Finished Jul 22 06:29:18 PM PDT 24
Peak memory 200300 kb
Host smart-accb5786-c404-4964-b002-78a6aaf955c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969245183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1969245183
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3804317409
Short name T258
Test name
Test status
Simulation time 6964924816 ps
CPU time 121.04 seconds
Started Jul 22 06:28:07 PM PDT 24
Finished Jul 22 06:30:08 PM PDT 24
Peak memory 216472 kb
Host smart-f7688142-2960-411c-958b-3124b3f1c9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804317409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3804317409
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.824027660
Short name T242
Test name
Test status
Simulation time 570737733 ps
CPU time 2.38 seconds
Started Jul 22 06:27:41 PM PDT 24
Finished Jul 22 06:27:49 PM PDT 24
Peak memory 200264 kb
Host smart-87a5a31e-db45-4359-9591-fb309378ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824027660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.824027660
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.930713786
Short name T211
Test name
Test status
Simulation time 12131324801 ps
CPU time 223.35 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:31:32 PM PDT 24
Peak memory 200216 kb
Host smart-ee000bd5-7c27-4509-b555-b2785a474bb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930713786 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.930713786
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.715356201
Short name T24
Test name
Test status
Simulation time 39519722946 ps
CPU time 2469.32 seconds
Started Jul 22 06:27:45 PM PDT 24
Finished Jul 22 07:08:56 PM PDT 24
Peak memory 710588 kb
Host smart-374c88af-d6ac-41e7-b454-9568b06f148c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715356201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.715356201
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2529013677
Short name T526
Test name
Test status
Simulation time 26085057428 ps
CPU time 163.73 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:30:27 PM PDT 24
Peak memory 200316 kb
Host smart-5a02db17-51a9-450d-9df6-4e2c18df2ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529013677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2529013677
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.154091560
Short name T173
Test name
Test status
Simulation time 42570253 ps
CPU time 0.61 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:27:50 PM PDT 24
Peak memory 196240 kb
Host smart-360fc375-63b5-48fc-9a87-9e5635c62aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154091560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.154091560
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.833887170
Short name T36
Test name
Test status
Simulation time 3316125615 ps
CPU time 48.22 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:32 PM PDT 24
Peak memory 200336 kb
Host smart-de51686f-6805-4831-90c3-4369227946c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833887170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.833887170
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4048073874
Short name T231
Test name
Test status
Simulation time 6682307108 ps
CPU time 49.44 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:28:35 PM PDT 24
Peak memory 200316 kb
Host smart-6ab3ea85-1694-4d37-a0c5-34e992b49bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048073874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4048073874
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2340646130
Short name T413
Test name
Test status
Simulation time 4647566015 ps
CPU time 241.37 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:31:43 PM PDT 24
Peak memory 354504 kb
Host smart-0ba79f65-cfeb-424c-99f2-001298c8dee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340646130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2340646130
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.248165038
Short name T187
Test name
Test status
Simulation time 22572890175 ps
CPU time 262.1 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:32:07 PM PDT 24
Peak memory 200292 kb
Host smart-989100fe-be28-48a7-bbb4-ecaa70fb8bc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248165038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.248165038
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.281055363
Short name T398
Test name
Test status
Simulation time 26627929222 ps
CPU time 100.92 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:29:26 PM PDT 24
Peak memory 200344 kb
Host smart-1041b1ab-9107-4c8e-9e5f-864d7699ca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281055363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.281055363
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3996266678
Short name T27
Test name
Test status
Simulation time 3577601065 ps
CPU time 16.51 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:28:00 PM PDT 24
Peak memory 200312 kb
Host smart-6d17846a-c4f0-4403-94a9-e88ed83440d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996266678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3996266678
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2737405705
Short name T410
Test name
Test status
Simulation time 22456435327 ps
CPU time 1807.22 seconds
Started Jul 22 06:29:39 PM PDT 24
Finished Jul 22 06:59:48 PM PDT 24
Peak memory 716816 kb
Host smart-a8b41018-5565-4ae7-91e6-8642e83856db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737405705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2737405705
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.476593470
Short name T110
Test name
Test status
Simulation time 6679295339 ps
CPU time 51.8 seconds
Started Jul 22 06:29:39 PM PDT 24
Finished Jul 22 06:30:31 PM PDT 24
Peak memory 200312 kb
Host smart-8b5129bf-62e7-4827-891b-4bb7bc89a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476593470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.476593470
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2745431778
Short name T331
Test name
Test status
Simulation time 14574843 ps
CPU time 0.59 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 196172 kb
Host smart-9c39234e-2614-4b5b-a28f-5b27335a4547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745431778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2745431778
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3882925122
Short name T28
Test name
Test status
Simulation time 3453373376 ps
CPU time 48.03 seconds
Started Jul 22 06:28:19 PM PDT 24
Finished Jul 22 06:29:08 PM PDT 24
Peak memory 200308 kb
Host smart-84329ad2-e6ac-4a6d-a434-c29973858bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882925122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3882925122
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.848741133
Short name T151
Test name
Test status
Simulation time 2334977521 ps
CPU time 44.38 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:28:28 PM PDT 24
Peak memory 200272 kb
Host smart-6e7f2968-55ef-4804-acc5-ef886a396dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848741133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.848741133
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2996452952
Short name T524
Test name
Test status
Simulation time 12359557604 ps
CPU time 638.89 seconds
Started Jul 22 06:27:43 PM PDT 24
Finished Jul 22 06:38:23 PM PDT 24
Peak memory 685008 kb
Host smart-1968b969-cd03-4aae-a72b-ef15e016d3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996452952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2996452952
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3687938581
Short name T105
Test name
Test status
Simulation time 101101186187 ps
CPU time 191.86 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:30:55 PM PDT 24
Peak memory 200348 kb
Host smart-5c5e61f3-9b2c-4288-a8a4-482b6c8ce781
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687938581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3687938581
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2877194160
Short name T472
Test name
Test status
Simulation time 50632937884 ps
CPU time 118.86 seconds
Started Jul 22 06:27:44 PM PDT 24
Finished Jul 22 06:29:45 PM PDT 24
Peak memory 200320 kb
Host smart-cb530000-36c6-4a2f-86d9-6668ce203443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877194160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2877194160
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1981518151
Short name T254
Test name
Test status
Simulation time 209018437 ps
CPU time 3.64 seconds
Started Jul 22 06:27:42 PM PDT 24
Finished Jul 22 06:27:46 PM PDT 24
Peak memory 200232 kb
Host smart-57c7b36d-79e4-4634-a5b0-ce72eb016d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981518151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1981518151
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2482755032
Short name T387
Test name
Test status
Simulation time 1632587687 ps
CPU time 44.14 seconds
Started Jul 22 06:27:47 PM PDT 24
Finished Jul 22 06:28:32 PM PDT 24
Peak memory 200208 kb
Host smart-ace32a7b-d46f-4b7f-9545-70ebd2510eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482755032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2482755032
Directory /workspace/9.hmac_wipe_secret/latest
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