Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19654662	1			T1	10597		T2	7962		T3	39183
all_values[1]	19654662	1			T1	10597		T2	7962		T3	39183
all_values[2]	19654662	1			T1	10597		T2	7962		T3	39183

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

309938

1

T3

2175

T9

1087

T4

1722

auto[1]

58654048

1

T1

31791

T2

23886

T3

115374

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50140696

1

T1

31566

T2

21786

T3

96996

auto[1]

8823290

1

T1

225

T2

2100

T3

20553

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	94820	1			T3	1464		T9	1087		T4	1367
all_values[0]	auto[0]	auto[1]	420	1			T4	2		T6	5		T11	2
all_values[0]	auto[1]	auto[0]	19538598	1			T1	10372		T2	7952		T3	37706
all_values[0]	auto[1]	auto[1]	20824	1			T1	225		T2	10		T3	13
all_values[1]	auto[0]	auto[0]	95852	1			T3	711		T6	55		T7	4
all_values[1]	auto[0]	auto[1]	219	1			T6	4		T7	2		T35	3
all_values[1]	auto[1]	auto[0]	19558251	1			T1	10597		T2	7962		T3	38472
all_values[1]	auto[1]	auto[1]	340	1			T6	4		T7	2		T35	5
all_values[2]	auto[0]	auto[0]	62686	1			T4	92		T5	292		T6	7
all_values[2]	auto[0]	auto[1]	55941	1			T4	261		T5	884		T6	291
all_values[2]	auto[1]	auto[0]	10790489	1			T1	10597		T2	5872		T3	18643
all_values[2]	auto[1]	auto[1]	8745546	1			T2	2090		T3	20540		T9	18365