Summary for Variable hmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for hmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
110236 |
1 |
|
|
T2 |
2 |
|
T9 |
38 |
|
T4 |
18 |
auto[1] |
121532 |
1 |
|
|
T1 |
236 |
|
T2 |
18 |
|
T3 |
36 |
Summary for Variable msg_len_lower_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
15 |
0 |
15 |
100.00 |
User Defined Bins for msg_len_lower_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
len_2050_plus |
82143 |
1 |
|
|
T2 |
8 |
|
T3 |
5 |
|
T9 |
26 |
len_1026_2046 |
6620 |
1 |
|
|
T6 |
15 |
|
T7 |
7 |
|
T78 |
1 |
len_514_1022 |
4721 |
1 |
|
|
T2 |
2 |
|
T10 |
7 |
|
T6 |
5 |
len_2_510 |
3013 |
1 |
|
|
T6 |
7 |
|
T7 |
2 |
|
T80 |
66 |
len_2056 |
192 |
1 |
|
|
T6 |
3 |
|
T7 |
3 |
|
T14 |
2 |
len_2048 |
332 |
1 |
|
|
T6 |
3 |
|
T7 |
1 |
|
T30 |
1 |
len_2040 |
214 |
1 |
|
|
T6 |
1 |
|
T7 |
5 |
|
T14 |
2 |
len_1032 |
189 |
1 |
|
|
T35 |
4 |
|
T134 |
1 |
|
T135 |
5 |
len_1024 |
1880 |
1 |
|
|
T1 |
118 |
|
T6 |
5 |
|
T30 |
1 |
len_1016 |
324 |
1 |
|
|
T10 |
2 |
|
T80 |
2 |
|
T38 |
1 |
len_520 |
248 |
1 |
|
|
T6 |
1 |
|
T80 |
2 |
|
T35 |
1 |
len_512 |
337 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T14 |
3 |
len_504 |
216 |
1 |
|
|
T14 |
1 |
|
T80 |
2 |
|
T35 |
2 |
len_8 |
1330 |
1 |
|
|
T3 |
12 |
|
T5 |
4 |
|
T6 |
10 |
len_0 |
14127 |
1 |
|
|
T3 |
1 |
|
T9 |
4 |
|
T4 |
2 |
Summary for Variable msg_len_upper_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for msg_len_upper_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
len_upper |
114 |
1 |
|
|
T6 |
2 |
|
T11 |
1 |
|
T37 |
1 |
Summary for Cross msg_len_lower_cross
Samples crossed: hmac_en msg_len_lower_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
30 |
0 |
30 |
100.00 |
|
Automatically Generated Cross Bins for msg_len_lower_cross
Bins
hmac_en | msg_len_lower_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
len_2050_plus |
41097 |
1 |
|
|
T2 |
1 |
|
T9 |
16 |
|
T4 |
7 |
auto[0] |
len_1026_2046 |
3710 |
1 |
|
|
T6 |
6 |
|
T7 |
4 |
|
T78 |
1 |
auto[0] |
len_514_1022 |
1957 |
1 |
|
|
T10 |
3 |
|
T6 |
4 |
|
T15 |
3 |
auto[0] |
len_2_510 |
2037 |
1 |
|
|
T6 |
3 |
|
T7 |
2 |
|
T80 |
66 |
auto[0] |
len_2056 |
112 |
1 |
|
|
T6 |
1 |
|
T7 |
3 |
|
T35 |
2 |
auto[0] |
len_2048 |
189 |
1 |
|
|
T6 |
2 |
|
T35 |
2 |
|
T134 |
7 |
auto[0] |
len_2040 |
112 |
1 |
|
|
T7 |
3 |
|
T14 |
1 |
|
T134 |
2 |
auto[0] |
len_1032 |
111 |
1 |
|
|
T35 |
2 |
|
T134 |
1 |
|
T135 |
4 |
auto[0] |
len_1024 |
324 |
1 |
|
|
T6 |
3 |
|
T30 |
1 |
|
T80 |
1 |
auto[0] |
len_1016 |
132 |
1 |
|
|
T10 |
1 |
|
T80 |
2 |
|
T136 |
1 |
auto[0] |
len_520 |
126 |
1 |
|
|
T6 |
1 |
|
T80 |
2 |
|
T136 |
1 |
auto[0] |
len_512 |
195 |
1 |
|
|
T6 |
1 |
|
T14 |
2 |
|
T80 |
1 |
auto[0] |
len_504 |
133 |
1 |
|
|
T14 |
1 |
|
T80 |
2 |
|
T35 |
1 |
auto[0] |
len_8 |
22 |
1 |
|
|
T80 |
2 |
|
T136 |
1 |
|
T137 |
1 |
auto[0] |
len_0 |
4863 |
1 |
|
|
T9 |
3 |
|
T4 |
2 |
|
T23 |
1 |
auto[1] |
len_2050_plus |
41046 |
1 |
|
|
T2 |
7 |
|
T3 |
5 |
|
T9 |
10 |
auto[1] |
len_1026_2046 |
2910 |
1 |
|
|
T6 |
9 |
|
T7 |
3 |
|
T35 |
6 |
auto[1] |
len_514_1022 |
2764 |
1 |
|
|
T2 |
2 |
|
T10 |
4 |
|
T6 |
1 |
auto[1] |
len_2_510 |
976 |
1 |
|
|
T6 |
4 |
|
T35 |
9 |
|
T41 |
8 |
auto[1] |
len_2056 |
80 |
1 |
|
|
T6 |
2 |
|
T14 |
2 |
|
T38 |
1 |
auto[1] |
len_2048 |
143 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T30 |
1 |
auto[1] |
len_2040 |
102 |
1 |
|
|
T6 |
1 |
|
T7 |
2 |
|
T14 |
1 |
auto[1] |
len_1032 |
78 |
1 |
|
|
T35 |
2 |
|
T135 |
1 |
|
T27 |
3 |
auto[1] |
len_1024 |
1556 |
1 |
|
|
T1 |
118 |
|
T6 |
2 |
|
T14 |
2 |
auto[1] |
len_1016 |
192 |
1 |
|
|
T10 |
1 |
|
T38 |
1 |
|
T135 |
2 |
auto[1] |
len_520 |
122 |
1 |
|
|
T35 |
1 |
|
T38 |
2 |
|
T135 |
3 |
auto[1] |
len_512 |
142 |
1 |
|
|
T7 |
1 |
|
T14 |
1 |
|
T11 |
1 |
auto[1] |
len_504 |
83 |
1 |
|
|
T35 |
1 |
|
T38 |
2 |
|
T134 |
3 |
auto[1] |
len_8 |
1308 |
1 |
|
|
T3 |
12 |
|
T5 |
4 |
|
T6 |
10 |
auto[1] |
len_0 |
9264 |
1 |
|
|
T3 |
1 |
|
T9 |
1 |
|
T25 |
4 |
Summary for Cross msg_len_upper_cross
Samples crossed: hmac_en msg_len_upper_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for msg_len_upper_cross
Bins
hmac_en | msg_len_upper_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
len_upper |
57 |
1 |
|
|
T37 |
1 |
|
T54 |
1 |
|
T12 |
2 |
auto[1] |
len_upper |
57 |
1 |
|
|
T6 |
2 |
|
T11 |
1 |
|
T54 |
2 |