Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4785952

1

T1

5271

T2

2665

T3

8600

auto[1]

3216117

1

T2

1310

T3

10806

T9

3557

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3129867

1

T2

1844

T3

5394

T9

4491

auto[1]

4872202

1

T1

5271

T2

2131

T3

14012

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3391808

1

T2

2205

T9

5735

T4

7669

auto[1]

4610261

1

T1

5271

T2

1770

T3

19406

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4882955

1

T1

5271

T2

2453

T3

9541

auto[1]

3119114

1

T2

1522

T3

9865

T9

3018

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7365294	1			T1	5059		T2	3846		T3	17827
fifo_depth[1]	126079	1			T1	149		T2	76		T3	245
fifo_depth[2]	92037	1			T1	58		T2	37		T3	263
fifo_depth[3]	71583	1			T1	5		T2	11		T3	257
fifo_depth[4]	62312	1			T2	3		T3	243		T4	7
fifo_depth[5]	49320	1			T2	2		T3	204		T29	2
fifo_depth[6]	38096	1			T3	159		T5	290		T6	3
fifo_depth[7]	25353	1			T3	110		T5	183		T30	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636775

1

T1

212

T2

129

T3

1579

auto[1]

7365294

1

T1

5059

T2

3846

T3

17827

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7992452

1

T1

5271

T2

3975

T3

19406

auto[1]

9617

1

T26

102

T27

179

T121

20

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28229

1

T2

22

T9

28

T4

71

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33610

1

T8

1

T6

16

T15

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28694

1

T9

1

T4

34

T18

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28948

1

T9

7

T4

41

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

129236

1

T6

35

T15

5

T19

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21220

1

T2

31

T18

6

T6

40

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24054

1

T9

2

T4

113

T18

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20779

1

T4

71

T18

7

T6

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

37049

1

T3

715

T5

323

T6

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

39635

1

T18

6

T6

8

T15

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42213

1

T2

23

T3

84

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34908

1

T2

16

T3

602

T4

85

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46616

1

T1

212

T2

16

T4

23

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38515

1

T3

97

T4

91

T29

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43556

1

T2

21

T3

81

T4

19

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39513

1

T4

33

T5

319

T6

85

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

193182

1

T2

270

T9

2453

T4

1959

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

192190

1

T2

508

T9

4

T4

233

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

197183

1

T9

279

T4

452

T29

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

179427

1

T9

374

T4

715

T29

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1762462

1

T2

648

T9

311

T4

177

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

183601

1

T2

726

T9

296

T4

1149

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

177083

1

T9

698

T4

1657

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

191910

1

T9

1282

T4

997

T10

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

506133

1

T2

233

T3

2311

T9

397

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

537805

1

T3

2

T9

454

T10

30

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

527425

1

T2

531

T3

573

T9

309

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

523236

1

T2

241

T3

1107

T9

180

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

549870

1

T1

5059

T2

211

T3

1244

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

486599

1

T3

4231

T9

1

T4

1784

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

589970

1

T2

478

T3

4533

T4

1168

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

567218

1

T3

3826

T9

420

T4

958

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

219377

1

T2

292

T9

2481

T4

2030

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

223610

1

T2

508

T9

4

T4

233

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

224179

1

T9

280

T4

486

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

207703

1

T9

381

T4

756

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1891419

1

T2

648

T9

311

T4

177

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

204698

1

T2

757

T9

296

T4

1149

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

200741

1

T9

700

T4

1770

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

212439

1

T9

1282

T4

1068

T10

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

543087

1

T2

233

T3

3026

T9

397

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

577184

1

T3

2

T9

454

T10

30

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

569239

1

T2

554

T3

657

T9

314

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

557972

1

T2

257

T3

1709

T9

180

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

596261

1

T1

5271

T2

227

T3

1244

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

524907

1

T3

4328

T9

1

T4

1875

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

633203

1

T2

499

T3

4614

T4

1187

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

606433

1

T3

3826

T9

420

T4

991

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

2034

1

T26

54

T63

140

T140

35

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2190

1

T26

4

T63

103

T140

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1698

1

T140

19

T21

23

T88

138

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

672

1

T27

1

T63

27

T140

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

279

1

T26

44

T63

13

T140

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

123

1

T63

33

T21

12

T141

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

396

1

T140

19

T142

5

T21

51

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

250

1

T63

6

T140

81

T143

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T143

22

T44

35

T33

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

256

1

T27

92

T88

48

T144

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

399

1

T21

81

T44

5

T141

234

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

172

1

T63

78

T73

93

T145

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

225

1

T63

13

T140

9

T21

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

207

1

T27

28

T44

38

T144

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

323

1

T27

58

T140

10

T143

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

298

1

T121

20

T63

44

T21

5

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

193182

1

T2

270

T9

2453

T4

1959

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

192190

1

T2

508

T9

4

T4

233

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

197183

1

T9

279

T4

452

T29

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

179427

1

T9

374

T4

715

T29

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1762462

1

T2

648

T9

311

T4

177

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

183601

1

T2

726

T9

296

T4

1149

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

177083

1

T9

698

T4

1657

T8

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

191910

1

T9

1282

T4

997

T10

22

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

506133

1

T2

233

T3

2311

T9

397

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

537805

1

T3

2

T9

454

T10

30

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

527425

1

T2

531

T3

573

T9

309

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

523236

1

T2

241

T3

1107

T9

180

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

549870

1

T1

5059

T2

211

T3

1244

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

486599

1

T3

4231

T9

1

T4

1784

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

589970

1

T2

478

T3

4533

T4

1168

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

567218

1

T3

3826

T9

420

T4

958

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3847

1

T2

18

T9

27

T4

33

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4137

1

T6

9

T15

8

T7

14

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3811

1

T9

1

T4

24

T18

4

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3774

1

T9

6

T4

27

T19

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

42592

1

T6

27

T15

3

T19

10

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3336

1

T2

15

T18

4

T6

32

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3643

1

T9

2

T4

67

T18

12

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3532

1

T4

45

T18

6

T6

9

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6438

1

T3

95

T5

40

T6

5

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7130

1

T18

4

T6

8

T15

9

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6951

1

T2

10

T3

14

T9

3

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7058

1

T2

7

T3

108

T4

60

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8422

1

T1

149

T2

11

T4

10

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6723

1

T3

15

T4

46

T29

5

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7435

1

T2

15

T3

13

T4

11

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

7250

1

T4

26

T5

40

T6

67

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111

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161

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13

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64

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49

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T5

27

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2

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16

fifo_depth[6]

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109

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1

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92

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1

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T42

111

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7

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18

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10

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16

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26

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4

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7

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1

T3

72

T5

29

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1

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1

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40

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19

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1

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18

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2

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1

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T5

14

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11

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53

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1

T3

7

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53

T14

1

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1

T3

9

T5

64

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1

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1

T5

23

T42

65

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4