Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19654662	1			T1	10597		T2	7962		T3	39183
all_pins[1]	19654662	1			T1	10597		T2	7962		T3	39183
all_pins[2]	19654662	1			T1	10597		T2	7962		T3	39183

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50196405	1			T1	31566		T2	21786		T3	96994
values[0x1]	8767581	1			T1	225		T2	2100		T3	20555
transitions[0x0=>0x1]	8767360	1			T1	225		T2	2100		T3	20555
transitions[0x1=>0x0]	8767375	1			T1	225		T2	2100		T3	20555

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19632992	1			T1	10372		T2	7952		T3	39168
all_pins[0]	values[0x1]	21670	1			T1	225		T2	10		T3	15
all_pins[0]	transitions[0x0=>0x1]	21580	1			T1	225		T2	10		T3	15
all_pins[0]	transitions[0x1=>0x0]	8745471	1			T2	2090		T3	20540		T9	18365
all_pins[1]	values[0x0]	19654297	1			T1	10597		T2	7962		T3	39183
all_pins[1]	values[0x1]	365	1			T6	4		T7	2		T35	5
all_pins[1]	transitions[0x0=>0x1]	300	1			T6	4		T7	2		T35	3
all_pins[1]	transitions[0x1=>0x0]	21605	1			T1	225		T2	10		T3	15
all_pins[2]	values[0x0]	10909116	1			T1	10597		T2	5872		T3	18643
all_pins[2]	values[0x1]	8745546	1			T2	2090		T3	20540		T9	18365
all_pins[2]	transitions[0x0=>0x1]	8745480	1			T2	2090		T3	20540		T9	18365
all_pins[2]	transitions[0x1=>0x0]	299	1			T6	4		T7	2		T35	3