Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1108 1 T6 14 T7 11 T35 18
all_values[1] 1108 1 T6 14 T7 11 T35 18
all_values[2] 1108 1 T6 14 T7 11 T35 18


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1687 1 T6 26 T7 12 T35 24
auto[1] 1637 1 T6 16 T7 21 T35 30


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1142 1 T6 18 T7 17 T35 15
auto[1] 2182 1 T6 24 T7 16 T35 39


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1855 1 T6 26 T7 20 T35 30
auto[1] 1469 1 T6 16 T7 13 T35 24


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 169 1 T6 3 T7 2 T35 1
all_values[0] auto[0] auto[0] auto[1] 116 1 T6 2 T35 2 T27 2
all_values[0] auto[0] auto[1] auto[0] 218 1 T6 2 T7 4 T35 6
all_values[0] auto[0] auto[1] auto[1] 117 1 T6 2 T35 2 T121 3
all_values[0] auto[1] auto[0] auto[1] 246 1 T6 5 T7 2 T35 1
all_values[0] auto[1] auto[1] auto[1] 242 1 T7 3 T35 6 T27 3
all_values[1] auto[0] auto[0] auto[0] 173 1 T6 2 T7 2 T35 3
all_values[1] auto[0] auto[0] auto[1] 134 1 T6 1 T7 1 T35 4
all_values[1] auto[0] auto[1] auto[0] 162 1 T6 2 T7 3 T27 3
all_values[1] auto[0] auto[1] auto[1] 157 1 T6 1 T7 1 T35 3
all_values[1] auto[1] auto[0] auto[1] 234 1 T6 4 T7 1 T35 2
all_values[1] auto[1] auto[1] auto[1] 248 1 T6 4 T7 3 T35 6
all_values[2] auto[0] auto[0] auto[0] 239 1 T6 8 T7 2 T35 3
all_values[2] auto[0] auto[0] auto[1] 101 1 T7 1 T35 3 T27 1
all_values[2] auto[0] auto[1] auto[0] 181 1 T6 1 T7 4 T35 2
all_values[2] auto[0] auto[1] auto[1] 88 1 T6 2 T35 1 T121 4
all_values[2] auto[1] auto[0] auto[1] 275 1 T6 1 T7 1 T35 5
all_values[2] auto[1] auto[1] auto[1] 224 1 T6 2 T7 3 T35 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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