Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4606	1			T2	2		T3	3		T9	11
sha2_none	4527	1			T2	2		T3	5		T9	4
sha2_512	8037	1			T1	225		T2	2		T3	7
sha2_384	7746	1			T2	4		T3	4		T9	9
sha2_256	6686	1			T2	3		T3	6		T4	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19607

1

T1

225

T2

8

T3

13

auto[1]

12435

1

T2

5

T3

12

T9

14

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12195

1

T2

7

T3

9

T9

17

auto[1]

19847

1

T1

225

T2

6

T3

16

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16811

1

T1

225

T2

7

T3

25

disabled

15231

1

T2

6

T9

20

T4

13

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5012	1			T2	2		T3	4		T9	10
key_none	8138	1			T2	1		T3	2		T9	4
key_1024	4577	1			T1	225		T2	2		T3	7
key_512	4103	1			T2	1		T3	2		T9	3
key_384	3564	1			T2	2		T3	1		T9	2
key_256	3357	1			T2	2		T3	5		T9	1
key_128	3206	1			T2	2		T3	4		T9	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T1

225

T2

8

T3

14

auto[1]

12170

1

T2

5

T3

11

T9

16

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31817

1

T1

225

T2

13

T3

25

disabled

225

1

T9

2

T29

1

T6

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1680

1

T2

1

T3

2

T9

2

enabled

auto[0]

auto[0]

auto[1]

1696

1

T3

1

T9

1

T10

1

enabled

auto[0]

auto[1]

auto[0]

1779

1

T2

2

T3

4

T9

1

enabled

auto[0]

auto[1]

auto[1]

1806

1

T2

2

T3

2

T9

2

enabled

auto[1]

auto[0]

auto[0]

4458

1

T1

225

T2

1

T3

4

enabled

auto[1]

auto[0]

auto[1]

1702

1

T3

6

T9

1

T4

3

enabled

auto[1]

auto[1]

auto[0]

1904

1

T2

1

T3

4

T4

3

enabled

auto[1]

auto[1]

auto[1]

1786

1

T3

2

T9

2

T4

2

disabled

auto[0]

auto[0]

auto[0]

1284

1

T2

1

T9

5

T4

2

disabled

auto[0]

auto[0]

auto[1]

1315

1

T2

1

T9

2

T4

1

disabled

auto[0]

auto[1]

auto[0]

1321

1

T9

1

T4

1

T29

1

disabled

auto[0]

auto[1]

auto[1]

1314

1

T9

3

T4

2

T8

1

disabled

auto[1]

auto[0]

auto[0]

6227

1

T2

2

T9

2

T4

2

disabled

auto[1]

auto[0]

auto[1]

1245

1

T2

2

T9

2

T4

1

disabled

auto[1]

auto[1]

auto[0]

1219

1

T9

2

T4

3

T8

1

disabled

auto[1]

auto[1]

auto[1]

1306

1

T9

3

T4

1

T10

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16724

1

T1

225

T2

7

T3

25

enabled

disabled

87

1

T9

1

T6

1

T35

3

disabled

disabled

138

1

T9

1

T29

1

T19

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15093

1

T2

6

T9

19

T4

13

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1203	1			T2	1		T9	4		T25	1
key_invalid	sha2_none	920	1			T2	1		T3	1		T9	1
key_invalid	sha2_512	938	1			T3	1		T9	2		T8	1
key_invalid	sha2_384	934	1			T3	1		T9	2		T4	1
key_invalid	sha2_256	911	1			T3	1		T4	2		T10	3
key_none	sha2_invalid	582	1			T10	1		T8	1		T5	1
key_none	sha2_none	604	1			T9	1		T10	2		T18	1
key_none	sha2_512	2617	1			T2	1		T3	1		T9	1
key_none	sha2_384	2624	1			T3	1		T9	2		T4	2
key_none	sha2_256	1640	1			T4	1		T25	1		T18	1
key_1024	sha2_invalid	545	1			T3	1		T9	3		T10	1
key_1024	sha2_none	593	1			T3	1		T4	1		T25	1
key_1024	sha2_512	1769	1			T1	225		T3	2		T9	1
key_1024	sha2_384	989	1			T2	2		T3	1		T9	2
key_512	sha2_invalid	586	1			T3	1		T9	2		T23	1
key_512	sha2_none	608	1			T9	1		T29	1		T6	4
key_512	sha2_512	697	1			T3	1		T4	2		T5	2
key_512	sha2_384	1283	1			T2	1		T4	1		T18	1
key_512	sha2_256	870	1			T4	3		T5	1		T6	7
key_384	sha2_invalid	532	1			T2	1		T4	1		T18	1
key_384	sha2_none	552	1			T4	1		T23	1		T29	1
key_384	sha2_512	659	1			T9	1		T4	1		T18	1
key_384	sha2_384	626	1			T2	1		T9	1		T4	1
key_384	sha2_256	1135	1			T3	1		T4	1		T6	11
key_256	sha2_invalid	569	1			T3	1		T4	1		T29	1
key_256	sha2_none	655	1			T2	1		T3	1		T4	1
key_256	sha2_512	661	1			T3	1		T4	1		T10	1
key_256	sha2_384	623	1			T3	1		T9	1		T4	1
key_256	sha2_256	804	1			T2	1		T3	1		T4	1
key_128	sha2_invalid	571	1			T9	2		T4	1		T29	1
key_128	sha2_none	579	1			T3	2		T9	1		T4	1
key_128	sha2_512	681	1			T2	1		T3	1		T9	1
key_128	sha2_384	652	1			T9	1		T5	1		T6	6
key_128	sha2_256	666	1			T2	1		T3	1		T5	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

641

1

T3

2

T10

2

T5

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1203	1			T2	1		T9	4		T25	1
key_invalid	sha2_none	920	1			T2	1		T3	1		T9	1
key_invalid	sha2_512	938	1			T3	1		T9	2		T8	1
key_invalid	sha2_384	934	1			T3	1		T9	2		T4	1
key_invalid	sha2_256	911	1			T3	1		T4	2		T10	3
key_none	sha2_invalid	582	1			T10	1		T8	1		T5	1
key_none	sha2_none	604	1			T9	1		T10	2		T18	1
key_none	sha2_512	2617	1			T2	1		T3	1		T9	1
key_none	sha2_384	2624	1			T3	1		T9	2		T4	2
key_none	sha2_256	1640	1			T4	1		T25	1		T18	1
key_1024	sha2_invalid	545	1			T3	1		T9	3		T10	1
key_1024	sha2_none	593	1			T3	1		T4	1		T25	1
key_1024	sha2_512	1769	1			T1	225		T3	2		T9	1
key_1024	sha2_384	989	1			T2	2		T3	1		T9	2
key_1024	sha2_256	641	1			T3	2		T10	2		T5	2
key_512	sha2_invalid	586	1			T3	1		T9	2		T23	1
key_512	sha2_none	608	1			T9	1		T29	1		T6	4
key_512	sha2_512	697	1			T3	1		T4	2		T5	2
key_512	sha2_384	1283	1			T2	1		T4	1		T18	1
key_512	sha2_256	870	1			T4	3		T5	1		T6	7
key_384	sha2_invalid	532	1			T2	1		T4	1		T18	1
key_384	sha2_none	552	1			T4	1		T23	1		T29	1
key_384	sha2_512	659	1			T9	1		T4	1		T18	1
key_384	sha2_384	626	1			T2	1		T9	1		T4	1
key_384	sha2_256	1135	1			T3	1		T4	1		T6	11
key_256	sha2_invalid	569	1			T3	1		T4	1		T29	1
key_256	sha2_none	655	1			T2	1		T3	1		T4	1
key_256	sha2_512	661	1			T3	1		T4	1		T10	1
key_256	sha2_384	623	1			T3	1		T9	1		T4	1
key_256	sha2_256	804	1			T2	1		T3	1		T4	1
key_128	sha2_invalid	571	1			T9	2		T4	1		T29	1
key_128	sha2_none	579	1			T3	2		T9	1		T4	1
key_128	sha2_512	681	1			T2	1		T3	1		T9	1
key_128	sha2_384	652	1			T9	1		T5	1		T6	6
key_128	sha2_256	666	1			T2	1		T3	1		T5	1