Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 658
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T99 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4041399119 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:46 PM PDT 24 35726934 ps
T69 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.478131844 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 91555422 ps
T533 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1464147876 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 193648408 ps
T112 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4025839804 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 418919069 ps
T534 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2601103324 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:40 PM PDT 24 13138081 ps
T535 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4142155711 Jul 23 06:19:32 PM PDT 24 Jul 23 06:19:44 PM PDT 24 81036246 ps
T100 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2290095500 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:33 PM PDT 24 294253067 ps
T70 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.145114149 Jul 23 06:19:36 PM PDT 24 Jul 23 06:19:52 PM PDT 24 515410488 ps
T536 /workspace/coverage/cover_reg_top/40.hmac_intr_test.367328534 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:46 PM PDT 24 41270750 ps
T537 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1331667814 Jul 23 06:19:37 PM PDT 24 Jul 23 06:32:47 PM PDT 24 291216854704 ps
T113 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3075097878 Jul 23 06:19:25 PM PDT 24 Jul 23 06:19:28 PM PDT 24 46498887 ps
T538 /workspace/coverage/cover_reg_top/5.hmac_intr_test.595515850 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:30 PM PDT 24 18875577 ps
T539 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4164022648 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:52 PM PDT 24 209112682 ps
T540 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.702908134 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:36 PM PDT 24 39318718 ps
T101 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2377701236 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:31 PM PDT 24 67187358 ps
T541 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.537207333 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:45 PM PDT 24 2944914027 ps
T542 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1853647307 Jul 23 06:19:35 PM PDT 24 Jul 23 06:19:48 PM PDT 24 27835476 ps
T543 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.989120196 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:36 PM PDT 24 264440201 ps
T544 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.831566670 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:53 PM PDT 24 86258827 ps
T545 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.758808617 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:33 PM PDT 24 2315550173 ps
T114 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3404781336 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:32 PM PDT 24 40235187 ps
T546 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.910967617 Jul 23 06:19:19 PM PDT 24 Jul 23 06:19:23 PM PDT 24 208135738 ps
T547 /workspace/coverage/cover_reg_top/15.hmac_intr_test.797305248 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:42 PM PDT 24 17605597 ps
T548 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3601601663 Jul 23 06:19:36 PM PDT 24 Jul 23 06:19:50 PM PDT 24 21135073 ps
T549 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3137412166 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:46 PM PDT 24 46319500 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.957314875 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 22315588 ps
T550 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3421749394 Jul 23 06:19:33 PM PDT 24 Jul 23 06:19:45 PM PDT 24 45646229 ps
T126 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3934941270 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:54 PM PDT 24 250193467 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1108403914 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:36 PM PDT 24 18902453 ps
T551 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.598968109 Jul 23 06:19:25 PM PDT 24 Jul 23 06:19:30 PM PDT 24 139175534 ps
T115 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3035943976 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:43 PM PDT 24 21897470 ps
T552 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2835782541 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:39 PM PDT 24 184776724 ps
T125 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.434528690 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:40 PM PDT 24 988587167 ps
T553 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1196295045 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:39 PM PDT 24 154598558 ps
T131 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1807955355 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:43 PM PDT 24 273041187 ps
T554 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1593434224 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:40 PM PDT 24 79884792 ps
T116 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2205547828 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:52 PM PDT 24 81438835 ps
T117 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2601915786 Jul 23 06:19:23 PM PDT 24 Jul 23 06:19:25 PM PDT 24 36977283 ps
T555 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3519025762 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:33 PM PDT 24 39955937 ps
T104 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.56299484 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 444853743 ps
T556 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1673983447 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 24422906 ps
T557 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.196878734 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 574043391 ps
T558 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1710356653 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:39 PM PDT 24 11374959 ps
T559 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2590506747 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 160283499 ps
T118 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3461295187 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:43 PM PDT 24 76508644 ps
T560 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2421275955 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:31 PM PDT 24 44152877 ps
T561 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3877182174 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:29 PM PDT 24 15744504 ps
T562 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3771691441 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:35 PM PDT 24 64321867 ps
T563 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2470167449 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:48 PM PDT 24 243359494 ps
T127 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.423784823 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:40 PM PDT 24 188764950 ps
T564 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3610787410 Jul 23 06:19:22 PM PDT 24 Jul 23 06:19:26 PM PDT 24 258647092 ps
T565 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3518342943 Jul 23 06:19:33 PM PDT 24 Jul 23 06:19:45 PM PDT 24 33028255 ps
T105 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2228005906 Jul 23 06:19:24 PM PDT 24 Jul 23 06:19:27 PM PDT 24 47049175 ps
T566 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2509385255 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:32 PM PDT 24 40488380 ps
T567 /workspace/coverage/cover_reg_top/0.hmac_intr_test.976854897 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:30 PM PDT 24 56520297 ps
T132 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.174864659 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:35 PM PDT 24 158982380 ps
T568 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2268759313 Jul 23 06:19:32 PM PDT 24 Jul 23 06:19:44 PM PDT 24 27533565 ps
T106 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1413319084 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:50 PM PDT 24 1639313788 ps
T569 /workspace/coverage/cover_reg_top/31.hmac_intr_test.724988393 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 12115180 ps
T570 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2115197653 Jul 23 06:19:35 PM PDT 24 Jul 23 06:19:48 PM PDT 24 20037919 ps
T129 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3163272213 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:40 PM PDT 24 183261443 ps
T130 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2748573016 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:42 PM PDT 24 280652796 ps
T571 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2467788725 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:51 PM PDT 24 12046012 ps
T572 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1915594919 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:38 PM PDT 24 187919109 ps
T573 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4071799630 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:38 PM PDT 24 344036893 ps
T574 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.620185957 Jul 23 06:19:25 PM PDT 24 Jul 23 06:19:30 PM PDT 24 28580376 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1178766401 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:38 PM PDT 24 538978177 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2814713734 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:51 PM PDT 24 163464829 ps
T576 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1836288786 Jul 23 06:19:35 PM PDT 24 Jul 23 06:19:48 PM PDT 24 75293833 ps
T577 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.443673020 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:36 PM PDT 24 573378207 ps
T578 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1014466105 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 26922300 ps
T579 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4030574489 Jul 23 06:19:32 PM PDT 24 Jul 23 06:19:44 PM PDT 24 108216517 ps
T580 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2950208102 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:33 PM PDT 24 12151249 ps
T581 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.182186915 Jul 23 06:19:33 PM PDT 24 Jul 23 06:19:46 PM PDT 24 448404581 ps
T582 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2768185546 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:34 PM PDT 24 92301009 ps
T583 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1879342603 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 218154650 ps
T584 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2483096781 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:35 PM PDT 24 284890385 ps
T108 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3785926271 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:47 PM PDT 24 2011737632 ps
T585 /workspace/coverage/cover_reg_top/10.hmac_intr_test.815374459 Jul 23 06:19:35 PM PDT 24 Jul 23 06:19:47 PM PDT 24 34965674 ps
T586 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2591077573 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 282518722 ps
T587 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3555464272 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:44 PM PDT 24 86374544 ps
T588 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2524134904 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:43 PM PDT 24 100184939 ps
T589 /workspace/coverage/cover_reg_top/35.hmac_intr_test.55186294 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 27475979 ps
T590 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1548082406 Jul 23 06:19:41 PM PDT 24 Jul 23 06:19:53 PM PDT 24 26155393 ps
T591 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1877849234 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:31 PM PDT 24 78256638 ps
T592 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1733526990 Jul 23 06:19:24 PM PDT 24 Jul 23 06:19:26 PM PDT 24 19060149 ps
T593 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2293223594 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:42 PM PDT 24 182993688 ps
T594 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4229746692 Jul 23 06:19:25 PM PDT 24 Jul 23 06:19:29 PM PDT 24 759911380 ps
T595 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2566331412 Jul 23 06:19:25 PM PDT 24 Jul 23 06:19:29 PM PDT 24 47423712 ps
T596 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1214394872 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:33 PM PDT 24 78044037 ps
T597 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2881092912 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:51 PM PDT 24 19450019 ps
T598 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1559837703 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:40 PM PDT 24 634183879 ps
T128 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.272285610 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:42 PM PDT 24 503126819 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3411670940 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:36 PM PDT 24 452172481 ps
T600 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3885940435 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:43 PM PDT 24 1022623346 ps
T601 /workspace/coverage/cover_reg_top/11.hmac_intr_test.886952458 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:31 PM PDT 24 14715419 ps
T109 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3336318575 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:36 PM PDT 24 278215334 ps
T110 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.860746213 Jul 23 06:19:35 PM PDT 24 Jul 23 06:19:48 PM PDT 24 12293574 ps
T602 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4023969789 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:44 PM PDT 24 358946958 ps
T603 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2141606447 Jul 23 06:19:32 PM PDT 24 Jul 23 06:19:45 PM PDT 24 85410607 ps
T604 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4049841774 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:41 PM PDT 24 426267268 ps
T605 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2706724313 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:42 PM PDT 24 12783775 ps
T606 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2617420241 Jul 23 06:19:40 PM PDT 24 Jul 23 06:19:53 PM PDT 24 151390731 ps
T607 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3151159279 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:36 PM PDT 24 282714461 ps
T608 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3959730548 Jul 23 06:19:23 PM PDT 24 Jul 23 06:19:32 PM PDT 24 2478881569 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2767586541 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:43 PM PDT 24 113339494 ps
T133 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1837458881 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:45 PM PDT 24 237574046 ps
T610 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4105689831 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:43 PM PDT 24 235757057 ps
T611 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1286094332 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:35 PM PDT 24 420262140 ps
T612 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3066299591 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:43 PM PDT 24 132716272 ps
T613 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2648478516 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 125888614 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3002691079 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:41 PM PDT 24 330418209 ps
T615 /workspace/coverage/cover_reg_top/9.hmac_intr_test.790256167 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 17639353 ps
T616 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3173392429 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:46 PM PDT 24 35944821 ps
T617 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2975519086 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:37 PM PDT 24 16445333 ps
T618 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4182161563 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:37 PM PDT 24 39785964 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1470797108 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:36 PM PDT 24 49372952 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.129402839 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 34980412 ps
T621 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4165827284 Jul 23 06:19:24 PM PDT 24 Jul 23 06:19:28 PM PDT 24 49048915 ps
T622 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4074202922 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:34 PM PDT 24 60451811 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3674626356 Jul 23 06:19:33 PM PDT 24 Jul 23 06:19:44 PM PDT 24 47741807 ps
T624 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3970708201 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:37 PM PDT 24 51762870 ps
T625 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1146056493 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:34 PM PDT 24 610803979 ps
T626 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2680350687 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 41686117 ps
T627 /workspace/coverage/cover_reg_top/25.hmac_intr_test.51954834 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:47 PM PDT 24 13083599 ps
T628 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3588246320 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:51 PM PDT 24 22337221 ps
T629 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2965962259 Jul 23 06:19:36 PM PDT 24 Jul 23 06:19:51 PM PDT 24 211020270 ps
T630 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1102004996 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:39 PM PDT 24 101994785 ps
T631 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3551293001 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:40 PM PDT 24 488087985 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_intr_test.136725474 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:39 PM PDT 24 60732474 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1984656717 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:33 PM PDT 24 47461067 ps
T634 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3841358154 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:42 PM PDT 24 713168470 ps
T71 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2449082640 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:54 PM PDT 24 129148570 ps
T635 /workspace/coverage/cover_reg_top/42.hmac_intr_test.167408628 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:51 PM PDT 24 12246692 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1815482851 Jul 23 06:19:30 PM PDT 24 Jul 23 06:19:40 PM PDT 24 41567523 ps
T637 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.855479649 Jul 23 06:19:24 PM PDT 24 Jul 23 06:19:26 PM PDT 24 21030700 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2377845660 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:34 PM PDT 24 781918499 ps
T639 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4270411071 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:33 PM PDT 24 292342417 ps
T640 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2699359843 Jul 23 06:19:37 PM PDT 24 Jul 23 06:19:50 PM PDT 24 16463716 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2240950853 Jul 23 06:19:31 PM PDT 24 Jul 23 06:19:42 PM PDT 24 54936059 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2444366771 Jul 23 06:19:23 PM PDT 24 Jul 23 06:19:30 PM PDT 24 2584444734 ps
T643 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1170516404 Jul 23 06:19:36 PM PDT 24 Jul 23 06:19:49 PM PDT 24 12177619 ps
T644 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4132053699 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:35 PM PDT 24 35831995 ps
T645 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2676958329 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:36 PM PDT 24 55602220 ps
T646 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3981187598 Jul 23 06:19:36 PM PDT 24 Jul 23 06:19:49 PM PDT 24 15922374 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4263006016 Jul 23 06:19:23 PM PDT 24 Jul 23 06:19:26 PM PDT 24 284048614 ps
T648 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3404326653 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:37 PM PDT 24 56999999 ps
T649 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1763305478 Jul 23 06:19:26 PM PDT 24 Jul 23 06:19:46 PM PDT 24 5113861720 ps
T650 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.282727269 Jul 23 06:19:34 PM PDT 24 Jul 23 06:19:48 PM PDT 24 452230679 ps
T651 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1417563389 Jul 23 06:19:38 PM PDT 24 Jul 23 06:19:51 PM PDT 24 22580012 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2746481741 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:40 PM PDT 24 50629725 ps
T653 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3297446784 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:34 PM PDT 24 40764927 ps
T654 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2147135330 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:34 PM PDT 24 16647983 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2034267279 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:31 PM PDT 24 24015247 ps
T656 /workspace/coverage/cover_reg_top/27.hmac_intr_test.898876522 Jul 23 06:19:28 PM PDT 24 Jul 23 06:19:36 PM PDT 24 13400738 ps
T657 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2547571501 Jul 23 06:19:42 PM PDT 24 Jul 23 06:19:53 PM PDT 24 32334921 ps
T124 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3435823587 Jul 23 06:19:27 PM PDT 24 Jul 23 06:19:35 PM PDT 24 86354286 ps
T658 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3093724530 Jul 23 06:19:29 PM PDT 24 Jul 23 06:19:38 PM PDT 24 408355427 ps

Test location /workspace/coverage/default/43.hmac_long_msg.3422513883
Short name T4
Test name
Test status
Simulation time 16943609624 ps
CPU time 150.82 seconds
Started Jul 23 06:22:08 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 199752 kb
Host smart-4a48cf0d-69a8-40da-a493-97a654bea128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422513883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3422513883
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3522795883
Short name T6
Test name
Test status
Simulation time 300782907947 ps
CPU time 2264 seconds
Started Jul 23 06:21:52 PM PDT 24
Finished Jul 23 06:59:38 PM PDT 24
Peak memory 774184 kb
Host smart-2ebb5708-27c9-46bc-95cc-34e5b367bd37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522795883 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3522795883
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1072227463
Short name T16
Test name
Test status
Simulation time 424110734821 ps
CPU time 1315.8 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:42:16 PM PDT 24
Peak memory 216196 kb
Host smart-bb6ac359-980e-4322-be01-aa8f2a9a7e5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072227463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1072227463
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2610887393
Short name T27
Test name
Test status
Simulation time 10047891496 ps
CPU time 1118.44 seconds
Started Jul 23 06:20:44 PM PDT 24
Finished Jul 23 06:39:24 PM PDT 24
Peak memory 683812 kb
Host smart-dcc00081-5c01-4f5f-b1f7-14caf1a753d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610887393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2610887393
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.145114149
Short name T70
Test name
Test status
Simulation time 515410488 ps
CPU time 4.45 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:52 PM PDT 24
Peak memory 199840 kb
Host smart-6b167fc9-fef4-44e9-98da-59674320d513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145114149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.145114149
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/43.hmac_alert_test.124261887
Short name T24
Test name
Test status
Simulation time 210968905 ps
CPU time 0.64 seconds
Started Jul 23 06:22:08 PM PDT 24
Finished Jul 23 06:22:23 PM PDT 24
Peak memory 196416 kb
Host smart-4a49e9b4-8eb9-4b93-be33-5ead40a8b390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124261887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.124261887
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3580553486
Short name T21
Test name
Test status
Simulation time 62668312746 ps
CPU time 1419.57 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 534432 kb
Host smart-b5430a56-58ff-465c-b9fd-e3dadeb620c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580553486 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3580553486
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2228005906
Short name T105
Test name
Test status
Simulation time 47049175 ps
CPU time 0.82 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:27 PM PDT 24
Peak memory 199188 kb
Host smart-66873780-f6df-4d59-88bb-fa17696180ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228005906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2228005906
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3806669772
Short name T35
Test name
Test status
Simulation time 67390748717 ps
CPU time 1890.31 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:52:11 PM PDT 24
Peak memory 757568 kb
Host smart-bdfd9287-b554-45c0-997a-47ae0b4142d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806669772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3806669772
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3441432798
Short name T57
Test name
Test status
Simulation time 404835628 ps
CPU time 1.01 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 219344 kb
Host smart-22c954dd-d119-4d26-82df-01739a84ac98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441432798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3441432798
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2679588813
Short name T13
Test name
Test status
Simulation time 10676288949 ps
CPU time 92.94 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:22:05 PM PDT 24
Peak memory 199784 kb
Host smart-55567fb3-6631-45b1-acde-9fcb473cabef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679588813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2679588813
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2527610695
Short name T63
Test name
Test status
Simulation time 120075724719 ps
CPU time 3638.14 seconds
Started Jul 23 06:20:18 PM PDT 24
Finished Jul 23 07:20:58 PM PDT 24
Peak memory 801452 kb
Host smart-293bcc00-7e3a-4e4b-8b56-9df415f6558a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527610695 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2527610695
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1837458881
Short name T133
Test name
Test status
Simulation time 237574046 ps
CPU time 3.97 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:45 PM PDT 24
Peak memory 199856 kb
Host smart-f7086a2d-4e55-4769-a414-69535b6cd8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837458881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1837458881
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2601915786
Short name T117
Test name
Test status
Simulation time 36977283 ps
CPU time 0.68 seconds
Started Jul 23 06:19:23 PM PDT 24
Finished Jul 23 06:19:25 PM PDT 24
Peak memory 197796 kb
Host smart-1adedb48-0b3c-4032-9a18-5e631c7eb924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601915786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2601915786
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3256539273
Short name T3
Test name
Test status
Simulation time 11836592215 ps
CPU time 590.05 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 718188 kb
Host smart-7e6c8db4-5cbb-40f9-ad3e-ca976b22b678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256539273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3256539273
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1350315528
Short name T44
Test name
Test status
Simulation time 23499260538 ps
CPU time 3277.72 seconds
Started Jul 23 06:21:03 PM PDT 24
Finished Jul 23 07:15:41 PM PDT 24
Peak memory 788596 kb
Host smart-7b526ab0-507e-4a85-b682-dfa5ffe9d111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350315528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1350315528
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.87148413
Short name T68
Test name
Test status
Simulation time 158775363 ps
CPU time 1.78 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:28 PM PDT 24
Peak memory 199872 kb
Host smart-702e7b03-9e25-4213-9e4b-73856203aeb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87148413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.87148413
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2092806276
Short name T148
Test name
Test status
Simulation time 441400637100 ps
CPU time 2238.43 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:57:05 PM PDT 24
Peak memory 207912 kb
Host smart-1a9d18d8-f139-43ff-ac53-9ba4ae272729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2092806276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2092806276
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2449082640
Short name T71
Test name
Test status
Simulation time 129148570 ps
CPU time 3.84 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:54 PM PDT 24
Peak memory 199880 kb
Host smart-8840f4ba-ce1e-4399-9e73-3fb3f1386575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449082640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2449082640
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3411670940
Short name T599
Test name
Test status
Simulation time 452172481 ps
CPU time 3.56 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199816 kb
Host smart-efb2c077-e26e-45d6-bfe2-767de4d0d4fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411670940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3411670940
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3524008275
Short name T532
Test name
Test status
Simulation time 6524399096 ps
CPU time 16.32 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199992 kb
Host smart-ed4a262d-8abe-49d4-af4c-a1fa927b9181
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524008275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3524008275
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1984656717
Short name T633
Test name
Test status
Simulation time 47461067 ps
CPU time 0.73 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 197732 kb
Host smart-7b267aa7-ed98-42ca-bb74-1ebd6383860a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984656717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1984656717
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2524134904
Short name T588
Test name
Test status
Simulation time 100184939 ps
CPU time 3.27 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 215384 kb
Host smart-7027a3ac-1ee6-451b-b2c6-c42c80e4bd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524134904 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2524134904
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.976854897
Short name T567
Test name
Test status
Simulation time 56520297 ps
CPU time 0.63 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 194892 kb
Host smart-f6e2fae4-cab2-4e27-b1b3-7762d1ff5565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976854897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.976854897
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1877849234
Short name T591
Test name
Test status
Simulation time 78256638 ps
CPU time 1.66 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 199908 kb
Host smart-0ddc07e9-b8f2-4c4f-a90e-494d68ca2163
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877849234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1877849234
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.989120196
Short name T543
Test name
Test status
Simulation time 264440201 ps
CPU time 2.97 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199828 kb
Host smart-312b3a01-4998-4a0b-b370-f0ba9d6676ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989120196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.989120196
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1312805074
Short name T529
Test name
Test status
Simulation time 436935969 ps
CPU time 5.39 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 199632 kb
Host smart-7a5d8e3d-5e01-4643-bf63-922dc138a010
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312805074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1312805074
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.537207333
Short name T541
Test name
Test status
Simulation time 2944914027 ps
CPU time 15.74 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:45 PM PDT 24
Peak memory 199864 kb
Host smart-93a874d5-c66e-4ad2-a584-c508a7be62e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537207333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.537207333
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1214394872
Short name T596
Test name
Test status
Simulation time 78044037 ps
CPU time 0.98 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 199704 kb
Host smart-4db8c0ec-a738-4269-8f72-7ba2faaa467b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214394872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1214394872
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1763305478
Short name T649
Test name
Test status
Simulation time 5113861720 ps
CPU time 16.77 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 215324 kb
Host smart-646d2286-d18b-4cf1-8cec-1d62f056d2be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763305478 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1763305478
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2814713734
Short name T107
Test name
Test status
Simulation time 163464829 ps
CPU time 0.8 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 199704 kb
Host smart-08a8212a-368f-4871-a822-b07a40653709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814713734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2814713734
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2601103324
Short name T534
Test name
Test status
Simulation time 13138081 ps
CPU time 0.59 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 194788 kb
Host smart-9ff804d6-44ce-4873-8ff0-95c35715e988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601103324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2601103324
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3035943976
Short name T115
Test name
Test status
Simulation time 21897470 ps
CPU time 1.09 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 198412 kb
Host smart-48ed5953-b25b-4e94-bf7a-d42ca04d358d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035943976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3035943976
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4071799630
Short name T573
Test name
Test status
Simulation time 344036893 ps
CPU time 3.77 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199864 kb
Host smart-4298ff10-ab0b-4203-9c01-78eb5fc9c8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071799630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4071799630
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2470167449
Short name T563
Test name
Test status
Simulation time 243359494 ps
CPU time 1.8 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 199728 kb
Host smart-ac474999-8572-4c57-8c95-7a9d74caddad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470167449 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2470167449
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4041399119
Short name T99
Test name
Test status
Simulation time 35726934 ps
CPU time 0.71 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 197924 kb
Host smart-3fbd0c41-b191-4725-a0a7-ed6f5d178e19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041399119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4041399119
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.815374459
Short name T585
Test name
Test status
Simulation time 34965674 ps
CPU time 0.57 seconds
Started Jul 23 06:19:35 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 194748 kb
Host smart-14323592-cff0-477a-bbc8-02d75c30be72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815374459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.815374459
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4025839804
Short name T112
Test name
Test status
Simulation time 418919069 ps
CPU time 1.83 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 199852 kb
Host smart-21164e5e-7793-4058-bd7d-c140f572f683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025839804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4025839804
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1836288786
Short name T576
Test name
Test status
Simulation time 75293833 ps
CPU time 1.86 seconds
Started Jul 23 06:19:35 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 199868 kb
Host smart-22f6a17d-378e-4930-af46-b704fc5a1a19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836288786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1836288786
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4105689831
Short name T610
Test name
Test status
Simulation time 235757057 ps
CPU time 4.18 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 199908 kb
Host smart-3f6c6cc1-3837-46e4-8826-3ed3f2ccdeb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105689831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4105689831
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3196102734
Short name T530
Test name
Test status
Simulation time 137573758 ps
CPU time 1.73 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:41 PM PDT 24
Peak memory 200000 kb
Host smart-5b6952b5-22f3-48f7-8d34-95341d199c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196102734 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3196102734
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.56299484
Short name T104
Test name
Test status
Simulation time 444853743 ps
CPU time 0.84 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199404 kb
Host smart-19d934cc-f0fe-466e-a149-f1411c5d3069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56299484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.56299484
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.886952458
Short name T601
Test name
Test status
Simulation time 14715419 ps
CPU time 0.61 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 194808 kb
Host smart-6ecc03c1-9734-470f-bb29-bd5e2795bfcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886952458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.886952458
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1146056493
Short name T625
Test name
Test status
Simulation time 610803979 ps
CPU time 2.25 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 199900 kb
Host smart-44b8bffc-f124-4872-a8ef-8b12e80cd985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146056493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1146056493
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2483096781
Short name T584
Test name
Test status
Simulation time 284890385 ps
CPU time 2.73 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 199772 kb
Host smart-330c72ae-b1f1-4d22-b879-90aea006d838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483096781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2483096781
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2748573016
Short name T130
Test name
Test status
Simulation time 280652796 ps
CPU time 4.34 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 199900 kb
Host smart-2cd0c877-9669-416f-a3a6-f604b2f37fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748573016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2748573016
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1331667814
Short name T537
Test name
Test status
Simulation time 291216854704 ps
CPU time 776.86 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:32:47 PM PDT 24
Peak memory 224560 kb
Host smart-3922137b-9213-4286-92b7-d21c6e4f502e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331667814 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1331667814
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2290095500
Short name T100
Test name
Test status
Simulation time 294253067 ps
CPU time 0.95 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 199680 kb
Host smart-9d9442f9-739b-4991-b32f-c0b06057128b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290095500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2290095500
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3877182174
Short name T561
Test name
Test status
Simulation time 15744504 ps
CPU time 0.58 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:29 PM PDT 24
Peak memory 194760 kb
Host smart-baf9798d-f64e-4913-8cd2-c0f41151ad6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877182174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3877182174
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3404781336
Short name T114
Test name
Test status
Simulation time 40235187 ps
CPU time 1.95 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:32 PM PDT 24
Peak memory 199888 kb
Host smart-b59c5437-c1c4-4857-9c4d-0e6eb498a2cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404781336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3404781336
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2746481741
Short name T652
Test name
Test status
Simulation time 50629725 ps
CPU time 2.58 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 199900 kb
Host smart-51932683-7cb8-42ea-94e1-f2fcf9757527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746481741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2746481741
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2768185546
Short name T582
Test name
Test status
Simulation time 92301009 ps
CPU time 1.74 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 199896 kb
Host smart-d428d4be-9a97-40ce-be66-646d39e32802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768185546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2768185546
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2268759313
Short name T568
Test name
Test status
Simulation time 27533565 ps
CPU time 1.58 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199916 kb
Host smart-dda720e8-d49b-42b4-8a3f-42e402157096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268759313 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2268759313
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4132053699
Short name T644
Test name
Test status
Simulation time 35831995 ps
CPU time 0.6 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 194840 kb
Host smart-03198e87-bf33-4e22-861b-b6ddb757c726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132053699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4132053699
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2766175106
Short name T111
Test name
Test status
Simulation time 23072876 ps
CPU time 1.02 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199708 kb
Host smart-febc591f-3103-48e7-85f7-57e027728753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766175106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2766175106
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.598968109
Short name T551
Test name
Test status
Simulation time 139175534 ps
CPU time 2.81 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 199840 kb
Host smart-fe561708-367c-40e8-acef-453b2f7577eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598968109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.598968109
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3934941270
Short name T126
Test name
Test status
Simulation time 250193467 ps
CPU time 4 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:54 PM PDT 24
Peak memory 199872 kb
Host smart-5fbace42-9a39-4839-8b1f-ef41a41386d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934941270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3934941270
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1464147876
Short name T533
Test name
Test status
Simulation time 193648408 ps
CPU time 2.53 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199968 kb
Host smart-e991cd00-ce32-4d75-a5b0-cb299c4f7afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464147876 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1464147876
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2975519086
Short name T617
Test name
Test status
Simulation time 16445333 ps
CPU time 0.84 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:37 PM PDT 24
Peak memory 199428 kb
Host smart-182df268-d045-45b5-be19-fea34b3cd384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975519086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2975519086
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1733526990
Short name T592
Test name
Test status
Simulation time 19060149 ps
CPU time 0.63 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 194776 kb
Host smart-fb344e1c-1f82-4f34-8102-467357aa0335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733526990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1733526990
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1559837703
Short name T598
Test name
Test status
Simulation time 634183879 ps
CPU time 1.09 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 198436 kb
Host smart-5d7a9ae3-e1ea-4242-a689-653732da1097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559837703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1559837703
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2835782541
Short name T552
Test name
Test status
Simulation time 184776724 ps
CPU time 3.77 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:39 PM PDT 24
Peak memory 199844 kb
Host smart-0865a1a4-706b-4f6c-ac44-8f525db43039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835782541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2835782541
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.272285610
Short name T128
Test name
Test status
Simulation time 503126819 ps
CPU time 4.35 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 200060 kb
Host smart-16f70408-c872-4f06-8590-f17628680da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272285610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.272285610
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3551293001
Short name T631
Test name
Test status
Simulation time 488087985 ps
CPU time 2.74 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 208144 kb
Host smart-1dea9c7e-5ce6-4bc3-9759-a10189e8fd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551293001 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3551293001
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1815482851
Short name T636
Test name
Test status
Simulation time 41567523 ps
CPU time 0.81 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 199624 kb
Host smart-24e92b69-3160-4b41-bf82-2eea77bd70fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815482851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1815482851
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.797305248
Short name T547
Test name
Test status
Simulation time 17605597 ps
CPU time 0.6 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 194808 kb
Host smart-3128dc71-c764-4c82-a3d9-f087599424eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797305248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.797305248
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3461295187
Short name T118
Test name
Test status
Simulation time 76508644 ps
CPU time 1.16 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 198396 kb
Host smart-fc5f0d48-f3ee-4623-802e-dc98595bdafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461295187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3461295187
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.910967617
Short name T546
Test name
Test status
Simulation time 208135738 ps
CPU time 3.17 seconds
Started Jul 23 06:19:19 PM PDT 24
Finished Jul 23 06:19:23 PM PDT 24
Peak memory 199984 kb
Host smart-e990eb9a-513f-4d6f-99db-228d943ef32d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910967617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.910967617
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4023969789
Short name T602
Test name
Test status
Simulation time 358946958 ps
CPU time 2.31 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199924 kb
Host smart-01d2a626-7e9e-4bf6-bdac-65898b71a598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023969789 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4023969789
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3066299591
Short name T612
Test name
Test status
Simulation time 132716272 ps
CPU time 1 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 199664 kb
Host smart-eaba43e4-747c-4f02-bc2b-f38a12720ab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066299591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3066299591
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1710356653
Short name T558
Test name
Test status
Simulation time 11374959 ps
CPU time 0.57 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:39 PM PDT 24
Peak memory 194804 kb
Host smart-cc110a36-4f42-468d-8c10-af615dfe359d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710356653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1710356653
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3555464272
Short name T587
Test name
Test status
Simulation time 86374544 ps
CPU time 2.1 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199776 kb
Host smart-8fead95e-19f6-479b-9f9a-12711e84066c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555464272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3555464272
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4049841774
Short name T604
Test name
Test status
Simulation time 426267268 ps
CPU time 1.75 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:41 PM PDT 24
Peak memory 199888 kb
Host smart-61b4a6f4-9ce8-4113-97ab-b6ea785940c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049841774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4049841774
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.423784823
Short name T127
Test name
Test status
Simulation time 188764950 ps
CPU time 1.72 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 199928 kb
Host smart-d1d1e7b7-719f-4a50-bc1e-7f4a13c5dc40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423784823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.423784823
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.282727269
Short name T650
Test name
Test status
Simulation time 452230679 ps
CPU time 1.81 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 199908 kb
Host smart-7f7af705-0711-4e91-9c4f-28e8dd38ddf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282727269 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.282727269
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.860746213
Short name T110
Test name
Test status
Simulation time 12293574 ps
CPU time 0.68 seconds
Started Jul 23 06:19:35 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 198152 kb
Host smart-51154be0-f55f-4026-9bc9-423b49c132a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860746213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.860746213
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1593434224
Short name T554
Test name
Test status
Simulation time 79884792 ps
CPU time 0.56 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 194868 kb
Host smart-ab2cf37b-893f-4be4-8b88-7b0c9fadec88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593434224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1593434224
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2421275955
Short name T560
Test name
Test status
Simulation time 44152877 ps
CPU time 1.13 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 199876 kb
Host smart-37358fec-460b-4b65-b003-0ca5f6605132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421275955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2421275955
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4142155711
Short name T535
Test name
Test status
Simulation time 81036246 ps
CPU time 1.89 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199864 kb
Host smart-2910196b-9136-440e-91c7-42e58a793895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142155711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4142155711
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.196878734
Short name T557
Test name
Test status
Simulation time 574043391 ps
CPU time 1.82 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199860 kb
Host smart-79f94cd1-b0aa-4d4b-bdaa-9abaa0bb9599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196878734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.196878734
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.831566670
Short name T544
Test name
Test status
Simulation time 86258827 ps
CPU time 2.15 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:53 PM PDT 24
Peak memory 199976 kb
Host smart-517ee827-7442-484b-b00a-5a2fc94d7e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831566670 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.831566670
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.129402839
Short name T620
Test name
Test status
Simulation time 34980412 ps
CPU time 0.89 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 199700 kb
Host smart-6d70c356-303f-49fd-b4ad-2e58347c4d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129402839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.129402839
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1879342603
Short name T583
Test name
Test status
Simulation time 218154650 ps
CPU time 0.62 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 194828 kb
Host smart-c54abb4a-c069-46d0-8a66-19e839432be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879342603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1879342603
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2205547828
Short name T116
Test name
Test status
Simulation time 81438835 ps
CPU time 2.13 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:52 PM PDT 24
Peak memory 199836 kb
Host smart-60b3f6c4-501d-456e-903a-3ab46e2b4d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205547828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2205547828
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2590506747
Short name T559
Test name
Test status
Simulation time 160283499 ps
CPU time 1.75 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 199964 kb
Host smart-2d3f11f3-f4fe-4055-8263-154d2efc6193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590506747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2590506747
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1915594919
Short name T572
Test name
Test status
Simulation time 187919109 ps
CPU time 3.29 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199908 kb
Host smart-0ca23939-35cc-420f-91ac-2b00e38b444b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915594919 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1915594919
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2377701236
Short name T101
Test name
Test status
Simulation time 67187358 ps
CPU time 0.93 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 199728 kb
Host smart-720550f9-775d-4666-b9ce-d6b6420873ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377701236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2377701236
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3518342943
Short name T565
Test name
Test status
Simulation time 33028255 ps
CPU time 0.57 seconds
Started Jul 23 06:19:33 PM PDT 24
Finished Jul 23 06:19:45 PM PDT 24
Peak memory 194728 kb
Host smart-14cecb68-0749-4cfb-9994-075d0eb3b6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518342943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3518342943
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2141606447
Short name T603
Test name
Test status
Simulation time 85410607 ps
CPU time 2.04 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:45 PM PDT 24
Peak memory 199932 kb
Host smart-5731ad37-24e1-4cc0-9ea8-2cf2d1f309d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141606447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2141606447
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1286094332
Short name T611
Test name
Test status
Simulation time 420262140 ps
CPU time 3.63 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 199896 kb
Host smart-f0f40cf1-ccaa-4e14-a613-f1d60115ab3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286094332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1286094332
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2591077573
Short name T586
Test name
Test status
Simulation time 282518722 ps
CPU time 1.72 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 199908 kb
Host smart-247a6605-b17a-4286-a85a-c5f3c8b7cd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591077573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2591077573
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3885940435
Short name T600
Test name
Test status
Simulation time 1022623346 ps
CPU time 3.6 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 199848 kb
Host smart-29954948-f0fb-4bd1-ae9c-15debab9aa22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885940435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3885940435
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3785926271
Short name T108
Test name
Test status
Simulation time 2011737632 ps
CPU time 11.68 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 199904 kb
Host smart-d675c2a9-e0a0-40aa-b7a2-210087197728
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785926271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3785926271
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.702908134
Short name T540
Test name
Test status
Simulation time 39318718 ps
CPU time 0.96 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199724 kb
Host smart-8b341ad9-e71f-4739-afe3-ee9c98ff2f7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702908134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.702908134
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3093724530
Short name T658
Test name
Test status
Simulation time 408355427 ps
CPU time 1.1 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199708 kb
Host smart-9f6845b6-81e5-4bb6-ae79-2e8edb865a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093724530 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3093724530
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2240950853
Short name T641
Test name
Test status
Simulation time 54936059 ps
CPU time 0.7 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 198048 kb
Host smart-1b765d12-04ba-44f6-9d4b-fab196b176da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240950853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2240950853
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3674626356
Short name T623
Test name
Test status
Simulation time 47741807 ps
CPU time 0.62 seconds
Started Jul 23 06:19:33 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 194840 kb
Host smart-ebb471d1-b68a-4f41-a737-8c0ed6dbf16d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674626356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3674626356
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3002691079
Short name T614
Test name
Test status
Simulation time 330418209 ps
CPU time 2 seconds
Started Jul 23 06:19:30 PM PDT 24
Finished Jul 23 06:19:41 PM PDT 24
Peak memory 199884 kb
Host smart-3d120b13-773d-4093-9d68-d5a6bb7cde3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002691079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3002691079
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2377845660
Short name T638
Test name
Test status
Simulation time 781918499 ps
CPU time 3.54 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 199880 kb
Host smart-fcba07b4-bbe6-4b72-a5b6-6efaba0a6035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377845660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2377845660
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3163272213
Short name T129
Test name
Test status
Simulation time 183261443 ps
CPU time 3.02 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 199888 kb
Host smart-81947e22-ea97-45f9-b959-5f05cafaf620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163272213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3163272213
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2115197653
Short name T570
Test name
Test status
Simulation time 20037919 ps
CPU time 0.61 seconds
Started Jul 23 06:19:35 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 194864 kb
Host smart-fc5eda56-208a-409c-abf6-ac2b8ac18cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115197653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2115197653
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2547571501
Short name T657
Test name
Test status
Simulation time 32334921 ps
CPU time 0.58 seconds
Started Jul 23 06:19:42 PM PDT 24
Finished Jul 23 06:19:53 PM PDT 24
Peak memory 194800 kb
Host smart-367fe6d2-78c2-43ed-bb34-9b5a09640961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547571501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2547571501
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4182161563
Short name T618
Test name
Test status
Simulation time 39785964 ps
CPU time 0.59 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:37 PM PDT 24
Peak memory 194728 kb
Host smart-f4b1f327-e619-49b7-99b9-7a78dce86a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182161563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4182161563
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3519025762
Short name T555
Test name
Test status
Simulation time 39955937 ps
CPU time 0.62 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 194884 kb
Host smart-5a520b67-d1cb-4ca3-bac3-3579114c5522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519025762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3519025762
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2881092912
Short name T597
Test name
Test status
Simulation time 19450019 ps
CPU time 0.65 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 194816 kb
Host smart-8116b6d2-db15-49e9-91cd-63b6324a571b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881092912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2881092912
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.51954834
Short name T627
Test name
Test status
Simulation time 13083599 ps
CPU time 0.68 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 194816 kb
Host smart-69aa885e-2460-4498-91f2-54cfdf8c40ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51954834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.51954834
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2680350687
Short name T626
Test name
Test status
Simulation time 41686117 ps
CPU time 0.55 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 194844 kb
Host smart-09bc078a-a05f-4743-a4cb-bee2e648bb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680350687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2680350687
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.898876522
Short name T656
Test name
Test status
Simulation time 13400738 ps
CPU time 0.62 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 194720 kb
Host smart-6914085f-6864-488b-8a98-d60134129442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898876522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.898876522
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3981187598
Short name T646
Test name
Test status
Simulation time 15922374 ps
CPU time 0.59 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:49 PM PDT 24
Peak memory 194808 kb
Host smart-a5a46315-4768-48c6-8db5-eef911eb8997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981187598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3981187598
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1417563389
Short name T651
Test name
Test status
Simulation time 22580012 ps
CPU time 0.6 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 194828 kb
Host smart-facc836f-5983-4d61-82d2-d0dd05bc08ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417563389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1417563389
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3959730548
Short name T608
Test name
Test status
Simulation time 2478881569 ps
CPU time 8.18 seconds
Started Jul 23 06:19:23 PM PDT 24
Finished Jul 23 06:19:32 PM PDT 24
Peak memory 199912 kb
Host smart-1b982d4a-68e3-4365-bd68-1910e1902049
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959730548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3959730548
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1413319084
Short name T106
Test name
Test status
Simulation time 1639313788 ps
CPU time 17.37 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 199852 kb
Host smart-8a8d8a48-7e25-4b3a-ba02-b7d8035e0c69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413319084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1413319084
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.957314875
Short name T102
Test name
Test status
Simulation time 22315588 ps
CPU time 0.73 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 197656 kb
Host smart-47eff2e3-a19d-406e-aa6f-d3f8fa0c9400
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957314875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.957314875
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.620185957
Short name T574
Test name
Test status
Simulation time 28580376 ps
CPU time 1.81 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 199880 kb
Host smart-23010133-3235-4771-894f-f2a0657b40fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620185957 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.620185957
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3959142421
Short name T98
Test name
Test status
Simulation time 26227019 ps
CPU time 0.84 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:32 PM PDT 24
Peak memory 199444 kb
Host smart-52623a38-fcb3-43d6-8020-15a4658ebe0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959142421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3959142421
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2950208102
Short name T580
Test name
Test status
Simulation time 12151249 ps
CPU time 0.59 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 194720 kb
Host smart-71586529-0899-44e3-a4bc-7e0d8611266e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950208102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2950208102
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4263006016
Short name T647
Test name
Test status
Simulation time 284048614 ps
CPU time 2.41 seconds
Started Jul 23 06:19:23 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 199848 kb
Host smart-e89677ce-f6d9-4cc1-b176-40c150f4c48e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263006016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4263006016
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1196295045
Short name T553
Test name
Test status
Simulation time 154598558 ps
CPU time 1.69 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:39 PM PDT 24
Peak memory 199880 kb
Host smart-24c859dd-304c-4c9d-a2ee-8e38b437265f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196295045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1196295045
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.443673020
Short name T577
Test name
Test status
Simulation time 573378207 ps
CPU time 4.36 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199884 kb
Host smart-48d73e95-9d64-4a9c-bb7f-b71bb1f82dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443673020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.443673020
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3970708201
Short name T624
Test name
Test status
Simulation time 51762870 ps
CPU time 0.6 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:37 PM PDT 24
Peak memory 194780 kb
Host smart-acd2eba4-d4a2-48be-b006-2add0fe2809e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970708201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3970708201
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.724988393
Short name T569
Test name
Test status
Simulation time 12115180 ps
CPU time 0.57 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 194560 kb
Host smart-1c97d468-fe09-4c78-bd09-fc96f16d0b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724988393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.724988393
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1170516404
Short name T643
Test name
Test status
Simulation time 12177619 ps
CPU time 0.57 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:49 PM PDT 24
Peak memory 194752 kb
Host smart-d72e803f-6a3c-4967-be35-5bd9ca727dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170516404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1170516404
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2467788725
Short name T571
Test name
Test status
Simulation time 12046012 ps
CPU time 0.56 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 194840 kb
Host smart-794aa8cf-0518-48a4-b343-c138210c37eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467788725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2467788725
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1014466105
Short name T578
Test name
Test status
Simulation time 26922300 ps
CPU time 0.61 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 194928 kb
Host smart-00e81a8a-7e9a-408f-b430-e9684ac769be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014466105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1014466105
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.55186294
Short name T589
Test name
Test status
Simulation time 27475979 ps
CPU time 0.61 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:47 PM PDT 24
Peak memory 194800 kb
Host smart-332cfc37-3abc-45fd-9f27-de6a6a99aad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55186294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.55186294
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3173392429
Short name T616
Test name
Test status
Simulation time 35944821 ps
CPU time 0.59 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 194784 kb
Host smart-c022fb23-a399-4e93-b4c9-ffd219a1f3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173392429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3173392429
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2699359843
Short name T640
Test name
Test status
Simulation time 16463716 ps
CPU time 0.59 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 194832 kb
Host smart-b41948f1-c1c1-4216-b358-f8ddfcc8a571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699359843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2699359843
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2676958329
Short name T645
Test name
Test status
Simulation time 55602220 ps
CPU time 0.59 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 194708 kb
Host smart-ae5291e2-e933-45d3-90d7-251788480548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676958329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2676958329
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1853647307
Short name T542
Test name
Test status
Simulation time 27835476 ps
CPU time 0.58 seconds
Started Jul 23 06:19:35 PM PDT 24
Finished Jul 23 06:19:48 PM PDT 24
Peak memory 194912 kb
Host smart-97f5bba7-52c4-4bae-9bec-e53a575fd044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853647307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1853647307
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2444366771
Short name T642
Test name
Test status
Simulation time 2584444734 ps
CPU time 6.05 seconds
Started Jul 23 06:19:23 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 199928 kb
Host smart-018f16bd-ea83-480e-a06c-75d86b82e047
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444366771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2444366771
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1178766401
Short name T575
Test name
Test status
Simulation time 538978177 ps
CPU time 6.05 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199920 kb
Host smart-47ce99ac-0d66-41f3-abff-ee9d221e78ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178766401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1178766401
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3297446784
Short name T653
Test name
Test status
Simulation time 40764927 ps
CPU time 1 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 199492 kb
Host smart-dd0506a2-f200-4adb-9a9e-0488dd71cb30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297446784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3297446784
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4229746692
Short name T594
Test name
Test status
Simulation time 759911380 ps
CPU time 1.22 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:29 PM PDT 24
Peak memory 199732 kb
Host smart-6e60e468-ebb7-4680-a43c-927aaa92c689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229746692 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4229746692
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1108403914
Short name T103
Test name
Test status
Simulation time 18902453 ps
CPU time 0.96 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199412 kb
Host smart-1576faba-b9d4-414f-8415-4ff1fe75d764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108403914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1108403914
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2034267279
Short name T655
Test name
Test status
Simulation time 24015247 ps
CPU time 0.58 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:31 PM PDT 24
Peak memory 194836 kb
Host smart-088f3b93-c04f-4f35-966f-f4f2e6f0d574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034267279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2034267279
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4165827284
Short name T621
Test name
Test status
Simulation time 49048915 ps
CPU time 2.22 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:28 PM PDT 24
Peak memory 199940 kb
Host smart-6b95b410-592d-4b03-98f3-895845b0c8c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165827284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4165827284
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3610787410
Short name T564
Test name
Test status
Simulation time 258647092 ps
CPU time 3.48 seconds
Started Jul 23 06:19:22 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 199964 kb
Host smart-b47129e1-c47c-421f-b7fb-56f726866a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610787410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3610787410
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.478131844
Short name T69
Test name
Test status
Simulation time 91555422 ps
CPU time 2.82 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199816 kb
Host smart-a1c09f3e-22cd-4c12-9c16-e0cc92b53339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478131844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.478131844
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.367328534
Short name T536
Test name
Test status
Simulation time 41270750 ps
CPU time 0.59 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 194832 kb
Host smart-e52689b8-9f4e-43c6-a220-41f71c131e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367328534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.367328534
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3421749394
Short name T550
Test name
Test status
Simulation time 45646229 ps
CPU time 0.65 seconds
Started Jul 23 06:19:33 PM PDT 24
Finished Jul 23 06:19:45 PM PDT 24
Peak memory 194788 kb
Host smart-2417bd41-b672-4a91-895c-b02e9b88914f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421749394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3421749394
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.167408628
Short name T635
Test name
Test status
Simulation time 12246692 ps
CPU time 0.58 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 194828 kb
Host smart-1dfb30b2-3a4e-42fc-893d-4b7ab5923ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167408628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.167408628
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3137412166
Short name T549
Test name
Test status
Simulation time 46319500 ps
CPU time 0.6 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 194804 kb
Host smart-17b72618-bea1-4edc-8571-67722ba7e564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137412166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3137412166
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2147135330
Short name T654
Test name
Test status
Simulation time 16647983 ps
CPU time 0.57 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 194868 kb
Host smart-b95a8a64-fd82-4419-a0e7-1f715f7eeeb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147135330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2147135330
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3601601663
Short name T548
Test name
Test status
Simulation time 21135073 ps
CPU time 0.6 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 194796 kb
Host smart-e5d0ff0b-27bf-4f26-a17a-db23ebe97c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601601663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3601601663
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1548082406
Short name T590
Test name
Test status
Simulation time 26155393 ps
CPU time 0.63 seconds
Started Jul 23 06:19:41 PM PDT 24
Finished Jul 23 06:19:53 PM PDT 24
Peak memory 194860 kb
Host smart-2e3b65fa-979f-4158-b41c-0ce408d0f122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548082406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1548082406
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2617420241
Short name T606
Test name
Test status
Simulation time 151390731 ps
CPU time 0.6 seconds
Started Jul 23 06:19:40 PM PDT 24
Finished Jul 23 06:19:53 PM PDT 24
Peak memory 194752 kb
Host smart-14889b2a-cf2f-49c9-b5ec-4eb7fb07dd81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617420241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2617420241
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3588246320
Short name T628
Test name
Test status
Simulation time 22337221 ps
CPU time 0.59 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 194776 kb
Host smart-93b5d539-30e0-42fe-8bae-a9938b52a3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588246320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3588246320
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2790453354
Short name T531
Test name
Test status
Simulation time 32141091 ps
CPU time 0.64 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:49 PM PDT 24
Peak memory 194692 kb
Host smart-341661ac-41aa-4efa-9f36-11253fa54536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790453354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2790453354
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2566331412
Short name T595
Test name
Test status
Simulation time 47423712 ps
CPU time 1.3 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:29 PM PDT 24
Peak memory 199776 kb
Host smart-c5f369f0-e8e8-4f48-853d-036f3b3e2fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566331412 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2566331412
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.855479649
Short name T637
Test name
Test status
Simulation time 21030700 ps
CPU time 0.78 seconds
Started Jul 23 06:19:24 PM PDT 24
Finished Jul 23 06:19:26 PM PDT 24
Peak memory 198176 kb
Host smart-d3992f4c-69bf-44b8-bbd1-73d21ff3782d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855479649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.855479649
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.595515850
Short name T538
Test name
Test status
Simulation time 18875577 ps
CPU time 0.61 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:30 PM PDT 24
Peak memory 194732 kb
Host smart-83053be7-38e4-47d5-960c-5c022b4e928b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595515850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.595515850
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3075097878
Short name T113
Test name
Test status
Simulation time 46498887 ps
CPU time 1.18 seconds
Started Jul 23 06:19:25 PM PDT 24
Finished Jul 23 06:19:28 PM PDT 24
Peak memory 198492 kb
Host smart-27b2dbee-cd71-42c9-8e61-77dadc2a734d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075097878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3075097878
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.758808617
Short name T545
Test name
Test status
Simulation time 2315550173 ps
CPU time 3.87 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 199984 kb
Host smart-af6ada07-781a-4542-99f6-147d02bd4864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758808617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.758808617
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3435823587
Short name T124
Test name
Test status
Simulation time 86354286 ps
CPU time 1.88 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 199816 kb
Host smart-7269fbc9-1313-470d-b025-0ae4dc761959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435823587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3435823587
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4270411071
Short name T639
Test name
Test status
Simulation time 292342417 ps
CPU time 1.77 seconds
Started Jul 23 06:19:26 PM PDT 24
Finished Jul 23 06:19:33 PM PDT 24
Peak memory 199940 kb
Host smart-26d0f0f8-e626-48b5-83eb-4c6128f4bbd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270411071 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4270411071
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3771691441
Short name T562
Test name
Test status
Simulation time 64321867 ps
CPU time 0.71 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 197908 kb
Host smart-0678a159-ff3b-477b-8e89-18ed143fde47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771691441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3771691441
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4074202922
Short name T622
Test name
Test status
Simulation time 60451811 ps
CPU time 0.61 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:34 PM PDT 24
Peak memory 194772 kb
Host smart-07b9c5f1-f421-4351-b438-71260acda5e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074202922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4074202922
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2509385255
Short name T566
Test name
Test status
Simulation time 40488380 ps
CPU time 1.16 seconds
Started Jul 23 06:19:27 PM PDT 24
Finished Jul 23 06:19:32 PM PDT 24
Peak memory 199940 kb
Host smart-ef9dd3bf-5562-48aa-aa7f-5945a8c17c62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509385255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2509385255
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3151159279
Short name T607
Test name
Test status
Simulation time 282714461 ps
CPU time 1.77 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199776 kb
Host smart-598eba63-fe75-4f02-aae5-860bb82377e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151159279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3151159279
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1807955355
Short name T131
Test name
Test status
Simulation time 273041187 ps
CPU time 4.48 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 199908 kb
Host smart-b5ea9dce-d939-41b8-854a-3fcb7c2d53d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807955355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1807955355
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2293223594
Short name T593
Test name
Test status
Simulation time 182993688 ps
CPU time 3.21 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 208092 kb
Host smart-42a41d87-4c46-4ca2-bb2d-f86c21710403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293223594 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2293223594
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2648478516
Short name T613
Test name
Test status
Simulation time 125888614 ps
CPU time 0.97 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 199308 kb
Host smart-b25b2246-12cd-45a6-984e-114a9a9b5911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648478516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2648478516
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2706724313
Short name T605
Test name
Test status
Simulation time 12783775 ps
CPU time 0.64 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 194772 kb
Host smart-972f81fd-777c-43a4-a6da-1681057c300b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706724313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2706724313
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3404326653
Short name T648
Test name
Test status
Simulation time 56999999 ps
CPU time 1.51 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:37 PM PDT 24
Peak memory 200040 kb
Host smart-f3472de2-340b-4c19-8af9-fab08256ac8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404326653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3404326653
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1102004996
Short name T630
Test name
Test status
Simulation time 101994785 ps
CPU time 1.29 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:39 PM PDT 24
Peak memory 199864 kb
Host smart-3bcba349-48d4-4ddc-aafa-d477c0e0e6a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102004996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1102004996
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.182186915
Short name T581
Test name
Test status
Simulation time 448404581 ps
CPU time 2.93 seconds
Started Jul 23 06:19:33 PM PDT 24
Finished Jul 23 06:19:46 PM PDT 24
Peak memory 199900 kb
Host smart-d6d4ed0c-af1b-406b-aadd-66f0b0ce950b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182186915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.182186915
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1470797108
Short name T619
Test name
Test status
Simulation time 49372952 ps
CPU time 1.25 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199872 kb
Host smart-3de1ccc8-e090-4daa-8b5e-f75f2f4f35a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470797108 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1470797108
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1673983447
Short name T556
Test name
Test status
Simulation time 24422906 ps
CPU time 0.66 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:50 PM PDT 24
Peak memory 197652 kb
Host smart-0a6aeb48-2310-4c82-890a-36fba15aa837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673983447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1673983447
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.136725474
Short name T632
Test name
Test status
Simulation time 60732474 ps
CPU time 0.64 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:39 PM PDT 24
Peak memory 194832 kb
Host smart-a9103a8c-4789-4039-877b-ef1475df48f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136725474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.136725474
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2965962259
Short name T629
Test name
Test status
Simulation time 211020270 ps
CPU time 1.77 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 199836 kb
Host smart-467299ca-4e51-4071-b60d-7cfba436708b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965962259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2965962259
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3841358154
Short name T634
Test name
Test status
Simulation time 713168470 ps
CPU time 3.85 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:42 PM PDT 24
Peak memory 199880 kb
Host smart-5bdba188-7c88-4b4f-9aa4-219cff6f8ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841358154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3841358154
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.174864659
Short name T132
Test name
Test status
Simulation time 158982380 ps
CPU time 1.81 seconds
Started Jul 23 06:19:28 PM PDT 24
Finished Jul 23 06:19:35 PM PDT 24
Peak memory 199936 kb
Host smart-bde111ec-0625-4be0-bae5-58623d55107d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174864659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.174864659
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4030574489
Short name T579
Test name
Test status
Simulation time 108216517 ps
CPU time 1.44 seconds
Started Jul 23 06:19:32 PM PDT 24
Finished Jul 23 06:19:44 PM PDT 24
Peak memory 199860 kb
Host smart-57f445e0-d471-4892-bebd-c4b9fbfb8459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030574489 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4030574489
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3336318575
Short name T109
Test name
Test status
Simulation time 278215334 ps
CPU time 0.96 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:36 PM PDT 24
Peak memory 199464 kb
Host smart-fe7f2e27-e7cd-4d75-805a-9493b4a25ce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336318575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3336318575
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.790256167
Short name T615
Test name
Test status
Simulation time 17639353 ps
CPU time 0.59 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:38 PM PDT 24
Peak memory 194932 kb
Host smart-861cf70e-dedc-421e-bb5d-167e6f6eb5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790256167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.790256167
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2767586541
Short name T609
Test name
Test status
Simulation time 113339494 ps
CPU time 2.21 seconds
Started Jul 23 06:19:31 PM PDT 24
Finished Jul 23 06:19:43 PM PDT 24
Peak memory 199920 kb
Host smart-010df2fe-f5b8-40f4-a353-ebabb5bcc2f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767586541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2767586541
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4164022648
Short name T539
Test name
Test status
Simulation time 209112682 ps
CPU time 2.7 seconds
Started Jul 23 06:19:37 PM PDT 24
Finished Jul 23 06:19:52 PM PDT 24
Peak memory 199884 kb
Host smart-79386ecf-31f9-42dc-88cd-f0f03d8515b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164022648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4164022648
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.434528690
Short name T125
Test name
Test status
Simulation time 988587167 ps
CPU time 4.08 seconds
Started Jul 23 06:19:29 PM PDT 24
Finished Jul 23 06:19:40 PM PDT 24
Peak memory 199884 kb
Host smart-1033cefa-5834-4b26-8e39-e754ef41b112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434528690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.434528690
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2867399368
Short name T277
Test name
Test status
Simulation time 16032259 ps
CPU time 0.6 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:19:51 PM PDT 24
Peak memory 195916 kb
Host smart-d2509526-afed-4baa-adcd-364388008662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867399368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2867399368
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2813663887
Short name T508
Test name
Test status
Simulation time 7745218947 ps
CPU time 86.18 seconds
Started Jul 23 06:19:44 PM PDT 24
Finished Jul 23 06:21:21 PM PDT 24
Peak memory 199720 kb
Host smart-8f7e2bd1-cf13-488c-abed-57d175f683ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813663887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2813663887
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.307180602
Short name T436
Test name
Test status
Simulation time 12339566791 ps
CPU time 58.1 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:20:52 PM PDT 24
Peak memory 199732 kb
Host smart-0cf7dab3-0338-48a1-9bf8-a9db8a1eb79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307180602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.307180602
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1627807864
Short name T353
Test name
Test status
Simulation time 11064282420 ps
CPU time 326.73 seconds
Started Jul 23 06:19:41 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 597016 kb
Host smart-6ee0633c-0d91-4c8d-b36b-dc597355e55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627807864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1627807864
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1391033449
Short name T236
Test name
Test status
Simulation time 39948385763 ps
CPU time 163.61 seconds
Started Jul 23 06:19:40 PM PDT 24
Finished Jul 23 06:22:36 PM PDT 24
Peak memory 199788 kb
Host smart-6c91fd77-489d-4f74-a62c-7d1378197680
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391033449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1391033449
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3339515621
Short name T164
Test name
Test status
Simulation time 27301764437 ps
CPU time 87.97 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:21:23 PM PDT 24
Peak memory 199788 kb
Host smart-bc4df222-a161-46cd-aca0-2e15470985dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339515621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3339515621
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2378875339
Short name T197
Test name
Test status
Simulation time 1077056915 ps
CPU time 3.51 seconds
Started Jul 23 06:19:42 PM PDT 24
Finished Jul 23 06:19:57 PM PDT 24
Peak memory 199660 kb
Host smart-532197ea-2833-4146-99fa-c711780fe5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378875339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2378875339
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.105991627
Short name T462
Test name
Test status
Simulation time 50385563432 ps
CPU time 858.32 seconds
Started Jul 23 06:19:41 PM PDT 24
Finished Jul 23 06:34:11 PM PDT 24
Peak memory 627540 kb
Host smart-798057fc-3804-4939-a009-788e42ce20f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105991627 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.105991627
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1455072268
Short name T17
Test name
Test status
Simulation time 78092217593 ps
CPU time 1415.59 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:43:24 PM PDT 24
Peak memory 737040 kb
Host smart-b5e0573a-635e-4891-9d47-35ec5e73eab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455072268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1455072268
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2412276942
Short name T203
Test name
Test status
Simulation time 4950842130 ps
CPU time 47.06 seconds
Started Jul 23 06:19:45 PM PDT 24
Finished Jul 23 06:20:43 PM PDT 24
Peak memory 199740 kb
Host smart-907ffe64-01ce-4933-9e47-d4ac107af343
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2412276942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2412276942
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2521199827
Short name T491
Test name
Test status
Simulation time 9278493810 ps
CPU time 91.83 seconds
Started Jul 23 06:19:36 PM PDT 24
Finished Jul 23 06:21:21 PM PDT 24
Peak memory 199712 kb
Host smart-4a274c41-bb8c-4fa4-9949-ad9d15c5bc37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2521199827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2521199827
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1107365227
Short name T1
Test name
Test status
Simulation time 31423745411 ps
CPU time 90.93 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:21:26 PM PDT 24
Peak memory 199712 kb
Host smart-88aa18a4-3302-414e-8cdb-b11ab64b2177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1107365227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1107365227
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2603263480
Short name T61
Test name
Test status
Simulation time 33562191466 ps
CPU time 619.58 seconds
Started Jul 23 06:19:34 PM PDT 24
Finished Jul 23 06:30:05 PM PDT 24
Peak memory 199800 kb
Host smart-f9717cb4-d7dd-4680-89e7-9ca9cc781acf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2603263480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2603263480
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2334727049
Short name T304
Test name
Test status
Simulation time 147330219224 ps
CPU time 2516.74 seconds
Started Jul 23 06:19:48 PM PDT 24
Finished Jul 23 07:01:53 PM PDT 24
Peak memory 215304 kb
Host smart-a8c843b1-add7-4810-b319-16dc7f0edcda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2334727049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2334727049
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3454581994
Short name T325
Test name
Test status
Simulation time 31469776524 ps
CPU time 139.1 seconds
Started Jul 23 06:19:38 PM PDT 24
Finished Jul 23 06:22:09 PM PDT 24
Peak memory 199792 kb
Host smart-7827e432-5afc-46a2-af29-c571396ffb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454581994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3454581994
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2301400125
Short name T36
Test name
Test status
Simulation time 18672471 ps
CPU time 0.58 seconds
Started Jul 23 06:19:47 PM PDT 24
Finished Jul 23 06:19:57 PM PDT 24
Peak memory 194600 kb
Host smart-3248b1e8-b7c3-49b2-9efe-91f3f873d856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301400125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2301400125
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2505203025
Short name T241
Test name
Test status
Simulation time 1929019321 ps
CPU time 56.47 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:20:52 PM PDT 24
Peak memory 199704 kb
Host smart-f44268e8-15f1-43d4-99da-5576bc3b0021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505203025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2505203025
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1876682416
Short name T430
Test name
Test status
Simulation time 2597471513 ps
CPU time 35.15 seconds
Started Jul 23 06:19:42 PM PDT 24
Finished Jul 23 06:20:28 PM PDT 24
Peak memory 199992 kb
Host smart-a16bf6b5-fe52-4164-8524-7cd2338ee2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876682416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1876682416
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.486018091
Short name T392
Test name
Test status
Simulation time 6276302597 ps
CPU time 1229.75 seconds
Started Jul 23 06:19:40 PM PDT 24
Finished Jul 23 06:40:22 PM PDT 24
Peak memory 724260 kb
Host smart-c064b14f-d59c-4359-a4ec-1aa3c82a36db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486018091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.486018091
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1041386476
Short name T9
Test name
Test status
Simulation time 13824777131 ps
CPU time 170.91 seconds
Started Jul 23 06:19:49 PM PDT 24
Finished Jul 23 06:22:47 PM PDT 24
Peak memory 199736 kb
Host smart-051e9c7b-13b3-4cea-b895-3631c8caba8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041386476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1041386476
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2669420539
Short name T59
Test name
Test status
Simulation time 130473204 ps
CPU time 0.86 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:19:54 PM PDT 24
Peak memory 218356 kb
Host smart-5c34d3ba-f316-493f-92cc-dafc9ab6e8b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669420539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2669420539
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2013322376
Short name T314
Test name
Test status
Simulation time 1075659642 ps
CPU time 12.87 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:20:07 PM PDT 24
Peak memory 199748 kb
Host smart-685d89fa-a009-4023-a262-2e6b943ab7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013322376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2013322376
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1531355006
Short name T401
Test name
Test status
Simulation time 47600480569 ps
CPU time 1040.01 seconds
Started Jul 23 06:19:44 PM PDT 24
Finished Jul 23 06:37:15 PM PDT 24
Peak memory 595844 kb
Host smart-d1645d2b-c453-4dd1-9d00-ffdc970b2b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531355006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1531355006
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3424603427
Short name T7
Test name
Test status
Simulation time 90969471769 ps
CPU time 1371.13 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:42:47 PM PDT 24
Peak memory 213832 kb
Host smart-01292e9f-5b4b-4c88-a4f2-a5202eb068e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424603427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3424603427
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2179148079
Short name T416
Test name
Test status
Simulation time 4891688798 ps
CPU time 45.05 seconds
Started Jul 23 06:19:41 PM PDT 24
Finished Jul 23 06:20:37 PM PDT 24
Peak memory 199784 kb
Host smart-94831fa1-9b51-458c-a2ff-17c65cb45f7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2179148079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2179148079
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.4086393529
Short name T427
Test name
Test status
Simulation time 23920402268 ps
CPU time 100.75 seconds
Started Jul 23 06:19:49 PM PDT 24
Finished Jul 23 06:21:37 PM PDT 24
Peak memory 199756 kb
Host smart-f635dfae-982c-4816-9195-9945b7b3e594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4086393529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.4086393529
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1210711380
Short name T415
Test name
Test status
Simulation time 92727880378 ps
CPU time 87.92 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:21:22 PM PDT 24
Peak memory 199692 kb
Host smart-1ea7c23c-9fa4-4ae2-a6ba-d32767fdba00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1210711380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1210711380
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2288880888
Short name T137
Test name
Test status
Simulation time 37417646946 ps
CPU time 664.01 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:30:59 PM PDT 24
Peak memory 199748 kb
Host smart-45692089-8c4d-42f3-8f11-e4dcef8cdef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2288880888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2288880888
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3634835407
Short name T174
Test name
Test status
Simulation time 427001853842 ps
CPU time 2541.26 seconds
Started Jul 23 06:19:44 PM PDT 24
Finished Jul 23 07:02:16 PM PDT 24
Peak memory 215224 kb
Host smart-9ef1038b-4fe8-4572-84cb-0b0d4ebccfa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3634835407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3634835407
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4259876183
Short name T80
Test name
Test status
Simulation time 557791582228 ps
CPU time 2378.09 seconds
Started Jul 23 06:19:42 PM PDT 24
Finished Jul 23 06:59:32 PM PDT 24
Peak memory 215320 kb
Host smart-585e63d2-0102-40e4-ba80-632975b90a37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4259876183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4259876183
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3749310994
Short name T161
Test name
Test status
Simulation time 7525199326 ps
CPU time 5.3 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:19:59 PM PDT 24
Peak memory 199800 kb
Host smart-225a5dae-99d2-4a99-aa95-2ea321885f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749310994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3749310994
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3474102762
Short name T525
Test name
Test status
Simulation time 38023460 ps
CPU time 0.59 seconds
Started Jul 23 06:20:25 PM PDT 24
Finished Jul 23 06:20:27 PM PDT 24
Peak memory 194660 kb
Host smart-a2f8e094-fe47-4df9-bb6e-36eceabb35a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474102762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3474102762
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.660507860
Short name T488
Test name
Test status
Simulation time 1975879278 ps
CPU time 29.73 seconds
Started Jul 23 06:20:29 PM PDT 24
Finished Jul 23 06:21:00 PM PDT 24
Peak memory 199700 kb
Host smart-f35a2572-b1e3-465a-867c-96d249affa1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660507860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.660507860
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3814043162
Short name T385
Test name
Test status
Simulation time 962258487 ps
CPU time 25.95 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:20:57 PM PDT 24
Peak memory 199676 kb
Host smart-fc368c15-7acc-4819-8f68-6692859c7455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814043162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3814043162
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.989552680
Short name T345
Test name
Test status
Simulation time 10063153155 ps
CPU time 483.08 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:28:32 PM PDT 24
Peak memory 652900 kb
Host smart-feba68b7-bb24-4a28-8f9c-b974dc38c4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989552680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.989552680
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2920134124
Short name T229
Test name
Test status
Simulation time 20328345313 ps
CPU time 127.8 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 06:22:35 PM PDT 24
Peak memory 199788 kb
Host smart-ed84c4e7-d10c-45cf-863e-cf3f3214f94f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920134124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2920134124
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3902700508
Short name T269
Test name
Test status
Simulation time 10849324789 ps
CPU time 191.62 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:23:44 PM PDT 24
Peak memory 199764 kb
Host smart-a63119f4-230e-461a-bc00-a13137ac0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902700508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3902700508
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2580749987
Short name T501
Test name
Test status
Simulation time 1116902514 ps
CPU time 5.82 seconds
Started Jul 23 06:20:29 PM PDT 24
Finished Jul 23 06:20:36 PM PDT 24
Peak memory 199720 kb
Host smart-b867217e-8672-405d-9460-c6ae36ac16c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580749987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2580749987
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1211696635
Short name T222
Test name
Test status
Simulation time 17526423976 ps
CPU time 926.88 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:35:59 PM PDT 24
Peak memory 747444 kb
Host smart-8e759740-6965-4acd-874d-caa0d8fe78f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211696635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1211696635
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1312993214
Short name T333
Test name
Test status
Simulation time 2088364685 ps
CPU time 110.07 seconds
Started Jul 23 06:20:25 PM PDT 24
Finished Jul 23 06:22:15 PM PDT 24
Peak memory 199720 kb
Host smart-cbe75dbc-5169-4b88-9adf-82b174614e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312993214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1312993214
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3655469548
Short name T184
Test name
Test status
Simulation time 48537007 ps
CPU time 0.56 seconds
Started Jul 23 06:20:29 PM PDT 24
Finished Jul 23 06:20:30 PM PDT 24
Peak memory 195384 kb
Host smart-bf1fc37f-9bd6-4893-8f6e-0e1a7dfacada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655469548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3655469548
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1805704821
Short name T138
Test name
Test status
Simulation time 5180742610 ps
CPU time 68.8 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:21:39 PM PDT 24
Peak memory 216156 kb
Host smart-a6719a62-9a31-4e1e-99d8-9dec16aaa047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805704821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1805704821
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.249005090
Short name T431
Test name
Test status
Simulation time 9436266573 ps
CPU time 28.13 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:20:57 PM PDT 24
Peak memory 199768 kb
Host smart-982a380e-3faa-49ea-a75e-2edd4003b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249005090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.249005090
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.552712601
Short name T200
Test name
Test status
Simulation time 12456118031 ps
CPU time 1135.33 seconds
Started Jul 23 06:20:29 PM PDT 24
Finished Jul 23 06:39:25 PM PDT 24
Peak memory 743596 kb
Host smart-93b2683f-5127-403b-b20a-cd03a743619b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552712601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.552712601
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3308542782
Short name T479
Test name
Test status
Simulation time 4711131767 ps
CPU time 68.96 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:21:40 PM PDT 24
Peak memory 199784 kb
Host smart-14b70cc8-8080-4093-8d29-bfb418fd7eda
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308542782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3308542782
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2442746007
Short name T340
Test name
Test status
Simulation time 6075589575 ps
CPU time 169 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 06:23:16 PM PDT 24
Peak memory 216180 kb
Host smart-fdf005ca-972f-4f41-99da-571626bcfc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442746007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2442746007
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2631077985
Short name T417
Test name
Test status
Simulation time 42263491 ps
CPU time 2.05 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:20:30 PM PDT 24
Peak memory 199720 kb
Host smart-e6e8c9ab-a832-4f2a-9757-f70ecc1dd51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631077985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2631077985
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.680440582
Short name T366
Test name
Test status
Simulation time 288900637698 ps
CPU time 2199.59 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:57:08 PM PDT 24
Peak memory 759848 kb
Host smart-722cef19-248a-4eb1-b6d8-a5c30f108a92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680440582 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.680440582
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1191123122
Short name T444
Test name
Test status
Simulation time 6917070092 ps
CPU time 90.37 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:22:03 PM PDT 24
Peak memory 199720 kb
Host smart-adc009be-c86d-41bf-a9c8-f7a545374d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191123122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1191123122
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1901435040
Short name T60
Test name
Test status
Simulation time 18491809 ps
CPU time 0.6 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 06:20:28 PM PDT 24
Peak memory 195712 kb
Host smart-cad04d00-340e-4e80-9390-9008dfce0ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901435040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1901435040
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1452055880
Short name T406
Test name
Test status
Simulation time 827684815 ps
CPU time 42.64 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:21:15 PM PDT 24
Peak memory 199700 kb
Host smart-1394d2dc-3eff-4b91-bef0-fbe5d2df013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452055880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1452055880
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1309379860
Short name T446
Test name
Test status
Simulation time 2116317290 ps
CPU time 330.8 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:26:02 PM PDT 24
Peak memory 641148 kb
Host smart-ccd7ad18-42c4-4da2-b5f5-6df5522e204c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309379860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1309379860
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2049617185
Short name T267
Test name
Test status
Simulation time 9978391760 ps
CPU time 125.56 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:22:35 PM PDT 24
Peak memory 199760 kb
Host smart-1a0693ee-fcd5-4d09-bda6-6c1fba8bb9f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049617185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2049617185
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2395462725
Short name T376
Test name
Test status
Simulation time 32328597697 ps
CPU time 108.15 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:22:18 PM PDT 24
Peak memory 199824 kb
Host smart-85c49dcb-61d3-4a7e-b85c-3ad43d27640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395462725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2395462725
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2163041552
Short name T45
Test name
Test status
Simulation time 675944265 ps
CPU time 8.86 seconds
Started Jul 23 06:20:29 PM PDT 24
Finished Jul 23 06:20:39 PM PDT 24
Peak memory 199768 kb
Host smart-f26a0b36-c1bb-4b6f-9e9b-716307def04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163041552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2163041552
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1551979882
Short name T469
Test name
Test status
Simulation time 68923676126 ps
CPU time 4136.8 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 07:29:25 PM PDT 24
Peak memory 841084 kb
Host smart-9eda8398-bbbe-4015-8332-ad0c8e0d1ef7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551979882 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1551979882
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1523953796
Short name T163
Test name
Test status
Simulation time 16094790641 ps
CPU time 38.06 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:21:10 PM PDT 24
Peak memory 199732 kb
Host smart-9ad96b70-c69a-4f5e-bdd9-ec7b388b7ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523953796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1523953796
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2480230778
Short name T513
Test name
Test status
Simulation time 95439018 ps
CPU time 0.65 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:20:43 PM PDT 24
Peak memory 195672 kb
Host smart-a8ee9e94-a5db-41f5-b455-a5759e97041e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480230778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2480230778
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3394071454
Short name T8
Test name
Test status
Simulation time 1589282853 ps
CPU time 24.11 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:06 PM PDT 24
Peak memory 199684 kb
Host smart-b1461aec-1bdc-465a-8e3b-8e118dac0869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394071454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3394071454
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2067545699
Short name T188
Test name
Test status
Simulation time 863592791 ps
CPU time 11.33 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:20:50 PM PDT 24
Peak memory 199760 kb
Host smart-b71980d5-3a76-40ca-98d6-f4bd65ffcd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067545699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2067545699
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.807902528
Short name T418
Test name
Test status
Simulation time 1866480041 ps
CPU time 299.65 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:25:41 PM PDT 24
Peak memory 632244 kb
Host smart-7be2b7d3-715a-4462-aa26-1d5c7ef2d98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807902528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.807902528
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1233684321
Short name T154
Test name
Test status
Simulation time 4508616975 ps
CPU time 58.34 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:21:40 PM PDT 24
Peak memory 199672 kb
Host smart-6226068c-4630-47c0-8ed9-5894afcc320d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233684321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1233684321
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2296012143
Short name T373
Test name
Test status
Simulation time 5133839092 ps
CPU time 140.33 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:23:01 PM PDT 24
Peak memory 207996 kb
Host smart-da0867c2-5663-4f3a-bf71-549bd33d8571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296012143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2296012143
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3605981567
Short name T506
Test name
Test status
Simulation time 109840901 ps
CPU time 4.75 seconds
Started Jul 23 06:20:36 PM PDT 24
Finished Jul 23 06:20:42 PM PDT 24
Peak memory 199696 kb
Host smart-b211089b-712a-4fde-92ef-6852bfff3712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605981567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3605981567
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2795537217
Short name T485
Test name
Test status
Simulation time 181307952229 ps
CPU time 591.92 seconds
Started Jul 23 06:20:37 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 456768 kb
Host smart-e89ca3c0-f2e9-4b7c-b119-096a745875a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795537217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2795537217
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3735176437
Short name T120
Test name
Test status
Simulation time 5517853649 ps
CPU time 67.4 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:49 PM PDT 24
Peak memory 199760 kb
Host smart-b233ad37-e079-40c2-9bca-c275a83a5fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735176437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3735176437
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2772858024
Short name T344
Test name
Test status
Simulation time 13954232 ps
CPU time 0.6 seconds
Started Jul 23 06:20:36 PM PDT 24
Finished Jul 23 06:20:37 PM PDT 24
Peak memory 195736 kb
Host smart-137af310-d8f3-491b-8862-9a6ec670c53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772858024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2772858024
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.290892936
Short name T466
Test name
Test status
Simulation time 653534315 ps
CPU time 36.64 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:19 PM PDT 24
Peak memory 199692 kb
Host smart-354af60f-1d97-4610-8582-99dbe549562b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290892936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.290892936
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2775108827
Short name T482
Test name
Test status
Simulation time 1094184380 ps
CPU time 20.27 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:21:00 PM PDT 24
Peak memory 199732 kb
Host smart-b3a61e74-7afc-4da9-b706-ba38e541577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775108827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2775108827
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.807778734
Short name T423
Test name
Test status
Simulation time 17801610263 ps
CPU time 720.32 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:32:43 PM PDT 24
Peak memory 611976 kb
Host smart-81bff2d7-423a-430e-86eb-bd979a38088b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807778734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.807778734
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3947255946
Short name T29
Test name
Test status
Simulation time 1401894588 ps
CPU time 38.84 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:21 PM PDT 24
Peak memory 199672 kb
Host smart-2e6c956c-a8ea-4434-b465-bcf249501236
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947255946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3947255946
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2714674669
Short name T422
Test name
Test status
Simulation time 2268360253 ps
CPU time 123.8 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:22:45 PM PDT 24
Peak memory 199804 kb
Host smart-5fd84a24-93a0-4df8-8b6e-7bc02213d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714674669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2714674669
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4070030279
Short name T135
Test name
Test status
Simulation time 2599888625 ps
CPU time 15.72 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:20:55 PM PDT 24
Peak memory 199756 kb
Host smart-7a531b83-52fb-4a19-b6bf-011777c3c6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070030279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4070030279
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3520034772
Short name T144
Test name
Test status
Simulation time 95866997218 ps
CPU time 1116 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:39:19 PM PDT 24
Peak memory 199780 kb
Host smart-c2c4b9b4-e298-46f9-83c1-46c0c1f5675c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520034772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3520034772
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3955816100
Short name T122
Test name
Test status
Simulation time 691464982 ps
CPU time 32.55 seconds
Started Jul 23 06:20:37 PM PDT 24
Finished Jul 23 06:21:10 PM PDT 24
Peak memory 199712 kb
Host smart-f9e7b014-9ddc-4652-9e0d-d1958a3d3658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955816100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3955816100
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1795689726
Short name T170
Test name
Test status
Simulation time 13624737 ps
CPU time 0.58 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:20:43 PM PDT 24
Peak memory 194644 kb
Host smart-a154a649-ab3a-4bee-9a7f-7be32b23a2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795689726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1795689726
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1088305942
Short name T437
Test name
Test status
Simulation time 539096743 ps
CPU time 30.18 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:21:12 PM PDT 24
Peak memory 199716 kb
Host smart-5d63af15-4ca0-4b6b-a584-9e552e0e662c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088305942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1088305942
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2371079411
Short name T141
Test name
Test status
Simulation time 4298516293 ps
CPU time 53.95 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:21:35 PM PDT 24
Peak memory 199820 kb
Host smart-7cb33193-14b5-4166-8d77-d05871b6c55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371079411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2371079411
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3690346018
Short name T447
Test name
Test status
Simulation time 5700035285 ps
CPU time 1094.52 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:38:57 PM PDT 24
Peak memory 780860 kb
Host smart-e3a26161-6cc2-4eac-ae3d-fd60164d23eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690346018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3690346018
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2228633804
Short name T517
Test name
Test status
Simulation time 29824640052 ps
CPU time 132.79 seconds
Started Jul 23 06:20:35 PM PDT 24
Finished Jul 23 06:22:48 PM PDT 24
Peak memory 199768 kb
Host smart-7e00cf45-60cb-4d4d-9240-59a3e3156412
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228633804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2228633804
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1924162155
Short name T519
Test name
Test status
Simulation time 8773211045 ps
CPU time 111.74 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:22:33 PM PDT 24
Peak memory 199920 kb
Host smart-a6562138-5c9b-4243-8bf4-3cc2caee87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924162155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1924162155
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2845881983
Short name T254
Test name
Test status
Simulation time 380331039 ps
CPU time 9.07 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:20:51 PM PDT 24
Peak memory 199624 kb
Host smart-9eccd7ac-63a3-4ff0-b8a8-b5c11775d922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845881983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2845881983
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4057817167
Short name T500
Test name
Test status
Simulation time 5281530904 ps
CPU time 294.21 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:25:33 PM PDT 24
Peak memory 199652 kb
Host smart-687bff46-4743-41d0-b431-c3dda41590ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057817167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4057817167
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4074243978
Short name T213
Test name
Test status
Simulation time 3209619674 ps
CPU time 74.65 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:21:54 PM PDT 24
Peak memory 199760 kb
Host smart-ea4b88a2-af5d-449a-b8ea-fd1b59dd8ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074243978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4074243978
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2672097440
Short name T404
Test name
Test status
Simulation time 16357990 ps
CPU time 0.62 seconds
Started Jul 23 06:20:37 PM PDT 24
Finished Jul 23 06:20:39 PM PDT 24
Peak memory 195748 kb
Host smart-33eea7d2-d6b6-4aac-89e3-bf57d1f01102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672097440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2672097440
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.68296937
Short name T280
Test name
Test status
Simulation time 1765336597 ps
CPU time 25.79 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:21:07 PM PDT 24
Peak memory 199724 kb
Host smart-b2fd1e52-8db0-4e58-8cf5-e28d4eee48ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68296937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.68296937
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.258079237
Short name T408
Test name
Test status
Simulation time 2602016273 ps
CPU time 54.16 seconds
Started Jul 23 06:20:36 PM PDT 24
Finished Jul 23 06:21:31 PM PDT 24
Peak memory 199804 kb
Host smart-1dc60e0d-616b-4038-83fe-d5090a25affb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258079237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.258079237
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.385484925
Short name T268
Test name
Test status
Simulation time 19785361559 ps
CPU time 897.82 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:35:37 PM PDT 24
Peak memory 711224 kb
Host smart-73f163e6-41ec-4656-847e-360f78f6dff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385484925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.385484925
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1792360729
Short name T167
Test name
Test status
Simulation time 10536571892 ps
CPU time 83.25 seconds
Started Jul 23 06:20:37 PM PDT 24
Finished Jul 23 06:22:01 PM PDT 24
Peak memory 199720 kb
Host smart-b318fdb6-b38e-4f60-8857-70f44aa9b757
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792360729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1792360729
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3993881208
Short name T440
Test name
Test status
Simulation time 187208005 ps
CPU time 3.73 seconds
Started Jul 23 06:20:36 PM PDT 24
Finished Jul 23 06:20:41 PM PDT 24
Peak memory 199752 kb
Host smart-5daf3059-845b-4f4e-905c-0010ef2c52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993881208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3993881208
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.141479729
Short name T10
Test name
Test status
Simulation time 1568997249 ps
CPU time 5.49 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:20:46 PM PDT 24
Peak memory 199764 kb
Host smart-dedac1fc-4f77-4481-a0c3-bf3c9c7e7172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141479729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.141479729
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2610885020
Short name T81
Test name
Test status
Simulation time 13514581252 ps
CPU time 128.74 seconds
Started Jul 23 06:20:36 PM PDT 24
Finished Jul 23 06:22:45 PM PDT 24
Peak memory 208028 kb
Host smart-8917f16e-38bd-4daf-8d68-c1eb226087e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610885020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2610885020
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1881680204
Short name T23
Test name
Test status
Simulation time 377554237 ps
CPU time 5.83 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:20:46 PM PDT 24
Peak memory 199652 kb
Host smart-58cc0614-d28e-4000-a819-c7afeeb3962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881680204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1881680204
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.500370916
Short name T273
Test name
Test status
Simulation time 15757339 ps
CPU time 0.63 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:20:43 PM PDT 24
Peak memory 195732 kb
Host smart-6bd5116c-3585-47ff-8c02-d57eda82e9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500370916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.500370916
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1285631867
Short name T43
Test name
Test status
Simulation time 7903675543 ps
CPU time 48.05 seconds
Started Jul 23 06:20:46 PM PDT 24
Finished Jul 23 06:21:35 PM PDT 24
Peak memory 199760 kb
Host smart-dfdb7232-2e7f-4793-90d5-dd74e8885171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285631867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1285631867
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.254402321
Short name T162
Test name
Test status
Simulation time 2803119188 ps
CPU time 20.48 seconds
Started Jul 23 06:20:45 PM PDT 24
Finished Jul 23 06:21:07 PM PDT 24
Peak memory 199824 kb
Host smart-3cd52a19-5267-4cf7-990c-0a541a2e72bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254402321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.254402321
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_error.770070372
Short name T156
Test name
Test status
Simulation time 3624628889 ps
CPU time 61.06 seconds
Started Jul 23 06:20:45 PM PDT 24
Finished Jul 23 06:21:47 PM PDT 24
Peak memory 199752 kb
Host smart-1c711372-d0eb-4c29-b981-346cf8b8ce22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770070372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.770070372
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4111953478
Short name T390
Test name
Test status
Simulation time 47961290477 ps
CPU time 213.29 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:24:15 PM PDT 24
Peak memory 199792 kb
Host smart-44f27ab7-d695-4fb3-9623-6fe1e6f6d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111953478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4111953478
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2241616354
Short name T14
Test name
Test status
Simulation time 434385062 ps
CPU time 5.61 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:20:46 PM PDT 24
Peak memory 199708 kb
Host smart-5db2a07f-57f6-4091-a00c-fcb5f1d07e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241616354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2241616354
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1204918432
Short name T193
Test name
Test status
Simulation time 37970164503 ps
CPU time 100.81 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:22:23 PM PDT 24
Peak memory 199832 kb
Host smart-f990a6ed-42c3-489b-861d-35ddb81193bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204918432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1204918432
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1180213327
Short name T337
Test name
Test status
Simulation time 12440354 ps
CPU time 0.6 seconds
Started Jul 23 06:20:41 PM PDT 24
Finished Jul 23 06:20:44 PM PDT 24
Peak memory 195668 kb
Host smart-f3b18114-d9d8-42be-867e-9a763448db66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180213327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1180213327
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1915012705
Short name T11
Test name
Test status
Simulation time 10057588250 ps
CPU time 83.56 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:22:06 PM PDT 24
Peak memory 208000 kb
Host smart-f003d3ed-b19e-400b-b3b5-39d400b7d387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915012705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1915012705
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.469092484
Short name T456
Test name
Test status
Simulation time 1146904413 ps
CPU time 42.55 seconds
Started Jul 23 06:20:44 PM PDT 24
Finished Jul 23 06:21:28 PM PDT 24
Peak memory 199724 kb
Host smart-d94fceea-605a-433f-a98b-8fe91e27c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469092484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.469092484
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1446394676
Short name T468
Test name
Test status
Simulation time 8342544088 ps
CPU time 785.87 seconds
Started Jul 23 06:20:44 PM PDT 24
Finished Jul 23 06:33:52 PM PDT 24
Peak memory 707176 kb
Host smart-fdc45492-0ea8-4a17-87d8-d76f306963df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446394676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1446394676
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3371242188
Short name T78
Test name
Test status
Simulation time 975139377 ps
CPU time 51.96 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:35 PM PDT 24
Peak memory 199564 kb
Host smart-62318079-a260-41e0-bd5a-751fe63eb97a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371242188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3371242188
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3245758787
Short name T166
Test name
Test status
Simulation time 1856296806 ps
CPU time 99 seconds
Started Jul 23 06:20:44 PM PDT 24
Finished Jul 23 06:22:23 PM PDT 24
Peak memory 199724 kb
Host smart-33c26549-d52e-4b9f-9072-55445339aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245758787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3245758787
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.295021241
Short name T255
Test name
Test status
Simulation time 1372448508 ps
CPU time 9 seconds
Started Jul 23 06:20:39 PM PDT 24
Finished Jul 23 06:20:51 PM PDT 24
Peak memory 199792 kb
Host smart-208d3090-397f-44fb-9eb2-1189a80085df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295021241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.295021241
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.103965888
Short name T183
Test name
Test status
Simulation time 14183923854 ps
CPU time 43.38 seconds
Started Jul 23 06:20:44 PM PDT 24
Finished Jul 23 06:21:29 PM PDT 24
Peak memory 199784 kb
Host smart-082f2981-378f-48f4-b23d-7b89a114bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103965888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.103965888
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1640389122
Short name T458
Test name
Test status
Simulation time 47344405 ps
CPU time 0.59 seconds
Started Jul 23 06:20:46 PM PDT 24
Finished Jul 23 06:20:48 PM PDT 24
Peak memory 195472 kb
Host smart-c1d34b46-49d2-4484-8d8a-32880b69c571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640389122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1640389122
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.785125884
Short name T520
Test name
Test status
Simulation time 1475142918 ps
CPU time 72.3 seconds
Started Jul 23 06:20:49 PM PDT 24
Finished Jul 23 06:22:03 PM PDT 24
Peak memory 199740 kb
Host smart-a64e4b06-3f73-42c6-94ff-bf22393c679b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785125884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.785125884
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2388466970
Short name T37
Test name
Test status
Simulation time 2474982481 ps
CPU time 42.67 seconds
Started Jul 23 06:20:47 PM PDT 24
Finished Jul 23 06:21:31 PM PDT 24
Peak memory 199748 kb
Host smart-3a36e9b2-669e-4add-9cd5-090cf5d449a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388466970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2388466970
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.484760313
Short name T283
Test name
Test status
Simulation time 3182813513 ps
CPU time 534.46 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:29:48 PM PDT 24
Peak memory 632292 kb
Host smart-a45e3b26-bc60-4e3c-a7a9-df2fab3f8db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484760313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.484760313
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4017919814
Short name T350
Test name
Test status
Simulation time 195971496 ps
CPU time 10.7 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:21:01 PM PDT 24
Peak memory 199612 kb
Host smart-3e22de06-1a32-481c-bd3d-1597d5749beb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017919814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4017919814
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3981370184
Short name T160
Test name
Test status
Simulation time 18344978022 ps
CPU time 69.01 seconds
Started Jul 23 06:20:40 PM PDT 24
Finished Jul 23 06:21:51 PM PDT 24
Peak memory 199648 kb
Host smart-0ceb7c0d-a747-4d3c-9569-1f8f8bd8a432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981370184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3981370184
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3791289232
Short name T453
Test name
Test status
Simulation time 3617878003 ps
CPU time 11.5 seconds
Started Jul 23 06:20:38 PM PDT 24
Finished Jul 23 06:20:51 PM PDT 24
Peak memory 199792 kb
Host smart-881c5651-13aa-4d1a-af85-c93d8333f469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791289232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3791289232
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2160992448
Short name T275
Test name
Test status
Simulation time 88388766422 ps
CPU time 2357.52 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 07:00:14 PM PDT 24
Peak memory 749436 kb
Host smart-40de7639-4932-4bbf-9496-1e9855b405b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160992448 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2160992448
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3148978868
Short name T228
Test name
Test status
Simulation time 8177041044 ps
CPU time 75.78 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:22:09 PM PDT 24
Peak memory 199764 kb
Host smart-498a5243-a0c3-4129-babe-64b0033ef446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148978868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3148978868
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4007251550
Short name T312
Test name
Test status
Simulation time 44188917 ps
CPU time 0.62 seconds
Started Jul 23 06:19:44 PM PDT 24
Finished Jul 23 06:19:55 PM PDT 24
Peak memory 195728 kb
Host smart-640448d3-3a53-459f-8288-eb8e061849e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007251550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4007251550
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1507325571
Short name T307
Test name
Test status
Simulation time 1499447845 ps
CPU time 83.54 seconds
Started Jul 23 06:19:49 PM PDT 24
Finished Jul 23 06:21:20 PM PDT 24
Peak memory 199704 kb
Host smart-7c8bd569-4b7b-4363-99f5-7e7573a2a172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507325571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1507325571
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.182735988
Short name T263
Test name
Test status
Simulation time 2481479440 ps
CPU time 29.49 seconds
Started Jul 23 06:19:50 PM PDT 24
Finished Jul 23 06:20:26 PM PDT 24
Peak memory 199828 kb
Host smart-06eb072a-ecea-4d5e-a490-f379c209f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182735988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.182735988
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4195962922
Short name T247
Test name
Test status
Simulation time 5279359869 ps
CPU time 943.43 seconds
Started Jul 23 06:19:44 PM PDT 24
Finished Jul 23 06:35:38 PM PDT 24
Peak memory 694576 kb
Host smart-29944532-d00d-43f2-95da-800fc8d1b2c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195962922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4195962922
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3443884040
Short name T343
Test name
Test status
Simulation time 11539940224 ps
CPU time 30.86 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:20:26 PM PDT 24
Peak memory 199768 kb
Host smart-33e12d71-c294-4d07-bef4-5d76b1db039f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443884040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3443884040
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3048619781
Short name T471
Test name
Test status
Simulation time 1574633557 ps
CPU time 86.66 seconds
Started Jul 23 06:19:42 PM PDT 24
Finished Jul 23 06:21:20 PM PDT 24
Peak memory 199724 kb
Host smart-d5686a5a-afc9-4581-98f3-97fbdb60bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048619781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3048619781
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3050899641
Short name T58
Test name
Test status
Simulation time 86385840 ps
CPU time 1.02 seconds
Started Jul 23 06:19:47 PM PDT 24
Finished Jul 23 06:19:57 PM PDT 24
Peak memory 219372 kb
Host smart-a73e75fa-5a91-41c3-8f39-3c716b25db2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050899641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3050899641
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2528435189
Short name T239
Test name
Test status
Simulation time 1036368411 ps
CPU time 7.06 seconds
Started Jul 23 06:19:49 PM PDT 24
Finished Jul 23 06:20:03 PM PDT 24
Peak memory 199680 kb
Host smart-dfe96594-568a-44c5-8543-2e84fd356e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528435189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2528435189
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3052050657
Short name T370
Test name
Test status
Simulation time 457942160353 ps
CPU time 3602.71 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 07:19:59 PM PDT 24
Peak memory 834028 kb
Host smart-89b1b012-ddf7-4644-9462-1d2bdc0a512a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052050657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3052050657
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.438313301
Short name T74
Test name
Test status
Simulation time 24636471525 ps
CPU time 456.51 seconds
Started Jul 23 06:19:45 PM PDT 24
Finished Jul 23 06:27:31 PM PDT 24
Peak memory 338732 kb
Host smart-65efbc80-fc45-4c95-860e-d7cfbdfec4d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438313301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.438313301
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3068094051
Short name T278
Test name
Test status
Simulation time 1679802514 ps
CPU time 69.84 seconds
Started Jul 23 06:19:47 PM PDT 24
Finished Jul 23 06:21:06 PM PDT 24
Peak memory 199712 kb
Host smart-592b69ec-efdc-4bd9-b20e-0761514b5e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3068094051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3068094051
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.87026180
Short name T475
Test name
Test status
Simulation time 8995636933 ps
CPU time 89.59 seconds
Started Jul 23 06:19:48 PM PDT 24
Finished Jul 23 06:21:26 PM PDT 24
Peak memory 199788 kb
Host smart-bc41d3c2-ed4c-404e-93be-f746e43ad33e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=87026180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.87026180
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1804935471
Short name T66
Test name
Test status
Simulation time 9020124340 ps
CPU time 78.85 seconds
Started Jul 23 06:19:48 PM PDT 24
Finished Jul 23 06:21:15 PM PDT 24
Peak memory 199748 kb
Host smart-7bd6a44e-3a27-40fe-bb50-84ca0febe035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1804935471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1804935471
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1982423599
Short name T288
Test name
Test status
Simulation time 11089686007 ps
CPU time 556.27 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:29:12 PM PDT 24
Peak memory 199812 kb
Host smart-02cd3d4f-0b67-47e3-9917-b5b45072a45c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1982423599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1982423599
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.468362724
Short name T136
Test name
Test status
Simulation time 543538280608 ps
CPU time 2313.62 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:58:30 PM PDT 24
Peak memory 215936 kb
Host smart-42b1ea7e-f7af-440e-a342-9c88cc6b1d0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=468362724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.468362724
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3831460805
Short name T524
Test name
Test status
Simulation time 42505138936 ps
CPU time 2344.14 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:58:58 PM PDT 24
Peak memory 215364 kb
Host smart-45f8b552-df16-4717-911c-9f35b4b0ee73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3831460805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3831460805
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3929448503
Short name T382
Test name
Test status
Simulation time 38674762350 ps
CPU time 128.72 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:22:04 PM PDT 24
Peak memory 199536 kb
Host smart-c8603d6a-4a96-4033-979f-14946e61fcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929448503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3929448503
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3781041612
Short name T492
Test name
Test status
Simulation time 36638776 ps
CPU time 0.61 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 06:20:57 PM PDT 24
Peak memory 195396 kb
Host smart-bb360b6e-9dfc-46ec-a2f7-30b60ea40fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781041612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3781041612
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.476170556
Short name T300
Test name
Test status
Simulation time 1052096195 ps
CPU time 60.93 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:21:57 PM PDT 24
Peak memory 199684 kb
Host smart-64a8e4a6-0b4b-4142-b532-a5907eeb0c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476170556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.476170556
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3865920025
Short name T97
Test name
Test status
Simulation time 1095704619 ps
CPU time 16.55 seconds
Started Jul 23 06:20:45 PM PDT 24
Finished Jul 23 06:21:03 PM PDT 24
Peak memory 199744 kb
Host smart-c7950543-3240-4b6d-9148-46223aa91cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865920025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3865920025
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.920942296
Short name T377
Test name
Test status
Simulation time 1333012309 ps
CPU time 229.15 seconds
Started Jul 23 06:20:47 PM PDT 24
Finished Jul 23 06:24:37 PM PDT 24
Peak memory 488268 kb
Host smart-095b0a81-06b6-4a07-bb81-eb1428c6514d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920942296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.920942296
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3208065113
Short name T313
Test name
Test status
Simulation time 31119580531 ps
CPU time 91.59 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:22:24 PM PDT 24
Peak memory 199772 kb
Host smart-2b54f8ed-f215-4581-bff7-96ac1e469422
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208065113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3208065113
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3017575779
Short name T34
Test name
Test status
Simulation time 1615538401 ps
CPU time 30.02 seconds
Started Jul 23 06:20:45 PM PDT 24
Finished Jul 23 06:21:17 PM PDT 24
Peak memory 199684 kb
Host smart-eb6a7acf-4014-44d3-990f-eb025daa95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017575779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3017575779
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1615349378
Short name T38
Test name
Test status
Simulation time 441280562 ps
CPU time 9.44 seconds
Started Jul 23 06:20:47 PM PDT 24
Finished Jul 23 06:20:57 PM PDT 24
Peak memory 199708 kb
Host smart-ab9415f8-f3d2-4bf5-95dd-b4b1cce21420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615349378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1615349378
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.839611823
Short name T121
Test name
Test status
Simulation time 27811858309 ps
CPU time 1391.4 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 710024 kb
Host smart-86abdb63-f2d3-418d-a791-285b8bd59637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839611823 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.839611823
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3890233479
Short name T94
Test name
Test status
Simulation time 11376729148 ps
CPU time 24.68 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:21:19 PM PDT 24
Peak memory 199784 kb
Host smart-26e709d1-a86c-4802-a5df-b345785d4346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890233479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3890233479
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1456014508
Short name T429
Test name
Test status
Simulation time 13522389 ps
CPU time 0.56 seconds
Started Jul 23 06:20:45 PM PDT 24
Finished Jul 23 06:20:48 PM PDT 24
Peak memory 194620 kb
Host smart-084d7bd4-d610-46dd-80f2-84c6214716b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456014508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1456014508
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1479620599
Short name T270
Test name
Test status
Simulation time 1508640962 ps
CPU time 42.57 seconds
Started Jul 23 06:20:49 PM PDT 24
Finished Jul 23 06:21:34 PM PDT 24
Peak memory 199740 kb
Host smart-74718733-eb2c-43e9-a7b9-73629215939d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479620599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1479620599
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2742336219
Short name T331
Test name
Test status
Simulation time 1399423863 ps
CPU time 18.56 seconds
Started Jul 23 06:20:46 PM PDT 24
Finished Jul 23 06:21:06 PM PDT 24
Peak memory 199780 kb
Host smart-5332721e-73cc-46b4-9777-720fd52690b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742336219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2742336219
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.403370321
Short name T448
Test name
Test status
Simulation time 8277569903 ps
CPU time 646.88 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 719088 kb
Host smart-a9395360-53c5-4be2-a152-c62a2e39eba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403370321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.403370321
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3110419423
Short name T151
Test name
Test status
Simulation time 4775928830 ps
CPU time 82.73 seconds
Started Jul 23 06:20:47 PM PDT 24
Finished Jul 23 06:22:11 PM PDT 24
Peak memory 199756 kb
Host smart-12e26107-26dd-43eb-855f-9976aaf519c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110419423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3110419423
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2472479090
Short name T204
Test name
Test status
Simulation time 5368867581 ps
CPU time 147.74 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:23:21 PM PDT 24
Peak memory 207968 kb
Host smart-01e82dae-e53c-4e82-b894-fa30aff1b6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472479090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2472479090
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.44490211
Short name T317
Test name
Test status
Simulation time 326146157 ps
CPU time 14.37 seconds
Started Jul 23 06:20:47 PM PDT 24
Finished Jul 23 06:21:03 PM PDT 24
Peak memory 199724 kb
Host smart-432e53e3-0efa-4e45-8b83-a07c3bad3e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44490211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.44490211
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1931704030
Short name T328
Test name
Test status
Simulation time 24365843 ps
CPU time 0.66 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:20:50 PM PDT 24
Peak memory 195612 kb
Host smart-a47a5c95-7424-4d68-b8cd-7d9d13c53c2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931704030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1931704030
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.123357933
Short name T296
Test name
Test status
Simulation time 3720671323 ps
CPU time 108.13 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 06:22:45 PM PDT 24
Peak memory 199848 kb
Host smart-c6379962-ecb8-4e13-9844-c5efbf46578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123357933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.123357933
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3754277837
Short name T259
Test name
Test status
Simulation time 128937261 ps
CPU time 0.58 seconds
Started Jul 23 06:21:03 PM PDT 24
Finished Jul 23 06:21:05 PM PDT 24
Peak memory 194688 kb
Host smart-94f05b29-8e37-4fbb-b648-77e96ba39a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754277837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3754277837
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.110215450
Short name T351
Test name
Test status
Simulation time 440844738 ps
CPU time 13.54 seconds
Started Jul 23 06:20:51 PM PDT 24
Finished Jul 23 06:21:06 PM PDT 24
Peak memory 199632 kb
Host smart-7b6d67d7-501c-43d3-9f12-31a0d4ef9f84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110215450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.110215450
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2480479235
Short name T467
Test name
Test status
Simulation time 3246085853 ps
CPU time 28.89 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:21:18 PM PDT 24
Peak memory 199840 kb
Host smart-f6dc731f-a026-4ab0-a096-7f1e5053d7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480479235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2480479235
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.499170041
Short name T272
Test name
Test status
Simulation time 2939607657 ps
CPU time 533.44 seconds
Started Jul 23 06:20:50 PM PDT 24
Finished Jul 23 06:29:45 PM PDT 24
Peak memory 672344 kb
Host smart-8c3a78d0-03fe-406a-b727-7fe323ebfb66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499170041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.499170041
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.972773215
Short name T19
Test name
Test status
Simulation time 19027069847 ps
CPU time 197.4 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:24:08 PM PDT 24
Peak memory 199764 kb
Host smart-72c05542-d5df-4e26-a67a-f0f04bbf839f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972773215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.972773215
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2829447842
Short name T526
Test name
Test status
Simulation time 3914940902 ps
CPU time 17.07 seconds
Started Jul 23 06:20:49 PM PDT 24
Finished Jul 23 06:21:07 PM PDT 24
Peak memory 199780 kb
Host smart-e3043a50-fb58-4033-af72-46a05e19cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829447842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2829447842
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1181088385
Short name T175
Test name
Test status
Simulation time 689931723 ps
CPU time 5.8 seconds
Started Jul 23 06:20:48 PM PDT 24
Finished Jul 23 06:20:55 PM PDT 24
Peak memory 199692 kb
Host smart-2e9f407a-ea2d-476b-9dc3-b5bd3f1a23c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181088385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1181088385
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2924778559
Short name T463
Test name
Test status
Simulation time 34607216135 ps
CPU time 425.97 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 06:28:02 PM PDT 24
Peak memory 199672 kb
Host smart-dd6ddcfd-6dbb-4e8b-9877-353330d29afe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924778559 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2924778559
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.578613904
Short name T15
Test name
Test status
Simulation time 5442439682 ps
CPU time 70.93 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 06:22:07 PM PDT 24
Peak memory 199772 kb
Host smart-c1b735a9-1e05-4250-a1bb-01a70bbb726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578613904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.578613904
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1080629936
Short name T62
Test name
Test status
Simulation time 19061893 ps
CPU time 0.57 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:20:54 PM PDT 24
Peak memory 194712 kb
Host smart-0d9d2d25-9389-4e9d-a535-c2f96f6a65e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080629936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1080629936
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2201574185
Short name T497
Test name
Test status
Simulation time 597043278 ps
CPU time 36.67 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:21:32 PM PDT 24
Peak memory 199728 kb
Host smart-29cb8d58-c410-4a11-8a7f-e948eb45692a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201574185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2201574185
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2349083203
Short name T375
Test name
Test status
Simulation time 3145850290 ps
CPU time 27.4 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:21:22 PM PDT 24
Peak memory 199756 kb
Host smart-aefbee67-e0f5-44ea-ac9b-bf2f942d7186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349083203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2349083203
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2209185379
Short name T249
Test name
Test status
Simulation time 7574717864 ps
CPU time 468.06 seconds
Started Jul 23 06:21:03 PM PDT 24
Finished Jul 23 06:28:52 PM PDT 24
Peak memory 686628 kb
Host smart-6d5ccc93-70b4-460f-95db-c2c3a6673c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209185379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2209185379
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2922469568
Short name T198
Test name
Test status
Simulation time 68092495986 ps
CPU time 173.98 seconds
Started Jul 23 06:21:03 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 199756 kb
Host smart-c557f52c-7421-4f3e-a45f-2fd100dab4d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922469568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2922469568
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1538616765
Short name T439
Test name
Test status
Simulation time 4588973870 ps
CPU time 81.54 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:22:17 PM PDT 24
Peak memory 216152 kb
Host smart-78e26ac0-7023-4e1c-b7b2-80b119a4ae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538616765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1538616765
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.897602781
Short name T391
Test name
Test status
Simulation time 1111070638 ps
CPU time 10.15 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:21:03 PM PDT 24
Peak memory 199712 kb
Host smart-73e27db3-d2cb-434e-8d55-9c41a1ff9bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897602781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.897602781
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1622043516
Short name T309
Test name
Test status
Simulation time 15146593510 ps
CPU time 58.16 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:21:52 PM PDT 24
Peak memory 199812 kb
Host smart-c9956fbe-7df4-4e97-a64b-76fb6f69ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622043516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1622043516
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.599093451
Short name T321
Test name
Test status
Simulation time 46378632 ps
CPU time 0.56 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:20:55 PM PDT 24
Peak memory 194724 kb
Host smart-81303ee5-0d41-478c-8428-4b10dc1c6336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599093451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.599093451
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2897677676
Short name T195
Test name
Test status
Simulation time 3574450097 ps
CPU time 56.07 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:21:51 PM PDT 24
Peak memory 199788 kb
Host smart-fb7110e7-401e-4ffe-a815-d56c06e39e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897677676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2897677676
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3081685666
Short name T178
Test name
Test status
Simulation time 9795975028 ps
CPU time 35.53 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:21:34 PM PDT 24
Peak memory 199456 kb
Host smart-e4097fd2-ab61-4013-a12d-6c118d84a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081685666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3081685666
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3035750342
Short name T432
Test name
Test status
Simulation time 16583288475 ps
CPU time 305.65 seconds
Started Jul 23 06:21:03 PM PDT 24
Finished Jul 23 06:26:10 PM PDT 24
Peak memory 650252 kb
Host smart-10ccdbac-fd79-4df5-8df0-00bd939a7690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035750342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3035750342
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2586400270
Short name T77
Test name
Test status
Simulation time 4152022839 ps
CPU time 15.59 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:21:14 PM PDT 24
Peak memory 199396 kb
Host smart-e6be0c84-b544-4af0-8840-3c56f3226e60
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586400270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2586400270
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.915732120
Short name T503
Test name
Test status
Simulation time 119026797 ps
CPU time 1.69 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:20:55 PM PDT 24
Peak memory 199592 kb
Host smart-616dd5fc-bbf1-48d3-8765-96f73bb462a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915732120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.915732120
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2678030617
Short name T396
Test name
Test status
Simulation time 888377145 ps
CPU time 3.09 seconds
Started Jul 23 06:20:52 PM PDT 24
Finished Jul 23 06:20:56 PM PDT 24
Peak memory 199744 kb
Host smart-699891fb-b6d5-41a9-8df8-919cc103f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678030617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2678030617
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.628397913
Short name T52
Test name
Test status
Simulation time 297742108992 ps
CPU time 1060.64 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:38:40 PM PDT 24
Peak memory 199780 kb
Host smart-93de362b-f8c3-41a1-bb7c-c8d41b30768d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628397913 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.628397913
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1425921031
Short name T286
Test name
Test status
Simulation time 2610884653 ps
CPU time 23.64 seconds
Started Jul 23 06:20:57 PM PDT 24
Finished Jul 23 06:21:21 PM PDT 24
Peak memory 199780 kb
Host smart-6425e702-f444-4121-9696-422401cf78c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425921031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1425921031
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1488850983
Short name T498
Test name
Test status
Simulation time 34018852 ps
CPU time 0.58 seconds
Started Jul 23 06:20:57 PM PDT 24
Finished Jul 23 06:20:59 PM PDT 24
Peak memory 196408 kb
Host smart-f300237e-f161-44d8-8b43-45383717b56e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488850983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1488850983
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3382660576
Short name T487
Test name
Test status
Simulation time 1347261736 ps
CPU time 39.88 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:21:35 PM PDT 24
Peak memory 199796 kb
Host smart-5da000da-bc05-4e2f-8035-b7fad2c597f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382660576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3382660576
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1832525933
Short name T41
Test name
Test status
Simulation time 793443962 ps
CPU time 11.22 seconds
Started Jul 23 06:20:53 PM PDT 24
Finished Jul 23 06:21:06 PM PDT 24
Peak memory 199720 kb
Host smart-c2e50dfd-e133-49cb-ba08-859224dfc53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832525933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1832525933
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.258581725
Short name T381
Test name
Test status
Simulation time 4241026388 ps
CPU time 757.88 seconds
Started Jul 23 06:20:55 PM PDT 24
Finished Jul 23 06:33:35 PM PDT 24
Peak memory 688284 kb
Host smart-29410a55-be60-468f-99e2-7aae8aeb3993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258581725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.258581725
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3337198167
Short name T457
Test name
Test status
Simulation time 7135197859 ps
CPU time 86.11 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:22:25 PM PDT 24
Peak memory 199776 kb
Host smart-aa09125e-7fd0-4328-99a1-cc11fa6163c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337198167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3337198167
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4198270939
Short name T295
Test name
Test status
Simulation time 46212484585 ps
CPU time 208.01 seconds
Started Jul 23 06:21:02 PM PDT 24
Finished Jul 23 06:24:31 PM PDT 24
Peak memory 199776 kb
Host smart-e7a96a7d-a764-47d2-9d1d-f51fecda385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198270939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4198270939
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2453911151
Short name T336
Test name
Test status
Simulation time 1086601844 ps
CPU time 12.38 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:21:11 PM PDT 24
Peak memory 199568 kb
Host smart-3bfd1d73-274a-4646-9980-f19c2a0fc1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453911151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2453911151
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2529009204
Short name T368
Test name
Test status
Simulation time 161771641714 ps
CPU time 3469.19 seconds
Started Jul 23 06:20:57 PM PDT 24
Finished Jul 23 07:18:47 PM PDT 24
Peak memory 844352 kb
Host smart-17d70f47-29cd-493d-928a-d5d19dd7adca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529009204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2529009204
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3126763089
Short name T158
Test name
Test status
Simulation time 2279270948 ps
CPU time 33.6 seconds
Started Jul 23 06:20:54 PM PDT 24
Finished Jul 23 06:21:28 PM PDT 24
Peak memory 199788 kb
Host smart-67bf5f1f-c60f-4c66-87f9-abc08d9d6815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126763089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3126763089
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2930019240
Short name T293
Test name
Test status
Simulation time 14795481 ps
CPU time 0.62 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:10 PM PDT 24
Peak memory 195732 kb
Host smart-ae11bca1-dcbb-428a-abe0-4cdabd6b22b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930019240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2930019240
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.115223393
Short name T30
Test name
Test status
Simulation time 3535653144 ps
CPU time 56.29 seconds
Started Jul 23 06:20:59 PM PDT 24
Finished Jul 23 06:21:56 PM PDT 24
Peak memory 199820 kb
Host smart-0d9ec379-6636-4633-b932-e4c6e3d59478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115223393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.115223393
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2951506917
Short name T480
Test name
Test status
Simulation time 2261875935 ps
CPU time 29.87 seconds
Started Jul 23 06:20:59 PM PDT 24
Finished Jul 23 06:21:30 PM PDT 24
Peak memory 199788 kb
Host smart-181e67e5-d0b1-4cc1-8db8-130a532fa739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951506917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2951506917
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1944752695
Short name T25
Test name
Test status
Simulation time 2275240455 ps
CPU time 131.9 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:23:11 PM PDT 24
Peak memory 596080 kb
Host smart-d0fbe013-cd0e-4461-8e29-ae5894f1d826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944752695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1944752695
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4222003184
Short name T79
Test name
Test status
Simulation time 18599538972 ps
CPU time 75.25 seconds
Started Jul 23 06:20:59 PM PDT 24
Finished Jul 23 06:22:15 PM PDT 24
Peak memory 199660 kb
Host smart-b63ffda0-1ea1-48ee-bc64-8f86e4e317b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222003184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4222003184
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1537077244
Short name T190
Test name
Test status
Simulation time 10848946887 ps
CPU time 109.54 seconds
Started Jul 23 06:21:06 PM PDT 24
Finished Jul 23 06:22:57 PM PDT 24
Peak memory 199776 kb
Host smart-0dc3d878-8eaf-430b-863c-11dd48ed72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537077244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1537077244
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3690740165
Short name T134
Test name
Test status
Simulation time 810968902 ps
CPU time 13.18 seconds
Started Jul 23 06:21:04 PM PDT 24
Finished Jul 23 06:21:18 PM PDT 24
Peak memory 199740 kb
Host smart-b476cd43-e03b-4ac3-8c94-9eb8471ad9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690740165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3690740165
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2278472547
Short name T461
Test name
Test status
Simulation time 2401340091 ps
CPU time 130.94 seconds
Started Jul 23 06:20:59 PM PDT 24
Finished Jul 23 06:23:11 PM PDT 24
Peak memory 199784 kb
Host smart-a350be0e-fbeb-48fb-9d39-07640d53f9cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278472547 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2278472547
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2557994921
Short name T290
Test name
Test status
Simulation time 1071672257 ps
CPU time 5.51 seconds
Started Jul 23 06:20:58 PM PDT 24
Finished Jul 23 06:21:04 PM PDT 24
Peak memory 199688 kb
Host smart-a1273962-0605-4042-bcce-565b11d181b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557994921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2557994921
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2462772361
Short name T250
Test name
Test status
Simulation time 58950890 ps
CPU time 0.58 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:10 PM PDT 24
Peak memory 195700 kb
Host smart-5d295cfe-16b5-49fa-b3df-436119a73b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462772361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2462772361
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.256448045
Short name T31
Test name
Test status
Simulation time 5807133649 ps
CPU time 79.68 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:22:29 PM PDT 24
Peak memory 199812 kb
Host smart-54d86d48-f085-420c-8ba9-8ec42e5ecdf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256448045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.256448045
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1042665976
Short name T266
Test name
Test status
Simulation time 6941139563 ps
CPU time 63.38 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:22:11 PM PDT 24
Peak memory 199792 kb
Host smart-81a5d828-194d-4b3c-9f03-e8296704cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042665976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1042665976
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2117204855
Short name T5
Test name
Test status
Simulation time 3010701118 ps
CPU time 497.59 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 06:29:28 PM PDT 24
Peak memory 673888 kb
Host smart-b9a0e54d-2448-4b5f-8cff-062616a043b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117204855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2117204855
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3925557399
Short name T420
Test name
Test status
Simulation time 9741189276 ps
CPU time 88.4 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 06:22:39 PM PDT 24
Peak memory 199732 kb
Host smart-e0995594-0078-4e3c-b919-9276a423d75a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925557399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3925557399
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2854307923
Short name T528
Test name
Test status
Simulation time 37273628082 ps
CPU time 160.94 seconds
Started Jul 23 06:21:10 PM PDT 24
Finished Jul 23 06:23:53 PM PDT 24
Peak memory 216176 kb
Host smart-a8b523d1-21a9-4cb7-9480-7d0e0931b758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854307923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2854307923
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.417953543
Short name T521
Test name
Test status
Simulation time 31724082 ps
CPU time 1.77 seconds
Started Jul 23 06:21:10 PM PDT 24
Finished Jul 23 06:21:15 PM PDT 24
Peak memory 199700 kb
Host smart-04cc8a95-8e05-42bb-93fb-6ed95d91a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417953543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.417953543
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3338059724
Short name T123
Test name
Test status
Simulation time 511051989931 ps
CPU time 2768.19 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 07:07:17 PM PDT 24
Peak memory 785868 kb
Host smart-3ef09740-5f81-4936-b0e5-e1c0791b28d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338059724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3338059724
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.16247304
Short name T196
Test name
Test status
Simulation time 10137364203 ps
CPU time 104.56 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:22:56 PM PDT 24
Peak memory 199788 kb
Host smart-874aa330-0827-4a13-bffc-f086ece541e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16247304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.16247304
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.920066909
Short name T398
Test name
Test status
Simulation time 44197177 ps
CPU time 0.62 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:21:12 PM PDT 24
Peak memory 195700 kb
Host smart-dc3aa6e5-48d1-4f03-b83e-0fa8ecc78c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920066909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.920066909
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1824551205
Short name T32
Test name
Test status
Simulation time 1422974216 ps
CPU time 79.56 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 06:22:30 PM PDT 24
Peak memory 199732 kb
Host smart-bec28334-6077-4b45-b32a-7c5893c82b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824551205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1824551205
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3734432126
Short name T505
Test name
Test status
Simulation time 1666681048 ps
CPU time 45.71 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:55 PM PDT 24
Peak memory 199700 kb
Host smart-4c039d92-fff6-4465-a31f-5c4cc46989ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734432126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3734432126
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.378300165
Short name T279
Test name
Test status
Simulation time 2012259393 ps
CPU time 376.79 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:27:29 PM PDT 24
Peak memory 630968 kb
Host smart-93298f7c-0e8e-4645-ae33-6230bd41ce53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378300165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.378300165
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4046793032
Short name T189
Test name
Test status
Simulation time 1202985604 ps
CPU time 62.76 seconds
Started Jul 23 06:21:06 PM PDT 24
Finished Jul 23 06:22:10 PM PDT 24
Peak memory 199608 kb
Host smart-d8070f0f-b8f1-427a-8e8a-2dba4523a643
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046793032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4046793032
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2360671798
Short name T450
Test name
Test status
Simulation time 11471229746 ps
CPU time 201.39 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:24:31 PM PDT 24
Peak memory 199804 kb
Host smart-efa99762-6bc8-4fcb-a34e-3cf0acb59850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360671798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2360671798
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1289762205
Short name T354
Test name
Test status
Simulation time 2421082081 ps
CPU time 14.46 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:24 PM PDT 24
Peak memory 199856 kb
Host smart-90645704-389c-4d31-b988-98ffcf65fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289762205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1289762205
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3544667437
Short name T82
Test name
Test status
Simulation time 257794622337 ps
CPU time 3100.94 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 07:12:52 PM PDT 24
Peak memory 730744 kb
Host smart-44ecb015-98fe-4f1b-8122-a249805c5e25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544667437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3544667437
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2638129815
Short name T435
Test name
Test status
Simulation time 8593478238 ps
CPU time 120.41 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:23:08 PM PDT 24
Peak memory 199788 kb
Host smart-27f55457-0906-4257-a9cb-c89fe7dfae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638129815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2638129815
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.485860342
Short name T455
Test name
Test status
Simulation time 14975851 ps
CPU time 0.61 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 06:21:11 PM PDT 24
Peak memory 195712 kb
Host smart-737e7a61-493d-4984-8fe6-cb64094cc5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485860342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.485860342
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.6911118
Short name T243
Test name
Test status
Simulation time 792171866 ps
CPU time 45.56 seconds
Started Jul 23 06:21:11 PM PDT 24
Finished Jul 23 06:22:00 PM PDT 24
Peak memory 199664 kb
Host smart-b421067a-3d84-4333-a9d1-83e0d5f88a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6911118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.6911118
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2602075533
Short name T199
Test name
Test status
Simulation time 128068253 ps
CPU time 7.44 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:21:19 PM PDT 24
Peak memory 199720 kb
Host smart-dd65ff0d-a129-4151-ba32-290ada99d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602075533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2602075533
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3986140188
Short name T192
Test name
Test status
Simulation time 752819071 ps
CPU time 67.17 seconds
Started Jul 23 06:21:10 PM PDT 24
Finished Jul 23 06:22:19 PM PDT 24
Peak memory 342396 kb
Host smart-cdd32346-a4d5-4271-9948-9150a2465187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986140188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3986140188
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4282433811
Short name T206
Test name
Test status
Simulation time 2159225966 ps
CPU time 125.34 seconds
Started Jul 23 06:21:08 PM PDT 24
Finished Jul 23 06:23:16 PM PDT 24
Peak memory 199760 kb
Host smart-850e9c3b-7417-4540-b720-9cf286700781
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282433811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4282433811
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.641906247
Short name T360
Test name
Test status
Simulation time 1188768635 ps
CPU time 58.66 seconds
Started Jul 23 06:21:10 PM PDT 24
Finished Jul 23 06:22:11 PM PDT 24
Peak memory 199720 kb
Host smart-53db9a40-b871-41a5-9390-3b9b33d30efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641906247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.641906247
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.954780690
Short name T179
Test name
Test status
Simulation time 155175190 ps
CPU time 2.57 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:12 PM PDT 24
Peak memory 199648 kb
Host smart-e353e6a1-2719-4095-86d5-f22e494a264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954780690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.954780690
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1123787113
Short name T476
Test name
Test status
Simulation time 161146569945 ps
CPU time 1771.12 seconds
Started Jul 23 06:21:10 PM PDT 24
Finished Jul 23 06:50:44 PM PDT 24
Peak memory 736900 kb
Host smart-3aa8eba1-70fe-43c5-9e75-28463900d977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123787113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1123787113
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2347613334
Short name T411
Test name
Test status
Simulation time 3711430798 ps
CPU time 49.8 seconds
Started Jul 23 06:21:07 PM PDT 24
Finished Jul 23 06:21:59 PM PDT 24
Peak memory 199748 kb
Host smart-29d08d44-6611-480c-a5d6-bfb71daa2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347613334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2347613334
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.766727766
Short name T67
Test name
Test status
Simulation time 96550546 ps
CPU time 0.6 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:23 PM PDT 24
Peak memory 195268 kb
Host smart-24125d6e-cd5b-4d71-8353-b1c59d57a986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766727766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.766727766
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2287924331
Short name T412
Test name
Test status
Simulation time 1931610923 ps
CPU time 78.62 seconds
Started Jul 23 06:19:48 PM PDT 24
Finished Jul 23 06:21:15 PM PDT 24
Peak memory 199696 kb
Host smart-eb457ee5-188a-42d1-b819-d3107bd1238b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287924331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2287924331
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3977954959
Short name T389
Test name
Test status
Simulation time 537138905 ps
CPU time 27.47 seconds
Started Jul 23 06:19:48 PM PDT 24
Finished Jul 23 06:20:24 PM PDT 24
Peak memory 199716 kb
Host smart-29c2ce29-8f75-40d1-b045-f1bfbc6bf5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977954959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3977954959
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2778431388
Short name T494
Test name
Test status
Simulation time 21988147647 ps
CPU time 1069.7 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:37:44 PM PDT 24
Peak memory 671628 kb
Host smart-31222271-beda-4425-bba0-bdca24bcc4a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778431388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2778431388
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3450576370
Short name T169
Test name
Test status
Simulation time 17835708607 ps
CPU time 227.56 seconds
Started Jul 23 06:19:49 PM PDT 24
Finished Jul 23 06:23:44 PM PDT 24
Peak memory 199744 kb
Host smart-91465d92-d81a-439b-8ad5-16bfa005f6a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450576370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3450576370
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2636980688
Short name T365
Test name
Test status
Simulation time 52112489981 ps
CPU time 211.6 seconds
Started Jul 23 06:19:46 PM PDT 24
Finished Jul 23 06:23:27 PM PDT 24
Peak memory 199832 kb
Host smart-27af039f-bfd7-4508-82b8-3f5c332c802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636980688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2636980688
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1534722093
Short name T55
Test name
Test status
Simulation time 223645210 ps
CPU time 0.95 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:20:21 PM PDT 24
Peak memory 218272 kb
Host smart-50be2d00-0e74-4812-930a-c810a4df44de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534722093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1534722093
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4016935311
Short name T50
Test name
Test status
Simulation time 263277995 ps
CPU time 12.18 seconds
Started Jul 23 06:19:43 PM PDT 24
Finished Jul 23 06:20:07 PM PDT 24
Peak memory 199732 kb
Host smart-0cf0fd09-0df1-4f3f-9474-b9cadc0c5249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016935311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4016935311
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.640270617
Short name T207
Test name
Test status
Simulation time 29060296775 ps
CPU time 5462.58 seconds
Started Jul 23 06:20:12 PM PDT 24
Finished Jul 23 07:51:16 PM PDT 24
Peak memory 869860 kb
Host smart-a3fc9db8-9a91-4d09-9bde-c45c3dfa7880
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640270617 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.640270617
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3875240765
Short name T22
Test name
Test status
Simulation time 45733130073 ps
CPU time 974.71 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:36:35 PM PDT 24
Peak memory 690880 kb
Host smart-463c5182-13c6-4def-afd9-2dead5bc400b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875240765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3875240765
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2302462318
Short name T523
Test name
Test status
Simulation time 3246598495 ps
CPU time 70.41 seconds
Started Jul 23 06:20:11 PM PDT 24
Finished Jul 23 06:21:22 PM PDT 24
Peak memory 199784 kb
Host smart-387b0f56-4556-4348-8882-881f2e7bbf24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2302462318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2302462318
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1237125671
Short name T305
Test name
Test status
Simulation time 1779222891 ps
CPU time 58.98 seconds
Started Jul 23 06:20:13 PM PDT 24
Finished Jul 23 06:21:13 PM PDT 24
Peak memory 199608 kb
Host smart-4e85442d-5093-44ad-a3d6-a65d215b0a20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1237125671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1237125671
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3973035790
Short name T186
Test name
Test status
Simulation time 11911584925 ps
CPU time 114.45 seconds
Started Jul 23 06:20:11 PM PDT 24
Finished Jul 23 06:22:06 PM PDT 24
Peak memory 199768 kb
Host smart-b60c9abf-3c6a-4025-a797-0e4a7be2722e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3973035790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3973035790
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2420134512
Short name T214
Test name
Test status
Simulation time 57583227980 ps
CPU time 676.01 seconds
Started Jul 23 06:20:15 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 199720 kb
Host smart-1c67bd3c-b482-473a-8d19-f97f5bd47c0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2420134512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2420134512
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2763744105
Short name T246
Test name
Test status
Simulation time 192044067215 ps
CPU time 2497.33 seconds
Started Jul 23 06:20:12 PM PDT 24
Finished Jul 23 07:01:50 PM PDT 24
Peak memory 215840 kb
Host smart-5bbd9c2f-4e0f-4634-91cd-6f7bf162af76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2763744105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2763744105
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.4061626209
Short name T413
Test name
Test status
Simulation time 204037040929 ps
CPU time 2308.95 seconds
Started Jul 23 06:20:12 PM PDT 24
Finished Jul 23 06:58:42 PM PDT 24
Peak memory 216072 kb
Host smart-b2c761c5-1571-4ccb-820f-948b1d6bc78c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4061626209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4061626209
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3294223042
Short name T217
Test name
Test status
Simulation time 12833545099 ps
CPU time 119.71 seconds
Started Jul 23 06:20:10 PM PDT 24
Finished Jul 23 06:22:10 PM PDT 24
Peak memory 199692 kb
Host smart-c6b6b967-1f10-4a76-909c-ab3441736b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294223042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3294223042
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2342051720
Short name T65
Test name
Test status
Simulation time 14307927 ps
CPU time 0.61 seconds
Started Jul 23 06:21:18 PM PDT 24
Finished Jul 23 06:21:19 PM PDT 24
Peak memory 195724 kb
Host smart-e7489eea-d0e8-4d1d-b176-d5803c1cd0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342051720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2342051720
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1330641111
Short name T386
Test name
Test status
Simulation time 556269149 ps
CPU time 30.52 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:21:42 PM PDT 24
Peak memory 199708 kb
Host smart-94eef525-9318-43b9-a08b-6d998a7dc5b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330641111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1330641111
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.635387711
Short name T262
Test name
Test status
Simulation time 1688847329 ps
CPU time 25.05 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:21:40 PM PDT 24
Peak memory 199736 kb
Host smart-c6c04dbf-e9c1-48d3-8724-b986cac563db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635387711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.635387711
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2897652626
Short name T459
Test name
Test status
Simulation time 3203527437 ps
CPU time 165.37 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:24:00 PM PDT 24
Peak memory 607628 kb
Host smart-252f5abe-1d93-4e1c-871c-69c33545acff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897652626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2897652626
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.769928389
Short name T496
Test name
Test status
Simulation time 9979501330 ps
CPU time 156.66 seconds
Started Jul 23 06:21:20 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 199764 kb
Host smart-12e22b85-60dc-42fd-a7ae-89bb81ac592f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769928389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.769928389
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.922836628
Short name T92
Test name
Test status
Simulation time 15380354 ps
CPU time 0.67 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:21:16 PM PDT 24
Peak memory 196300 kb
Host smart-5bc9963d-832b-4c22-b540-9a35dfd60848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922836628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.922836628
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.777826986
Short name T342
Test name
Test status
Simulation time 1619344094 ps
CPU time 7.73 seconds
Started Jul 23 06:21:09 PM PDT 24
Finished Jul 23 06:21:20 PM PDT 24
Peak memory 199896 kb
Host smart-5ed282ca-f9e5-4540-bdc7-2398dc205a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777826986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.777826986
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.464925670
Short name T303
Test name
Test status
Simulation time 96045660525 ps
CPU time 477.48 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:29:13 PM PDT 24
Peak memory 199764 kb
Host smart-27b8b5f4-6a5e-483e-a41b-87044ef2ca64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464925670 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.464925670
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3289173257
Short name T176
Test name
Test status
Simulation time 33020317853 ps
CPU time 99.61 seconds
Started Jul 23 06:21:14 PM PDT 24
Finished Jul 23 06:22:56 PM PDT 24
Peak memory 199772 kb
Host smart-bdf72011-8d7f-4393-a64e-93818feb0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289173257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3289173257
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3788229839
Short name T335
Test name
Test status
Simulation time 105045161 ps
CPU time 0.6 seconds
Started Jul 23 06:21:13 PM PDT 24
Finished Jul 23 06:21:16 PM PDT 24
Peak memory 195712 kb
Host smart-192a1c67-08d3-4d74-9a0a-cfa38bd4878c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788229839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3788229839
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4123044368
Short name T297
Test name
Test status
Simulation time 561126068 ps
CPU time 30.65 seconds
Started Jul 23 06:21:20 PM PDT 24
Finished Jul 23 06:21:52 PM PDT 24
Peak memory 199740 kb
Host smart-801a28f1-4d1c-43a6-9d5d-86f2f23219b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123044368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4123044368
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.133138537
Short name T230
Test name
Test status
Simulation time 6026964014 ps
CPU time 44.07 seconds
Started Jul 23 06:21:13 PM PDT 24
Finished Jul 23 06:22:00 PM PDT 24
Peak memory 199968 kb
Host smart-b66c32d5-9a29-4603-a30b-e22f05bedef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133138537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.133138537
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.436834210
Short name T234
Test name
Test status
Simulation time 7246389147 ps
CPU time 1396.45 seconds
Started Jul 23 06:21:14 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 729416 kb
Host smart-975c5861-fd4a-4800-8d12-44099245ae5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436834210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.436834210
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1849100227
Short name T504
Test name
Test status
Simulation time 27446441643 ps
CPU time 210.6 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:24:46 PM PDT 24
Peak memory 199744 kb
Host smart-03a6d89a-20a3-4630-afdd-cbbab6f0c503
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849100227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1849100227
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2282750209
Short name T405
Test name
Test status
Simulation time 3467497652 ps
CPU time 62.03 seconds
Started Jul 23 06:21:14 PM PDT 24
Finished Jul 23 06:22:18 PM PDT 24
Peak memory 199784 kb
Host smart-e0958b1a-bd8a-459b-b6f0-34e2808f0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282750209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2282750209
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.532940647
Short name T231
Test name
Test status
Simulation time 927269517 ps
CPU time 2.43 seconds
Started Jul 23 06:21:20 PM PDT 24
Finished Jul 23 06:21:24 PM PDT 24
Peak memory 199760 kb
Host smart-88794e23-298b-4258-b12f-78d671a53344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532940647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.532940647
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2318842828
Short name T88
Test name
Test status
Simulation time 9718421528 ps
CPU time 1026.13 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:38:21 PM PDT 24
Peak memory 708812 kb
Host smart-8fcadb70-256c-4e2b-980e-02ddebb00ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318842828 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2318842828
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.822061502
Short name T379
Test name
Test status
Simulation time 32966603222 ps
CPU time 26.6 seconds
Started Jul 23 06:21:20 PM PDT 24
Finished Jul 23 06:21:48 PM PDT 24
Peak memory 199780 kb
Host smart-9d5e2884-51a8-40c0-8d7f-746d2102cda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822061502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.822061502
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4254205740
Short name T464
Test name
Test status
Simulation time 24455396 ps
CPU time 0.62 seconds
Started Jul 23 06:21:39 PM PDT 24
Finished Jul 23 06:21:41 PM PDT 24
Peak memory 194688 kb
Host smart-d61c564e-65c7-4610-a6ad-90f40a0dec4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254205740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4254205740
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1376960743
Short name T294
Test name
Test status
Simulation time 841807592 ps
CPU time 47.23 seconds
Started Jul 23 06:21:24 PM PDT 24
Finished Jul 23 06:22:12 PM PDT 24
Peak memory 199692 kb
Host smart-d6e274d3-77c2-4db5-a0a6-6c17342219d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376960743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1376960743
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3468457584
Short name T146
Test name
Test status
Simulation time 27830874485 ps
CPU time 60.49 seconds
Started Jul 23 06:21:23 PM PDT 24
Finished Jul 23 06:22:24 PM PDT 24
Peak memory 199784 kb
Host smart-4a0497a7-2c2a-4f8f-b5ef-76378b8e36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468457584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3468457584
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2478231800
Short name T481
Test name
Test status
Simulation time 51533205809 ps
CPU time 503.7 seconds
Started Jul 23 06:21:22 PM PDT 24
Finished Jul 23 06:29:46 PM PDT 24
Peak memory 500172 kb
Host smart-9bf45bbe-8b2c-4098-ae78-96c9e9209b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478231800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2478231800
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.353409235
Short name T395
Test name
Test status
Simulation time 1792534444 ps
CPU time 90.04 seconds
Started Jul 23 06:21:23 PM PDT 24
Finished Jul 23 06:22:54 PM PDT 24
Peak memory 199708 kb
Host smart-b104de7f-f80d-48a5-a118-b154bcfb53ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353409235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.353409235
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1635580758
Short name T527
Test name
Test status
Simulation time 842270198 ps
CPU time 47.33 seconds
Started Jul 23 06:21:13 PM PDT 24
Finished Jul 23 06:22:03 PM PDT 24
Peak memory 199692 kb
Host smart-12a4ce64-c14a-4c76-8200-e116aa8c5cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635580758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1635580758
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2274655157
Short name T194
Test name
Test status
Simulation time 2686912739 ps
CPU time 9.16 seconds
Started Jul 23 06:21:12 PM PDT 24
Finished Jul 23 06:21:24 PM PDT 24
Peak memory 199784 kb
Host smart-5159e42d-269b-40e5-824b-795ffe061206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274655157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2274655157
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.38096788
Short name T358
Test name
Test status
Simulation time 981511490206 ps
CPU time 1471.89 seconds
Started Jul 23 06:21:38 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 768192 kb
Host smart-b8d07d33-10b4-4e59-9f5c-b886d79b0905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38096788 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.38096788
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1696772514
Short name T371
Test name
Test status
Simulation time 3214466527 ps
CPU time 77.58 seconds
Started Jul 23 06:21:30 PM PDT 24
Finished Jul 23 06:22:49 PM PDT 24
Peak memory 199652 kb
Host smart-c4b59514-75e3-415b-9c01-ceb0e6bfd127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696772514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1696772514
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2796630543
Short name T465
Test name
Test status
Simulation time 35139314 ps
CPU time 0.57 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:21:38 PM PDT 24
Peak memory 194716 kb
Host smart-767d3280-7052-4189-a14b-66c77c4516a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796630543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2796630543
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3513597785
Short name T452
Test name
Test status
Simulation time 1406435479 ps
CPU time 74.53 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:22:52 PM PDT 24
Peak memory 199588 kb
Host smart-424b1df8-41e2-4064-a23c-88e2f76e52cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513597785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3513597785
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1762579504
Short name T244
Test name
Test status
Simulation time 2124823575 ps
CPU time 26.99 seconds
Started Jul 23 06:21:37 PM PDT 24
Finished Jul 23 06:22:04 PM PDT 24
Peak memory 199832 kb
Host smart-11641b2e-4939-4e31-8071-5f3f449e2fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762579504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1762579504
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2398562842
Short name T258
Test name
Test status
Simulation time 12681073696 ps
CPU time 596.34 seconds
Started Jul 23 06:21:37 PM PDT 24
Finished Jul 23 06:31:35 PM PDT 24
Peak memory 500636 kb
Host smart-1f3f2e46-7ff4-401a-954c-c80984ef10a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398562842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2398562842
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1772341982
Short name T224
Test name
Test status
Simulation time 6902237344 ps
CPU time 48 seconds
Started Jul 23 06:21:39 PM PDT 24
Finished Jul 23 06:22:27 PM PDT 24
Peak memory 199948 kb
Host smart-95b7d352-fa29-414b-a52f-f15ec69c7429
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772341982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1772341982
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2672481807
Short name T157
Test name
Test status
Simulation time 378366890 ps
CPU time 10.56 seconds
Started Jul 23 06:21:39 PM PDT 24
Finished Jul 23 06:21:50 PM PDT 24
Peak memory 199688 kb
Host smart-c0b7e71a-cdd8-4d33-ac92-590c4f141f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672481807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2672481807
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1371746816
Short name T233
Test name
Test status
Simulation time 478355891 ps
CPU time 2.3 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:21:40 PM PDT 24
Peak memory 199688 kb
Host smart-ee486eef-9742-4dd0-ad0d-113835c4d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371746816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1371746816
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3717981204
Short name T33
Test name
Test status
Simulation time 28830235916 ps
CPU time 3876.97 seconds
Started Jul 23 06:21:35 PM PDT 24
Finished Jul 23 07:26:13 PM PDT 24
Peak memory 845940 kb
Host smart-cba68ac0-1867-4ea6-9e2a-4a2eabafe194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717981204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3717981204
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.724800545
Short name T323
Test name
Test status
Simulation time 312875017 ps
CPU time 8.65 seconds
Started Jul 23 06:21:37 PM PDT 24
Finished Jul 23 06:21:46 PM PDT 24
Peak memory 199712 kb
Host smart-6c593828-1388-4dec-accf-ff6714fbf165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724800545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.724800545
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4238919726
Short name T338
Test name
Test status
Simulation time 20085693 ps
CPU time 0.59 seconds
Started Jul 23 06:21:46 PM PDT 24
Finished Jul 23 06:21:47 PM PDT 24
Peak memory 195256 kb
Host smart-06dc9647-bee0-4b06-80f6-35e192c636d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238919726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4238919726
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2164191717
Short name T315
Test name
Test status
Simulation time 933600217 ps
CPU time 11.77 seconds
Started Jul 23 06:21:37 PM PDT 24
Finished Jul 23 06:21:49 PM PDT 24
Peak memory 199700 kb
Host smart-e375798e-be30-4a61-825e-53406d7ed191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164191717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2164191717
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1150598682
Short name T225
Test name
Test status
Simulation time 16372674368 ps
CPU time 50.12 seconds
Started Jul 23 06:21:34 PM PDT 24
Finished Jul 23 06:22:25 PM PDT 24
Peak memory 199792 kb
Host smart-c69176b4-341f-4b10-b4d3-ff3898d3d009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150598682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1150598682
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3857672202
Short name T182
Test name
Test status
Simulation time 4222039467 ps
CPU time 768.91 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:34:26 PM PDT 24
Peak memory 700736 kb
Host smart-b4d2ab72-a575-493f-bd2e-a1d716edb709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857672202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3857672202
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2159942081
Short name T433
Test name
Test status
Simulation time 2610586283 ps
CPU time 159.05 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:24:16 PM PDT 24
Peak memory 199772 kb
Host smart-964279ef-1d8a-493c-8352-8d02dffe84bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159942081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2159942081
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.953237456
Short name T490
Test name
Test status
Simulation time 6485695065 ps
CPU time 22.88 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:22:00 PM PDT 24
Peak memory 199784 kb
Host smart-18ac5d6f-ba08-41c3-886c-3937749ac03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953237456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.953237456
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1118528608
Short name T232
Test name
Test status
Simulation time 1191878344 ps
CPU time 16.1 seconds
Started Jul 23 06:21:35 PM PDT 24
Finished Jul 23 06:21:52 PM PDT 24
Peak memory 199724 kb
Host smart-ccfac036-8b7d-4827-bb5e-d900b1cc4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118528608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1118528608
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2919000691
Short name T474
Test name
Test status
Simulation time 8580493971 ps
CPU time 27.58 seconds
Started Jul 23 06:21:36 PM PDT 24
Finished Jul 23 06:22:04 PM PDT 24
Peak memory 199780 kb
Host smart-0ffc6d98-8734-4f35-8f74-c74ba4e1e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919000691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2919000691
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.548758744
Short name T173
Test name
Test status
Simulation time 13281020 ps
CPU time 0.6 seconds
Started Jul 23 06:21:42 PM PDT 24
Finished Jul 23 06:21:44 PM PDT 24
Peak memory 195688 kb
Host smart-7b85f858-8480-40a1-a4ac-ccd080118704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548758744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.548758744
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3164800126
Short name T48
Test name
Test status
Simulation time 1704231311 ps
CPU time 104.49 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:23:28 PM PDT 24
Peak memory 199676 kb
Host smart-93b3044d-0b1c-4960-87d5-2e63b26069d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164800126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3164800126
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2092708088
Short name T347
Test name
Test status
Simulation time 1263053135 ps
CPU time 33.17 seconds
Started Jul 23 06:21:44 PM PDT 24
Finished Jul 23 06:22:18 PM PDT 24
Peak memory 199772 kb
Host smart-188247ce-932d-47c4-8b68-caf4d5612f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092708088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2092708088
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3324449321
Short name T248
Test name
Test status
Simulation time 92676127 ps
CPU time 6.13 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:21:50 PM PDT 24
Peak memory 199788 kb
Host smart-9ad0fa7e-9699-4a77-a733-97a5c5f356e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324449321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3324449321
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3348005335
Short name T287
Test name
Test status
Simulation time 42177007372 ps
CPU time 188.43 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 199756 kb
Host smart-2e8774bf-ec0f-423a-9a6e-3ed4e95cf46d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348005335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3348005335
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2402618316
Short name T220
Test name
Test status
Simulation time 22035538660 ps
CPU time 35.8 seconds
Started Jul 23 06:21:45 PM PDT 24
Finished Jul 23 06:22:22 PM PDT 24
Peak memory 199876 kb
Host smart-fb42565d-3308-431d-8929-6b496c8b8309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402618316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2402618316
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2870700161
Short name T152
Test name
Test status
Simulation time 5541286988 ps
CPU time 13.25 seconds
Started Jul 23 06:21:42 PM PDT 24
Finished Jul 23 06:21:56 PM PDT 24
Peak memory 199784 kb
Host smart-0359b0e6-51f8-44af-9dff-384257cb2962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870700161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2870700161
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2755358919
Short name T425
Test name
Test status
Simulation time 570250083154 ps
CPU time 2201.07 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:58:25 PM PDT 24
Peak memory 768368 kb
Host smart-6ae0d1fd-245a-4caa-baab-52b512f757c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755358919 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2755358919
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2617182856
Short name T119
Test name
Test status
Simulation time 1765153765 ps
CPU time 93.26 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:23:17 PM PDT 24
Peak memory 199760 kb
Host smart-a4575d6e-727a-4bf6-957e-095f14fe62bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617182856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2617182856
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2752897948
Short name T397
Test name
Test status
Simulation time 43721164 ps
CPU time 0.61 seconds
Started Jul 23 06:21:44 PM PDT 24
Finished Jul 23 06:21:46 PM PDT 24
Peak memory 196416 kb
Host smart-d7af5fa2-184f-431a-be6f-ba9d7bfd84af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752897948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2752897948
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1571615636
Short name T509
Test name
Test status
Simulation time 837330507 ps
CPU time 12.96 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:21:57 PM PDT 24
Peak memory 199704 kb
Host smart-eda01225-d958-4d60-a319-da31bb1ea09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571615636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1571615636
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1120165522
Short name T140
Test name
Test status
Simulation time 1154961903 ps
CPU time 64.71 seconds
Started Jul 23 06:21:42 PM PDT 24
Finished Jul 23 06:22:48 PM PDT 24
Peak memory 199708 kb
Host smart-edb5e997-1ac6-4eea-abd7-061889f1f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120165522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1120165522
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1149048426
Short name T223
Test name
Test status
Simulation time 22221317672 ps
CPU time 549.81 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:30:54 PM PDT 24
Peak memory 672560 kb
Host smart-6d525750-fb73-4029-a93a-fda6569f816c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149048426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1149048426
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.4192101547
Short name T96
Test name
Test status
Simulation time 15288803384 ps
CPU time 186.98 seconds
Started Jul 23 06:21:42 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 199748 kb
Host smart-9983c8b5-4291-48b0-887b-b11335a5d4c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192101547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.4192101547
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.356551638
Short name T511
Test name
Test status
Simulation time 9709760922 ps
CPU time 177.97 seconds
Started Jul 23 06:21:42 PM PDT 24
Finished Jul 23 06:24:41 PM PDT 24
Peak memory 208000 kb
Host smart-8cb53208-7a0c-400d-8c26-1756f4c2dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356551638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.356551638
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1579474696
Short name T210
Test name
Test status
Simulation time 104441155 ps
CPU time 4.42 seconds
Started Jul 23 06:21:44 PM PDT 24
Finished Jul 23 06:21:49 PM PDT 24
Peak memory 199724 kb
Host smart-7edce791-8770-4e5f-a781-4c577900701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579474696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1579474696
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3573286744
Short name T83
Test name
Test status
Simulation time 138975330258 ps
CPU time 2881.52 seconds
Started Jul 23 06:21:44 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 784732 kb
Host smart-bba7e64e-703d-4514-a03c-8fdfa9facb5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573286744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3573286744
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1913591529
Short name T181
Test name
Test status
Simulation time 28156235923 ps
CPU time 121.13 seconds
Started Jul 23 06:21:46 PM PDT 24
Finished Jul 23 06:23:47 PM PDT 24
Peak memory 199668 kb
Host smart-9e46b5ed-4356-49df-a403-3e5e521d3b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913591529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1913591529
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4100395703
Short name T177
Test name
Test status
Simulation time 20264528 ps
CPU time 0.59 seconds
Started Jul 23 06:21:51 PM PDT 24
Finished Jul 23 06:21:53 PM PDT 24
Peak memory 195364 kb
Host smart-ac07083a-9902-4a4d-90f8-267bffb7e0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100395703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4100395703
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2869568235
Short name T372
Test name
Test status
Simulation time 4260976312 ps
CPU time 17.55 seconds
Started Jul 23 06:21:49 PM PDT 24
Finished Jul 23 06:22:09 PM PDT 24
Peak memory 199700 kb
Host smart-6610bc20-dd4b-4349-8e2d-5cf47617ef3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869568235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2869568235
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1156432348
Short name T499
Test name
Test status
Simulation time 17953317939 ps
CPU time 56.61 seconds
Started Jul 23 06:21:50 PM PDT 24
Finished Jul 23 06:22:48 PM PDT 24
Peak memory 199736 kb
Host smart-a103fdd8-f5ba-44cc-b344-e4b77c3aa28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156432348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1156432348
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1086571605
Short name T274
Test name
Test status
Simulation time 61127691 ps
CPU time 3.81 seconds
Started Jul 23 06:21:50 PM PDT 24
Finished Jul 23 06:21:55 PM PDT 24
Peak memory 199568 kb
Host smart-786e0d83-225a-4d45-b9be-e85698e996f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086571605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1086571605
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4155451075
Short name T507
Test name
Test status
Simulation time 11943171877 ps
CPU time 146.08 seconds
Started Jul 23 06:21:52 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 199768 kb
Host smart-03b456b6-0d8f-4aca-a099-6051fcf9c635
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155451075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4155451075
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1569860234
Short name T289
Test name
Test status
Simulation time 802704094 ps
CPU time 14.57 seconds
Started Jul 23 06:21:44 PM PDT 24
Finished Jul 23 06:21:59 PM PDT 24
Peak memory 199640 kb
Host smart-29c6113b-4bff-48ae-9083-7b2ad4c7709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569860234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1569860234
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1066127943
Short name T378
Test name
Test status
Simulation time 1680615800 ps
CPU time 14.03 seconds
Started Jul 23 06:21:43 PM PDT 24
Finished Jul 23 06:21:58 PM PDT 24
Peak memory 199700 kb
Host smart-dc9571f6-eef8-45c7-bc84-1dc66da123c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066127943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1066127943
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1496177115
Short name T298
Test name
Test status
Simulation time 8300390820 ps
CPU time 76.27 seconds
Started Jul 23 06:21:55 PM PDT 24
Finished Jul 23 06:23:16 PM PDT 24
Peak memory 199788 kb
Host smart-642369cf-c61b-4bbb-b728-c8cea1a03d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496177115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1496177115
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3558383193
Short name T46
Test name
Test status
Simulation time 11432990 ps
CPU time 0.57 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:11 PM PDT 24
Peak memory 194616 kb
Host smart-f3106542-f3bd-4fec-bd91-8de3f13e4cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558383193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3558383193
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1486841028
Short name T512
Test name
Test status
Simulation time 1581097197 ps
CPU time 46.08 seconds
Started Jul 23 06:21:52 PM PDT 24
Finished Jul 23 06:22:41 PM PDT 24
Peak memory 199728 kb
Host smart-4dd98fd7-257b-4853-8243-915b8a57e96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486841028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1486841028
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.550455823
Short name T424
Test name
Test status
Simulation time 3146135664 ps
CPU time 56.46 seconds
Started Jul 23 06:21:51 PM PDT 24
Finished Jul 23 06:22:49 PM PDT 24
Peak memory 199740 kb
Host smart-f706340c-2b44-45ba-a3a2-33d27d85a0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550455823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.550455823
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2313015410
Short name T281
Test name
Test status
Simulation time 4274336827 ps
CPU time 707.3 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:33:58 PM PDT 24
Peak memory 705216 kb
Host smart-b0808c37-74e7-411e-a00f-19bb4466ba92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313015410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2313015410
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1734617076
Short name T355
Test name
Test status
Simulation time 4445104968 ps
CPU time 43.61 seconds
Started Jul 23 06:21:52 PM PDT 24
Finished Jul 23 06:22:38 PM PDT 24
Peak memory 199740 kb
Host smart-1912e438-4e58-4fa8-b0d7-6160b7cb3890
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734617076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1734617076
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1397684987
Short name T489
Test name
Test status
Simulation time 548163296 ps
CPU time 8.04 seconds
Started Jul 23 06:21:54 PM PDT 24
Finished Jul 23 06:22:06 PM PDT 24
Peak memory 199708 kb
Host smart-5a21c815-b89b-4492-86bf-0f9be16ac8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397684987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1397684987
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1187327080
Short name T202
Test name
Test status
Simulation time 286067402 ps
CPU time 3.97 seconds
Started Jul 23 06:21:52 PM PDT 24
Finished Jul 23 06:21:58 PM PDT 24
Peak memory 199768 kb
Host smart-7b64d708-a4ea-43e4-ad00-26a710b49843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187327080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1187327080
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1664177593
Short name T85
Test name
Test status
Simulation time 114948767387 ps
CPU time 856.45 seconds
Started Jul 23 06:21:50 PM PDT 24
Finished Jul 23 06:36:08 PM PDT 24
Peak memory 665072 kb
Host smart-dd076f93-f273-45f0-9cd1-6885e094b95f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664177593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1664177593
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1591390565
Short name T394
Test name
Test status
Simulation time 23998645818 ps
CPU time 79.99 seconds
Started Jul 23 06:21:54 PM PDT 24
Finished Jul 23 06:23:18 PM PDT 24
Peak memory 199820 kb
Host smart-d45d763b-f7ea-4383-a3b3-e35fffb325c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591390565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1591390565
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4177289584
Short name T449
Test name
Test status
Simulation time 19501679 ps
CPU time 0.61 seconds
Started Jul 23 06:21:59 PM PDT 24
Finished Jul 23 06:22:13 PM PDT 24
Peak memory 195724 kb
Host smart-27d705b7-b42c-4a8a-9611-a75bbc6c13c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177289584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4177289584
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1205959232
Short name T227
Test name
Test status
Simulation time 1209732245 ps
CPU time 70.71 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:23:20 PM PDT 24
Peak memory 199604 kb
Host smart-f73f8072-a14d-408d-81ff-17af23a24e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1205959232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1205959232
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1232087597
Short name T316
Test name
Test status
Simulation time 2576885536 ps
CPU time 32.57 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:43 PM PDT 24
Peak memory 199768 kb
Host smart-ea6705cb-eabb-4bcf-9f40-ed50002177af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232087597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1232087597
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1153755308
Short name T400
Test name
Test status
Simulation time 2660014549 ps
CPU time 134.67 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:24:21 PM PDT 24
Peak memory 591108 kb
Host smart-0e7c371a-69df-472e-afdf-cb372b6e46fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153755308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1153755308
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.829980916
Short name T477
Test name
Test status
Simulation time 10286337502 ps
CPU time 184.52 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:25:11 PM PDT 24
Peak memory 199768 kb
Host smart-be75ea23-a4c0-451e-b152-e6e34122707d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829980916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.829980916
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3966153491
Short name T483
Test name
Test status
Simulation time 4729248046 ps
CPU time 128.02 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:24:19 PM PDT 24
Peak memory 199760 kb
Host smart-13f46b7b-a122-4e89-8150-9df7a06c1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966153491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3966153491
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1718937432
Short name T445
Test name
Test status
Simulation time 330962291 ps
CPU time 7.97 seconds
Started Jul 23 06:21:59 PM PDT 24
Finished Jul 23 06:22:20 PM PDT 24
Peak memory 199716 kb
Host smart-d1803634-73bf-4aa0-997b-74aa856ad9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718937432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1718937432
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2435996522
Short name T145
Test name
Test status
Simulation time 111544458475 ps
CPU time 3453.98 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 07:19:40 PM PDT 24
Peak memory 757248 kb
Host smart-b9b73614-bbd7-4614-8ec5-2ece74c43a9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435996522 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2435996522
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2359789453
Short name T18
Test name
Test status
Simulation time 10005452997 ps
CPU time 68.27 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:23:17 PM PDT 24
Peak memory 199784 kb
Host smart-7f3a9f86-f626-4170-967e-93d73667191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359789453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2359789453
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2415967753
Short name T253
Test name
Test status
Simulation time 14677431 ps
CPU time 0.62 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:20:21 PM PDT 24
Peak memory 195384 kb
Host smart-963b3796-9820-4089-a07a-a2a0e215aa46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415967753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2415967753
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3299003782
Short name T502
Test name
Test status
Simulation time 5537233528 ps
CPU time 71.65 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 06:21:39 PM PDT 24
Peak memory 199892 kb
Host smart-71163b2b-5d6a-4e49-9a01-229a2b66b098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299003782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3299003782
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1587100676
Short name T219
Test name
Test status
Simulation time 6766190642 ps
CPU time 30.23 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:20:59 PM PDT 24
Peak memory 199776 kb
Host smart-cf741877-a644-4823-bb19-f5153295bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587100676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1587100676
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4201260985
Short name T515
Test name
Test status
Simulation time 2095447191 ps
CPU time 386.69 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:26:49 PM PDT 24
Peak memory 643108 kb
Host smart-26df80e5-3fab-49af-8be3-7e971c286539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201260985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4201260985
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2238135872
Short name T442
Test name
Test status
Simulation time 6178957983 ps
CPU time 166.18 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:23:06 PM PDT 24
Peak memory 199764 kb
Host smart-55d32cb6-e858-4701-a39e-9ce5e5e6158f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238135872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2238135872
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3200700689
Short name T172
Test name
Test status
Simulation time 3513878841 ps
CPU time 28.97 seconds
Started Jul 23 06:20:18 PM PDT 24
Finished Jul 23 06:20:47 PM PDT 24
Peak memory 199792 kb
Host smart-2d596f30-5836-49f6-a52c-5d20b1258064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200700689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3200700689
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4059624314
Short name T56
Test name
Test status
Simulation time 36739777 ps
CPU time 0.82 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:20:24 PM PDT 24
Peak memory 218420 kb
Host smart-a75c6a3e-367c-45b0-b63e-c956923a8291
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059624314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4059624314
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.813526872
Short name T359
Test name
Test status
Simulation time 2219666511 ps
CPU time 14.78 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:37 PM PDT 24
Peak memory 199780 kb
Host smart-f841706e-f27b-41b0-807a-c40e5507a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813526872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.813526872
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.119304585
Short name T215
Test name
Test status
Simulation time 1477736991 ps
CPU time 83.76 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:21:45 PM PDT 24
Peak memory 199748 kb
Host smart-1e43fa48-0de8-418d-aa0f-2b738fc798f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119304585 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.119304585
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3498225208
Short name T91
Test name
Test status
Simulation time 17239021133 ps
CPU time 70.48 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:21:30 PM PDT 24
Peak memory 199816 kb
Host smart-e59a348b-8923-4b96-899a-e8b122e095d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3498225208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3498225208
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2188817085
Short name T369
Test name
Test status
Simulation time 8915433372 ps
CPU time 91.99 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 06:21:59 PM PDT 24
Peak memory 199764 kb
Host smart-afb22212-d0eb-48f9-ad94-c047290d83fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2188817085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2188817085
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3755541230
Short name T308
Test name
Test status
Simulation time 12732497300 ps
CPU time 110.72 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:22:19 PM PDT 24
Peak memory 199712 kb
Host smart-602c88b1-e4c4-44f1-bbe7-ac1835345033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3755541230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3755541230
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1378334352
Short name T319
Test name
Test status
Simulation time 39524778008 ps
CPU time 544.41 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:29:25 PM PDT 24
Peak memory 199752 kb
Host smart-298404ea-da97-47fa-a8e1-f9ded7fa5f3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1378334352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1378334352
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1057903696
Short name T153
Test name
Test status
Simulation time 472247243807 ps
CPU time 2184.57 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:56:46 PM PDT 24
Peak memory 209156 kb
Host smart-fdff53ff-f5a3-44f2-b72d-c226d861bfd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1057903696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1057903696
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2524289077
Short name T245
Test name
Test status
Simulation time 743408861130 ps
CPU time 2492.3 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 07:01:53 PM PDT 24
Peak memory 215412 kb
Host smart-86962a37-7610-4e99-b0de-80116eeff059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2524289077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2524289077
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1656999434
Short name T90
Test name
Test status
Simulation time 5780364826 ps
CPU time 64.87 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:21:26 PM PDT 24
Peak memory 199704 kb
Host smart-be1b2662-f881-416a-b56a-3d7b529f7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656999434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1656999434
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1793323004
Short name T473
Test name
Test status
Simulation time 34038271 ps
CPU time 0.58 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:12 PM PDT 24
Peak memory 194684 kb
Host smart-9dd34f21-1170-400c-bb58-b9a26b1757f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793323004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1793323004
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.916569987
Short name T187
Test name
Test status
Simulation time 1267141449 ps
CPU time 71.21 seconds
Started Jul 23 06:21:56 PM PDT 24
Finished Jul 23 06:23:15 PM PDT 24
Peak memory 199720 kb
Host smart-702c392c-f14d-4795-905a-6b71a30834e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916569987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.916569987
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2986109388
Short name T235
Test name
Test status
Simulation time 7033950664 ps
CPU time 24.12 seconds
Started Jul 23 06:21:59 PM PDT 24
Finished Jul 23 06:22:37 PM PDT 24
Peak memory 199768 kb
Host smart-15a6f7da-44a8-4457-a6a3-a109cf8d8db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986109388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2986109388
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1859068819
Short name T139
Test name
Test status
Simulation time 5442438198 ps
CPU time 858.28 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:36:25 PM PDT 24
Peak memory 738644 kb
Host smart-5316210b-cbc6-4c33-bcb6-6efdc5163cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859068819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1859068819
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2702728530
Short name T40
Test name
Test status
Simulation time 3165627190 ps
CPU time 163.49 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 199764 kb
Host smart-33b3f8f1-76c4-45c1-84ea-300c0051a6ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702728530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2702728530
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.195756430
Short name T380
Test name
Test status
Simulation time 6683398404 ps
CPU time 121.7 seconds
Started Jul 23 06:21:56 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 200016 kb
Host smart-ef299424-8fb5-4782-8afc-ed532bd15b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195756430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.195756430
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2115057978
Short name T514
Test name
Test status
Simulation time 45501155 ps
CPU time 0.7 seconds
Started Jul 23 06:22:00 PM PDT 24
Finished Jul 23 06:22:14 PM PDT 24
Peak memory 196264 kb
Host smart-d959bae3-d3fb-4889-be00-0967fdbef346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115057978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2115057978
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1531113230
Short name T201
Test name
Test status
Simulation time 574186176 ps
CPU time 2.97 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:14 PM PDT 24
Peak memory 199616 kb
Host smart-a3e60d51-e332-49ac-904b-2848408cf0ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531113230 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1531113230
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4162967658
Short name T470
Test name
Test status
Simulation time 1492522636 ps
CPU time 61.42 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:23:08 PM PDT 24
Peak memory 199768 kb
Host smart-24802e5f-196f-4375-bd47-0bfcd15a6791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162967658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4162967658
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3303790516
Short name T39
Test name
Test status
Simulation time 31314066 ps
CPU time 0.58 seconds
Started Jul 23 06:22:00 PM PDT 24
Finished Jul 23 06:22:13 PM PDT 24
Peak memory 195712 kb
Host smart-34ab5c1d-6ba5-42ba-be6a-c6903e5f1165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303790516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3303790516
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2781301133
Short name T310
Test name
Test status
Simulation time 1188590457 ps
CPU time 22.57 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:32 PM PDT 24
Peak memory 199604 kb
Host smart-c3b2d575-e293-40ac-96b1-4b64bbbf96d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781301133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2781301133
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4007694392
Short name T257
Test name
Test status
Simulation time 240988498 ps
CPU time 1.68 seconds
Started Jul 23 06:21:59 PM PDT 24
Finished Jul 23 06:22:14 PM PDT 24
Peak memory 199696 kb
Host smart-9f667cf4-1c62-4709-8c17-8eda5bbaba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007694392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4007694392
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1037134710
Short name T147
Test name
Test status
Simulation time 4663297715 ps
CPU time 896.52 seconds
Started Jul 23 06:22:01 PM PDT 24
Finished Jul 23 06:37:12 PM PDT 24
Peak memory 692624 kb
Host smart-18b88a69-3ca0-406b-90aa-8fc3960dc374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037134710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1037134710
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.4026472461
Short name T522
Test name
Test status
Simulation time 3194512004 ps
CPU time 179.29 seconds
Started Jul 23 06:22:00 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 199764 kb
Host smart-c94871ec-f3d8-4d7b-91eb-7f0bbf856ff9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026472461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4026472461
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3210656299
Short name T93
Test name
Test status
Simulation time 243160823 ps
CPU time 12.8 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:22:21 PM PDT 24
Peak memory 199876 kb
Host smart-908f42e0-e1df-455c-9945-268d7a80a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210656299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3210656299
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4027730348
Short name T211
Test name
Test status
Simulation time 683516705 ps
CPU time 8.55 seconds
Started Jul 23 06:21:57 PM PDT 24
Finished Jul 23 06:22:15 PM PDT 24
Peak memory 199672 kb
Host smart-215cc00d-68cf-4abb-b7af-9be63ac0b8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027730348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4027730348
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3039490895
Short name T495
Test name
Test status
Simulation time 344810240600 ps
CPU time 3516.08 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 07:20:47 PM PDT 24
Peak memory 795352 kb
Host smart-56bf2a6d-caa4-45af-802b-2cc72b72a225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039490895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3039490895
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2282485417
Short name T180
Test name
Test status
Simulation time 6009347609 ps
CPU time 110.62 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:24:01 PM PDT 24
Peak memory 199752 kb
Host smart-7ca1a07f-86a9-474e-9088-4de1fa9cd30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282485417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2282485417
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.839896425
Short name T484
Test name
Test status
Simulation time 29522558 ps
CPU time 0.58 seconds
Started Jul 23 06:22:08 PM PDT 24
Finished Jul 23 06:22:23 PM PDT 24
Peak memory 195712 kb
Host smart-e17db71b-5c20-4995-b327-225839ad968a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839896425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.839896425
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1886606930
Short name T185
Test name
Test status
Simulation time 838948157 ps
CPU time 29.14 seconds
Started Jul 23 06:21:58 PM PDT 24
Finished Jul 23 06:22:38 PM PDT 24
Peak memory 199688 kb
Host smart-121a165d-4695-4fae-bd2a-de6561cdfd67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886606930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1886606930
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1906255966
Short name T322
Test name
Test status
Simulation time 8925305911 ps
CPU time 31.11 seconds
Started Jul 23 06:22:06 PM PDT 24
Finished Jul 23 06:22:53 PM PDT 24
Peak memory 199740 kb
Host smart-addb764c-6965-4051-a7f8-c9512baa3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906255966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1906255966
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2892716638
Short name T349
Test name
Test status
Simulation time 9988791717 ps
CPU time 1195.98 seconds
Started Jul 23 06:22:07 PM PDT 24
Finished Jul 23 06:42:18 PM PDT 24
Peak memory 752220 kb
Host smart-b339604e-59aa-41f6-86d4-e353bf99ba84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892716638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2892716638
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.648896220
Short name T472
Test name
Test status
Simulation time 742589354 ps
CPU time 10.26 seconds
Started Jul 23 06:22:05 PM PDT 24
Finished Jul 23 06:22:31 PM PDT 24
Peak memory 199552 kb
Host smart-f6ec3d11-f7e3-4cb4-a68c-e1440c554169
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648896220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.648896220
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2375886100
Short name T421
Test name
Test status
Simulation time 1661940372 ps
CPU time 78.96 seconds
Started Jul 23 06:22:00 PM PDT 24
Finished Jul 23 06:23:33 PM PDT 24
Peak memory 199708 kb
Host smart-a2a6464a-2ea0-4f35-bcbd-032384e24206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375886100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2375886100
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3711101888
Short name T282
Test name
Test status
Simulation time 3633320070 ps
CPU time 13.06 seconds
Started Jul 23 06:22:00 PM PDT 24
Finished Jul 23 06:22:26 PM PDT 24
Peak memory 199780 kb
Host smart-dc86a3e3-dc96-4f7d-966e-d511f818fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711101888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3711101888
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2715232514
Short name T87
Test name
Test status
Simulation time 120591192843 ps
CPU time 559.15 seconds
Started Jul 23 06:22:09 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 199760 kb
Host smart-94989260-0a5c-4224-932a-08f9786fd8f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715232514 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2715232514
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1213271147
Short name T510
Test name
Test status
Simulation time 127008075 ps
CPU time 4.07 seconds
Started Jul 23 06:22:06 PM PDT 24
Finished Jul 23 06:22:25 PM PDT 24
Peak memory 199672 kb
Host smart-4236bdb8-f887-4809-9cdc-f05fd8ed4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213271147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1213271147
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2770420707
Short name T518
Test name
Test status
Simulation time 556733529 ps
CPU time 30.99 seconds
Started Jul 23 06:22:06 PM PDT 24
Finished Jul 23 06:22:52 PM PDT 24
Peak memory 199708 kb
Host smart-5dc9dae4-6a38-48be-a960-4a9008e3088d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770420707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2770420707
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3843420018
Short name T486
Test name
Test status
Simulation time 8457327418 ps
CPU time 33.39 seconds
Started Jul 23 06:22:09 PM PDT 24
Finished Jul 23 06:22:57 PM PDT 24
Peak memory 199808 kb
Host smart-517c8609-26d3-49b1-94ea-4c897fb7ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843420018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3843420018
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1359519843
Short name T383
Test name
Test status
Simulation time 2639155149 ps
CPU time 412.72 seconds
Started Jul 23 06:22:07 PM PDT 24
Finished Jul 23 06:29:15 PM PDT 24
Peak memory 677152 kb
Host smart-154ba8d6-a319-4c94-9a63-7f8761ec9588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359519843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1359519843
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4247368208
Short name T252
Test name
Test status
Simulation time 7070992065 ps
CPU time 121 seconds
Started Jul 23 06:22:06 PM PDT 24
Finished Jul 23 06:24:23 PM PDT 24
Peak memory 199768 kb
Host smart-963b8647-1a0e-4ecd-a013-9135594a53ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247368208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4247368208
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_smoke.1780051894
Short name T240
Test name
Test status
Simulation time 299805019 ps
CPU time 4.23 seconds
Started Jul 23 06:22:07 PM PDT 24
Finished Jul 23 06:22:26 PM PDT 24
Peak memory 199708 kb
Host smart-ab637446-948d-4ee0-98cd-cabb5ef0eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780051894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1780051894
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3335654807
Short name T86
Test name
Test status
Simulation time 1561790718 ps
CPU time 67.61 seconds
Started Jul 23 06:22:08 PM PDT 24
Finished Jul 23 06:23:30 PM PDT 24
Peak memory 199664 kb
Host smart-07007dbf-4b7c-4455-96a4-bb840180ff6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335654807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3335654807
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1332232426
Short name T341
Test name
Test status
Simulation time 2856042028 ps
CPU time 39.63 seconds
Started Jul 23 06:22:07 PM PDT 24
Finished Jul 23 06:23:02 PM PDT 24
Peak memory 199760 kb
Host smart-6b3cf45f-e25a-4c51-ad68-1d77abd0a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332232426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1332232426
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1188071879
Short name T299
Test name
Test status
Simulation time 34720217 ps
CPU time 0.61 seconds
Started Jul 23 06:22:17 PM PDT 24
Finished Jul 23 06:22:33 PM PDT 24
Peak memory 195704 kb
Host smart-11d37636-f959-47eb-876c-cdf4139bb33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188071879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1188071879
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2648325366
Short name T209
Test name
Test status
Simulation time 1000023013 ps
CPU time 52.98 seconds
Started Jul 23 06:22:15 PM PDT 24
Finished Jul 23 06:23:24 PM PDT 24
Peak memory 199688 kb
Host smart-609be42f-99d1-4df3-8e56-1056ff1030c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648325366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2648325366
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.275917546
Short name T142
Test name
Test status
Simulation time 97124190 ps
CPU time 5.05 seconds
Started Jul 23 06:22:19 PM PDT 24
Finished Jul 23 06:22:39 PM PDT 24
Peak memory 199752 kb
Host smart-ddd1870d-99ee-4fff-bdea-5de0d13b264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275917546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.275917546
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1452675914
Short name T393
Test name
Test status
Simulation time 20569053 ps
CPU time 1.02 seconds
Started Jul 23 06:22:13 PM PDT 24
Finished Jul 23 06:22:30 PM PDT 24
Peak memory 207816 kb
Host smart-a7bd2853-8287-4bba-a968-15614e258daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452675914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1452675914
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3884145646
Short name T212
Test name
Test status
Simulation time 24656709358 ps
CPU time 160.6 seconds
Started Jul 23 06:22:20 PM PDT 24
Finished Jul 23 06:25:15 PM PDT 24
Peak memory 199816 kb
Host smart-c3f619da-6b0c-4509-8554-b57b472420aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884145646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3884145646
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2145960591
Short name T271
Test name
Test status
Simulation time 668009715 ps
CPU time 11.74 seconds
Started Jul 23 06:22:22 PM PDT 24
Finished Jul 23 06:22:48 PM PDT 24
Peak memory 199708 kb
Host smart-f283b7cf-ed2a-4dd2-8240-d8f414f54a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145960591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2145960591
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3256542327
Short name T260
Test name
Test status
Simulation time 247394640 ps
CPU time 10.73 seconds
Started Jul 23 06:22:07 PM PDT 24
Finished Jul 23 06:22:33 PM PDT 24
Peak memory 199716 kb
Host smart-6aa7a79d-5808-4a1a-b962-f33d40199592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256542327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3256542327
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2847268242
Short name T516
Test name
Test status
Simulation time 60624980051 ps
CPU time 2754.86 seconds
Started Jul 23 06:22:14 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 764532 kb
Host smart-46db540c-3f7d-4c51-a482-42ab2322f06d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847268242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2847268242
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3922981398
Short name T402
Test name
Test status
Simulation time 4014407421 ps
CPU time 71.07 seconds
Started Jul 23 06:22:18 PM PDT 24
Finished Jul 23 06:23:45 PM PDT 24
Peak memory 199764 kb
Host smart-f1bbf69c-448e-4fe8-8d18-92b3cfb3f858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922981398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3922981398
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4098747417
Short name T159
Test name
Test status
Simulation time 14070233 ps
CPU time 0.63 seconds
Started Jul 23 06:22:14 PM PDT 24
Finished Jul 23 06:22:31 PM PDT 24
Peak memory 195704 kb
Host smart-15c4d3ae-dd96-4896-ae26-69ed2496aa2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098747417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4098747417
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2586299628
Short name T361
Test name
Test status
Simulation time 4062723505 ps
CPU time 57.88 seconds
Started Jul 23 06:22:13 PM PDT 24
Finished Jul 23 06:23:26 PM PDT 24
Peak memory 215948 kb
Host smart-1a338a2a-33fb-4d25-b4cf-db217a781235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586299628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2586299628
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3548902231
Short name T346
Test name
Test status
Simulation time 3840346835 ps
CPU time 49.45 seconds
Started Jul 23 06:22:19 PM PDT 24
Finished Jul 23 06:23:24 PM PDT 24
Peak memory 199740 kb
Host smart-3ebf9b46-68a7-4fe4-a134-8240191c713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548902231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3548902231
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1659918795
Short name T155
Test name
Test status
Simulation time 1002554086 ps
CPU time 163.7 seconds
Started Jul 23 06:22:19 PM PDT 24
Finished Jul 23 06:25:18 PM PDT 24
Peak memory 623464 kb
Host smart-194ef4a9-5233-41df-a6dc-7e469a893761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659918795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1659918795
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2045028182
Short name T208
Test name
Test status
Simulation time 611844803 ps
CPU time 10.04 seconds
Started Jul 23 06:22:16 PM PDT 24
Finished Jul 23 06:22:42 PM PDT 24
Peak memory 199696 kb
Host smart-1a324db6-1726-40a8-8a24-33471616932d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045028182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2045028182
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.165252368
Short name T301
Test name
Test status
Simulation time 23026142316 ps
CPU time 68.19 seconds
Started Jul 23 06:22:18 PM PDT 24
Finished Jul 23 06:23:42 PM PDT 24
Peak memory 215924 kb
Host smart-1f5f258a-352d-44cd-868c-7fb4fa167fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165252368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.165252368
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2589512545
Short name T399
Test name
Test status
Simulation time 1478093888 ps
CPU time 9.5 seconds
Started Jul 23 06:22:15 PM PDT 24
Finished Jul 23 06:22:41 PM PDT 24
Peak memory 199680 kb
Host smart-ab29d1f5-2766-4f3e-a5dd-62aa4473666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589512545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2589512545
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2250324946
Short name T326
Test name
Test status
Simulation time 4854987582 ps
CPU time 312.68 seconds
Started Jul 23 06:22:19 PM PDT 24
Finished Jul 23 06:27:47 PM PDT 24
Peak memory 482288 kb
Host smart-3db944b0-88f7-4923-bf49-2678f9917ad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250324946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2250324946
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3267503508
Short name T364
Test name
Test status
Simulation time 6917503655 ps
CPU time 87.23 seconds
Started Jul 23 06:22:18 PM PDT 24
Finished Jul 23 06:24:01 PM PDT 24
Peak memory 199792 kb
Host smart-b7f2b53a-18ac-452b-87d3-e0b1a706a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267503508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3267503508
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2327940403
Short name T265
Test name
Test status
Simulation time 25710874 ps
CPU time 0.6 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:22:42 PM PDT 24
Peak memory 195728 kb
Host smart-bf3bd677-152b-46cc-9441-5bb42bc900c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327940403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2327940403
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3576132446
Short name T357
Test name
Test status
Simulation time 2765840107 ps
CPU time 29.98 seconds
Started Jul 23 06:22:15 PM PDT 24
Finished Jul 23 06:23:00 PM PDT 24
Peak memory 199756 kb
Host smart-be143f30-42db-419f-a5e0-738c9570d1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576132446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3576132446
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.766775894
Short name T53
Test name
Test status
Simulation time 9926506886 ps
CPU time 66.79 seconds
Started Jul 23 06:22:24 PM PDT 24
Finished Jul 23 06:23:45 PM PDT 24
Peak memory 208120 kb
Host smart-2559d68b-dcf0-469a-8d0c-c996283ca6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766775894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.766775894
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.586172137
Short name T460
Test name
Test status
Simulation time 21821996529 ps
CPU time 909.88 seconds
Started Jul 23 06:22:16 PM PDT 24
Finished Jul 23 06:37:41 PM PDT 24
Peak memory 673236 kb
Host smart-b5e65129-b1ae-438b-979e-b7620baa4d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586172137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.586172137
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1108215354
Short name T419
Test name
Test status
Simulation time 1363348686 ps
CPU time 26.07 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:23:07 PM PDT 24
Peak memory 199704 kb
Host smart-388f90b4-23fe-4d58-b0d8-e7e5be73b636
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108215354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1108215354
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.997597148
Short name T374
Test name
Test status
Simulation time 13003007988 ps
CPU time 117.52 seconds
Started Jul 23 06:22:14 PM PDT 24
Finished Jul 23 06:24:27 PM PDT 24
Peak memory 200076 kb
Host smart-33095786-f79b-401a-87cc-14c794a33eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997597148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.997597148
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.4050279806
Short name T51
Test name
Test status
Simulation time 165752173 ps
CPU time 1.17 seconds
Started Jul 23 06:22:20 PM PDT 24
Finished Jul 23 06:22:36 PM PDT 24
Peak memory 199712 kb
Host smart-6ec738fc-f2b0-47d7-90e1-89b16bfd4f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050279806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4050279806
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1916406027
Short name T84
Test name
Test status
Simulation time 360909411884 ps
CPU time 2657.03 seconds
Started Jul 23 06:22:24 PM PDT 24
Finished Jul 23 07:06:55 PM PDT 24
Peak memory 798404 kb
Host smart-94c108b3-3401-4c9f-a4db-8ee9c4f78fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916406027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1916406027
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2573214196
Short name T356
Test name
Test status
Simulation time 35122385560 ps
CPU time 107.76 seconds
Started Jul 23 06:22:23 PM PDT 24
Finished Jul 23 06:24:25 PM PDT 24
Peak memory 199848 kb
Host smart-5bfeb041-3dc4-40a2-a515-83744cc0a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573214196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2573214196
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3530885687
Short name T454
Test name
Test status
Simulation time 44112537 ps
CPU time 0.6 seconds
Started Jul 23 06:22:26 PM PDT 24
Finished Jul 23 06:22:41 PM PDT 24
Peak memory 196408 kb
Host smart-1e7e69a8-66b5-4c74-8e81-afd4987e27cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530885687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3530885687
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.696006875
Short name T238
Test name
Test status
Simulation time 73525122 ps
CPU time 3.9 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:22:45 PM PDT 24
Peak memory 199644 kb
Host smart-c16dd837-9b53-435d-b198-1c6b496e2d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696006875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.696006875
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1172942208
Short name T332
Test name
Test status
Simulation time 8966545381 ps
CPU time 50.47 seconds
Started Jul 23 06:22:23 PM PDT 24
Finished Jul 23 06:23:28 PM PDT 24
Peak memory 207992 kb
Host smart-d866ee75-43a3-4bbc-973a-6d1c7cc2b4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172942208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1172942208
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2732174135
Short name T478
Test name
Test status
Simulation time 22298612119 ps
CPU time 777.52 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:35:39 PM PDT 24
Peak memory 719440 kb
Host smart-bb763c5b-bc00-4929-9b32-0f91a1939182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732174135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2732174135
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3607983481
Short name T264
Test name
Test status
Simulation time 241766916 ps
CPU time 0.82 seconds
Started Jul 23 06:22:23 PM PDT 24
Finished Jul 23 06:22:38 PM PDT 24
Peak memory 197464 kb
Host smart-2adee641-1922-4a4b-b78a-34249b28fe56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607983481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3607983481
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.373806526
Short name T218
Test name
Test status
Simulation time 19798575446 ps
CPU time 66.99 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 199780 kb
Host smart-994764a1-f78f-4f4b-bba7-7e17d5e1518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373806526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.373806526
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3984502682
Short name T318
Test name
Test status
Simulation time 282886322 ps
CPU time 4 seconds
Started Jul 23 06:22:24 PM PDT 24
Finished Jul 23 06:22:42 PM PDT 24
Peak memory 199652 kb
Host smart-4bb2d791-e24b-4756-bed6-5515128b1ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984502682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3984502682
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3305576927
Short name T28
Test name
Test status
Simulation time 111961021611 ps
CPU time 3283.4 seconds
Started Jul 23 06:22:25 PM PDT 24
Finished Jul 23 07:17:22 PM PDT 24
Peak memory 826440 kb
Host smart-005471f6-04b5-428e-a806-3c9931c19bc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305576927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3305576927
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1004122990
Short name T89
Test name
Test status
Simulation time 11002506086 ps
CPU time 95.97 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:24:17 PM PDT 24
Peak memory 199792 kb
Host smart-21a31388-7902-4764-b848-3759e387b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004122990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1004122990
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4080328211
Short name T387
Test name
Test status
Simulation time 217456971 ps
CPU time 0.59 seconds
Started Jul 23 06:22:35 PM PDT 24
Finished Jul 23 06:22:52 PM PDT 24
Peak memory 195748 kb
Host smart-c78a0b30-5e52-4df3-a2cd-a92b1852fd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080328211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4080328211
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2417932892
Short name T221
Test name
Test status
Simulation time 1668025713 ps
CPU time 48.72 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 199712 kb
Host smart-b0f541ba-5893-4819-82c2-17d8e5be36f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417932892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2417932892
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4033551729
Short name T26
Test name
Test status
Simulation time 295040812 ps
CPU time 13.56 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:23:01 PM PDT 24
Peak memory 199676 kb
Host smart-6e7a3bff-8d8c-479e-a742-805951dcb028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033551729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4033551729
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2614993106
Short name T311
Test name
Test status
Simulation time 30819820326 ps
CPU time 496.46 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 703148 kb
Host smart-f70aafa3-558d-460c-80fa-87cfaa0cafb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614993106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2614993106
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.952639675
Short name T324
Test name
Test status
Simulation time 959275161 ps
CPU time 11.3 seconds
Started Jul 23 06:22:35 PM PDT 24
Finished Jul 23 06:23:02 PM PDT 24
Peak memory 199688 kb
Host smart-c0784902-13d4-4a6f-83c8-f0101336d471
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952639675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.952639675
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4076247212
Short name T171
Test name
Test status
Simulation time 6089286953 ps
CPU time 84.35 seconds
Started Jul 23 06:22:26 PM PDT 24
Finished Jul 23 06:24:05 PM PDT 24
Peak memory 199824 kb
Host smart-b24e12ff-09e4-4e56-9c3b-b7ac5c09ef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076247212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4076247212
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1367924465
Short name T410
Test name
Test status
Simulation time 102527820 ps
CPU time 4.95 seconds
Started Jul 23 06:22:27 PM PDT 24
Finished Jul 23 06:22:46 PM PDT 24
Peak memory 199716 kb
Host smart-41bc7cf6-33ed-4429-b0c8-d08bad45a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367924465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1367924465
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1008368951
Short name T493
Test name
Test status
Simulation time 66824020 ps
CPU time 0.58 seconds
Started Jul 23 06:22:38 PM PDT 24
Finished Jul 23 06:22:55 PM PDT 24
Peak memory 195564 kb
Host smart-017a0da0-1220-4dce-b036-86e8fa46117d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008368951 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1008368951
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3082960892
Short name T95
Test name
Test status
Simulation time 5576074342 ps
CPU time 82.74 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:24:10 PM PDT 24
Peak memory 199832 kb
Host smart-bea8a4a7-76cd-499c-a5fc-2cf4bda9ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082960892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3082960892
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.866633627
Short name T216
Test name
Test status
Simulation time 30109365 ps
CPU time 0.54 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:22:48 PM PDT 24
Peak memory 194696 kb
Host smart-6ec8a14e-48a4-4559-bd63-0232240bcb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866633627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.866633627
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.520002874
Short name T403
Test name
Test status
Simulation time 1124520171 ps
CPU time 64.26 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:23:53 PM PDT 24
Peak memory 199744 kb
Host smart-7b4812b9-24cc-4e90-92fd-291f7684cfdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520002874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.520002874
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2928485912
Short name T443
Test name
Test status
Simulation time 978762195 ps
CPU time 18.13 seconds
Started Jul 23 06:22:36 PM PDT 24
Finished Jul 23 06:23:11 PM PDT 24
Peak memory 199692 kb
Host smart-8eb1bd39-cd11-43cd-aebb-3bbd99965ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928485912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2928485912
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2523224413
Short name T334
Test name
Test status
Simulation time 2405048763 ps
CPU time 436.75 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:30:05 PM PDT 24
Peak memory 665228 kb
Host smart-ddad86cd-5d1e-436b-8abf-1b8778912eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523224413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2523224413
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1183758066
Short name T434
Test name
Test status
Simulation time 13163858826 ps
CPU time 72.23 seconds
Started Jul 23 06:22:36 PM PDT 24
Finished Jul 23 06:24:05 PM PDT 24
Peak memory 199760 kb
Host smart-c73beb2e-c6c3-4a39-9ef9-d6488fdd6170
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183758066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1183758066
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4194984836
Short name T242
Test name
Test status
Simulation time 28510635490 ps
CPU time 97.09 seconds
Started Jul 23 06:22:32 PM PDT 24
Finished Jul 23 06:24:23 PM PDT 24
Peak memory 199800 kb
Host smart-7c379748-b0d0-439a-8487-74054bb593d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194984836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4194984836
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4055909597
Short name T261
Test name
Test status
Simulation time 132540835 ps
CPU time 2.87 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:22:50 PM PDT 24
Peak memory 199584 kb
Host smart-c65af4ff-9bf2-4ddc-8f85-b9c2e6f797b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055909597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4055909597
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1084088978
Short name T363
Test name
Test status
Simulation time 309868784636 ps
CPU time 2144.47 seconds
Started Jul 23 06:22:35 PM PDT 24
Finished Jul 23 06:58:35 PM PDT 24
Peak memory 742676 kb
Host smart-00a322f3-1e69-4a96-8c6b-5d935ccb1653
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084088978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1084088978
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4279676136
Short name T441
Test name
Test status
Simulation time 7256522241 ps
CPU time 16.92 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:23:06 PM PDT 24
Peak memory 199728 kb
Host smart-83c238b4-e9ba-423b-a3e1-d1f08b5b134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279676136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4279676136
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3037328344
Short name T49
Test name
Test status
Simulation time 44706942 ps
CPU time 0.6 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:20:20 PM PDT 24
Peak memory 195388 kb
Host smart-7399e2cb-d2e8-4cf0-b106-fed58df6f786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037328344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3037328344
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2073972125
Short name T12
Test name
Test status
Simulation time 6212212992 ps
CPU time 102.51 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:22:05 PM PDT 24
Peak memory 199780 kb
Host smart-789ac964-bf7d-4f6d-8395-cb252ff8b9a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073972125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2073972125
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1577259965
Short name T285
Test name
Test status
Simulation time 23532327651 ps
CPU time 76.39 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:21:40 PM PDT 24
Peak memory 199844 kb
Host smart-2fb4d244-5115-467c-8b38-ead9cab1825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577259965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1577259965
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.639081250
Short name T168
Test name
Test status
Simulation time 2594200178 ps
CPU time 133.37 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:22:35 PM PDT 24
Peak memory 617708 kb
Host smart-89025fe0-1acd-49b0-804f-cf2e468a5d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639081250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.639081250
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3939267567
Short name T426
Test name
Test status
Simulation time 14269198271 ps
CPU time 105.38 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:22:09 PM PDT 24
Peak memory 199768 kb
Host smart-40a5cb2c-6c86-4833-b012-d62e9730e677
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939267567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3939267567
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4242868069
Short name T292
Test name
Test status
Simulation time 2434711273 ps
CPU time 137.35 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:22:41 PM PDT 24
Peak memory 199768 kb
Host smart-b938a08d-d4c9-47ad-bace-8590ddd5bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242868069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4242868069
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3465876944
Short name T451
Test name
Test status
Simulation time 512105027 ps
CPU time 11.62 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:20:32 PM PDT 24
Peak memory 199688 kb
Host smart-36b08524-e145-48c3-8df9-64cc6c8e2546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465876944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3465876944
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3043532242
Short name T409
Test name
Test status
Simulation time 14995615283 ps
CPU time 1585.66 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:46:48 PM PDT 24
Peak memory 704996 kb
Host smart-a1725779-2f2e-45a6-948d-64c30db85882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043532242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3043532242
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.169898836
Short name T75
Test name
Test status
Simulation time 108004512033 ps
CPU time 1629.63 seconds
Started Jul 23 06:20:23 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 677764 kb
Host smart-31895cf0-1f44-4d48-9d9b-8e0e23eb58dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169898836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.169898836
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3287082080
Short name T2
Test name
Test status
Simulation time 2439064069 ps
CPU time 43.36 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:21:04 PM PDT 24
Peak memory 199820 kb
Host smart-cad7b0d1-f3b6-4584-9285-75996795d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287082080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3287082080
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2446154984
Short name T47
Test name
Test status
Simulation time 33188365 ps
CPU time 0.64 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:20:24 PM PDT 24
Peak memory 195292 kb
Host smart-c16d05eb-748e-4d7c-8501-80f2d5a0c0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446154984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2446154984
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.293153391
Short name T276
Test name
Test status
Simulation time 1286048728 ps
CPU time 75.45 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:21:37 PM PDT 24
Peak memory 199760 kb
Host smart-21421094-77b6-48d4-8ba8-33972362cc75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293153391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.293153391
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1030208012
Short name T149
Test name
Test status
Simulation time 39154915694 ps
CPU time 424.72 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:27:27 PM PDT 24
Peak memory 655768 kb
Host smart-dbe38e20-7fc1-4c0e-8f4b-3ea74b62df95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030208012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1030208012
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.19901087
Short name T165
Test name
Test status
Simulation time 11489182816 ps
CPU time 76.25 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:21:45 PM PDT 24
Peak memory 199760 kb
Host smart-51160673-133d-4dda-a448-efceb6a74a7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19901087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.19901087
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2960317493
Short name T284
Test name
Test status
Simulation time 6582392093 ps
CPU time 115.52 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:22:18 PM PDT 24
Peak memory 199668 kb
Host smart-036a75dd-1d5b-4d27-859f-e502853e7eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960317493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2960317493
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3575057624
Short name T251
Test name
Test status
Simulation time 813641957 ps
CPU time 13.68 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:36 PM PDT 24
Peak memory 199624 kb
Host smart-7a0b32bf-2eb9-4b22-b9db-cc3dd2191fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575057624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3575057624
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.285650072
Short name T20
Test name
Test status
Simulation time 133680442180 ps
CPU time 2860.92 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 07:08:01 PM PDT 24
Peak memory 703624 kb
Host smart-0eb39b72-4b89-4e55-a81e-e5fac3c4b1cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285650072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.285650072
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3883670555
Short name T191
Test name
Test status
Simulation time 1797963636 ps
CPU time 22.36 seconds
Started Jul 23 06:20:23 PM PDT 24
Finished Jul 23 06:20:46 PM PDT 24
Peak memory 199764 kb
Host smart-61066efb-1f5f-4d8d-b0d6-85c5ef5445ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883670555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3883670555
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4265724807
Short name T205
Test name
Test status
Simulation time 43046852 ps
CPU time 0.59 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:23 PM PDT 24
Peak memory 195732 kb
Host smart-1d907b03-5e92-42b7-94e4-bdc0694f7d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265724807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4265724807
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3489859954
Short name T237
Test name
Test status
Simulation time 9136193575 ps
CPU time 102.1 seconds
Started Jul 23 06:20:19 PM PDT 24
Finished Jul 23 06:22:03 PM PDT 24
Peak memory 199760 kb
Host smart-a7bb7a8f-56cf-4877-b11d-cc305f995b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489859954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3489859954
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2752537359
Short name T143
Test name
Test status
Simulation time 1066858630 ps
CPU time 28.76 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:51 PM PDT 24
Peak memory 199716 kb
Host smart-8468eb58-317a-44a4-8fbe-5893abe31cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752537359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2752537359
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2366911169
Short name T339
Test name
Test status
Simulation time 2174391666 ps
CPU time 335.21 seconds
Started Jul 23 06:20:22 PM PDT 24
Finished Jul 23 06:25:58 PM PDT 24
Peak memory 468688 kb
Host smart-192a128a-4cfe-42da-bf4d-9ca772dc283b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366911169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2366911169
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3952106699
Short name T64
Test name
Test status
Simulation time 1575425806 ps
CPU time 87.72 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:21:56 PM PDT 24
Peak memory 199676 kb
Host smart-0a6152e4-49dd-4dd9-8e55-56c46bc037b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952106699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3952106699
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4189119368
Short name T150
Test name
Test status
Simulation time 1002729098 ps
CPU time 18.49 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:20:39 PM PDT 24
Peak memory 199668 kb
Host smart-d2222682-f969-47b0-ae7e-1a60a6e561a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189119368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4189119368
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.791244026
Short name T438
Test name
Test status
Simulation time 2559867712 ps
CPU time 7.67 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:30 PM PDT 24
Peak memory 199824 kb
Host smart-1cec995f-78a4-4658-8c3a-1a28ab7003c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791244026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.791244026
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1783298365
Short name T226
Test name
Test status
Simulation time 1327772196 ps
CPU time 65.12 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:21:34 PM PDT 24
Peak memory 199700 kb
Host smart-f24b0748-3c4e-4c15-9e48-ff3e464dafb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783298365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1783298365
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2113954018
Short name T73
Test name
Test status
Simulation time 82287185612 ps
CPU time 4572.71 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 07:36:41 PM PDT 24
Peak memory 761456 kb
Host smart-7635d7f0-efa3-4e3e-976d-7975c7d6cb64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113954018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2113954018
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3979410401
Short name T362
Test name
Test status
Simulation time 2547849359 ps
CPU time 31.95 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:21:00 PM PDT 24
Peak memory 199728 kb
Host smart-a8ef792e-1307-44c1-bd8e-7b3ff1516691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979410401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3979410401
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1667199760
Short name T388
Test name
Test status
Simulation time 32321437 ps
CPU time 0.58 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:20:30 PM PDT 24
Peak memory 195352 kb
Host smart-e0fc3bc0-8de7-4be1-b0e5-378adf6144c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667199760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1667199760
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.625416163
Short name T414
Test name
Test status
Simulation time 858879106 ps
CPU time 43.53 seconds
Started Jul 23 06:20:20 PM PDT 24
Finished Jul 23 06:21:04 PM PDT 24
Peak memory 199656 kb
Host smart-4bdf1721-1147-4bfb-b7f7-5c8b74a8db87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625416163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.625416163
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1543709531
Short name T384
Test name
Test status
Simulation time 4151671732 ps
CPU time 30.36 seconds
Started Jul 23 06:20:25 PM PDT 24
Finished Jul 23 06:20:56 PM PDT 24
Peak memory 199776 kb
Host smart-52962daa-6e60-4822-83ae-6a63bc24b1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543709531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1543709531
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2983952075
Short name T330
Test name
Test status
Simulation time 3392242401 ps
CPU time 593.85 seconds
Started Jul 23 06:20:27 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 639784 kb
Host smart-3320771f-c08e-48e1-ae35-ab95ca0019e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983952075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2983952075
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3879045757
Short name T320
Test name
Test status
Simulation time 3475573946 ps
CPU time 44.52 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:21:17 PM PDT 24
Peak memory 199768 kb
Host smart-4013abfb-592d-4f20-b874-936588692103
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879045757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3879045757
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1888449845
Short name T367
Test name
Test status
Simulation time 2926305711 ps
CPU time 28.15 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:51 PM PDT 24
Peak memory 199680 kb
Host smart-63c8c97d-760f-48e8-8054-8eddd53873de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888449845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1888449845
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.301828461
Short name T428
Test name
Test status
Simulation time 757568314 ps
CPU time 9.23 seconds
Started Jul 23 06:20:21 PM PDT 24
Finished Jul 23 06:20:32 PM PDT 24
Peak memory 199740 kb
Host smart-ae97195b-e7a7-489e-b5f5-72f15501fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301828461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.301828461
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3459612878
Short name T348
Test name
Test status
Simulation time 50424005344 ps
CPU time 613.58 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 216160 kb
Host smart-df245772-b03b-4ad2-81d9-494eb9bc2ceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459612878 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3459612878
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1299318202
Short name T72
Test name
Test status
Simulation time 135238739529 ps
CPU time 621.41 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:30:53 PM PDT 24
Peak memory 215672 kb
Host smart-64cb611c-823e-46b7-816c-8d780edcc8e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299318202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1299318202
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.449906688
Short name T407
Test name
Test status
Simulation time 405624490 ps
CPU time 24.16 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:20:55 PM PDT 24
Peak memory 199684 kb
Host smart-b9fdf8e7-a5f7-4641-a747-391a1322ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449906688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.449906688
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1640552058
Short name T327
Test name
Test status
Simulation time 36166755 ps
CPU time 0.6 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:20:33 PM PDT 24
Peak memory 195648 kb
Host smart-ade62379-a131-4db6-8e27-031a8b7ed0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640552058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1640552058
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2016679034
Short name T54
Test name
Test status
Simulation time 2844268449 ps
CPU time 89.22 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:22:01 PM PDT 24
Peak memory 199696 kb
Host smart-f2a12adb-d006-4151-be80-27d0bc045f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016679034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2016679034
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4250858911
Short name T256
Test name
Test status
Simulation time 3013816728 ps
CPU time 10.27 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:20:39 PM PDT 24
Peak memory 199784 kb
Host smart-fa52d8b1-f50b-4d63-952b-984e21095a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250858911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4250858911
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1385722645
Short name T42
Test name
Test status
Simulation time 5413274108 ps
CPU time 952.52 seconds
Started Jul 23 06:20:30 PM PDT 24
Finished Jul 23 06:36:23 PM PDT 24
Peak memory 764812 kb
Host smart-c4a305ea-9ab4-486d-b50e-1355e9fc04c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385722645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1385722645
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1730701429
Short name T306
Test name
Test status
Simulation time 58920154 ps
CPU time 1.07 seconds
Started Jul 23 06:20:24 PM PDT 24
Finished Jul 23 06:20:26 PM PDT 24
Peak memory 199608 kb
Host smart-84a95b97-9273-45c2-b964-a33e9f3fc087
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730701429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1730701429
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.4044743966
Short name T352
Test name
Test status
Simulation time 25251749654 ps
CPU time 84.23 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:21:53 PM PDT 24
Peak memory 199792 kb
Host smart-ef4569c6-3d03-486d-96d5-aa702040f688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044743966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.4044743966
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2623951370
Short name T329
Test name
Test status
Simulation time 153951563 ps
CPU time 4.22 seconds
Started Jul 23 06:20:32 PM PDT 24
Finished Jul 23 06:20:37 PM PDT 24
Peak memory 199780 kb
Host smart-3335ad06-165f-4d87-90de-d6680451491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623951370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2623951370
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3913962819
Short name T291
Test name
Test status
Simulation time 583744223917 ps
CPU time 3773.12 seconds
Started Jul 23 06:20:26 PM PDT 24
Finished Jul 23 07:23:21 PM PDT 24
Peak memory 814780 kb
Host smart-f14544cb-258e-4ef6-83ef-58e17296fc83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913962819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3913962819
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2695374069
Short name T76
Test name
Test status
Simulation time 50095474128 ps
CPU time 303.29 seconds
Started Jul 23 06:20:28 PM PDT 24
Finished Jul 23 06:25:32 PM PDT 24
Peak memory 213600 kb
Host smart-01a5939a-151d-4ee3-8437-2ff189c24c8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695374069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2695374069
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1642697639
Short name T302
Test name
Test status
Simulation time 13355900279 ps
CPU time 52.34 seconds
Started Jul 23 06:20:31 PM PDT 24
Finished Jul 23 06:21:24 PM PDT 24
Peak memory 199724 kb
Host smart-2dc7cd6d-d8e2-487f-81b6-973e5a3fb2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642697639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1642697639
Directory /workspace/9.hmac_wipe_secret/latest
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