Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20846209	1			T1	441329		T2	20781		T3	29972
all_values[1]	20846209	1			T1	441329		T2	20781		T3	29972
all_values[2]	20846209	1			T1	441329		T2	20781		T3	29972

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320245

1

T3

836

T11

14

T25

613

auto[1]

62218382

1

T1

132398

T2

62343

T3

89080

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53143130

1

T1

117780

T2

51978

T3

77903

auto[1]

9395497

1

T1

146180

T2

10365

T3

12013

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99482	1			T3	836		T25	61		T30	37
all_values[0]	auto[0]	auto[1]	361	1			T55	2		T57	4		T61	2
all_values[0]	auto[1]	auto[0]	20724900	1			T1	440943		T2	20556		T3	29100
all_values[0]	auto[1]	auto[1]	21466	1			T1	386		T2	225		T3	36
all_values[1]	auto[0]	auto[0]	89100	1			T28	2305		T26	346		T55	1700
all_values[1]	auto[0]	auto[1]	220	1			T61	4		T62	5		T79	3
all_values[1]	auto[1]	auto[0]	20756508	1			T1	441329		T2	20781		T3	29972
all_values[1]	auto[1]	auto[1]	381	1			T21	4		T27	3		T61	2
all_values[2]	auto[0]	auto[0]	59508	1			T11	3		T25	14		T52	12
all_values[2]	auto[0]	auto[1]	71574	1			T11	11		T25	538		T132	1
all_values[2]	auto[1]	auto[0]	11413632	1			T1	295535		T2	10641		T3	17995
all_values[2]	auto[1]	auto[1]	9301495	1			T1	145794		T2	10140		T3	11977