Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134320

1

T1

384

T3

48

T6

12

auto[1]

117760

1

T2

224

T3

38

T6

26

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	98449	1			T1	55		T3	30		T6	19
len_1026_2046	4455	1			T1	1		T3	1		T7	1
len_514_1022	3113	1			T1	65		T3	3		T4	4
len_2_510	3986	1			T1	63		T3	2		T4	1
len_2056	239	1			T57	1		T62	5		T146	8
len_2048	327	1			T4	1		T5	3		T25	2
len_2040	189	1			T11	4		T62	4		T147	3
len_1032	181	1			T62	1		T147	5		T146	4
len_1024	1788	1			T1	2		T2	112		T3	5
len_1016	773	1			T1	1		T62	3		T146	2
len_520	182	1			T1	2		T62	6		T147	4
len_512	291	1			T11	2		T5	3		T25	1
len_504	382	1			T1	1		T23	2		T147	2
len_8	1346	1			T1	1		T21	21		T22	8
len_0	10341	1			T1	1		T3	2		T7	5

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

125

1

T3

6

T56

4

T148

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	53753	1			T1	55		T3	16		T6	6
auto[0]	len_1026_2046	2276	1			T1	1		T3	1		T7	1
auto[0]	len_514_1022	1824	1			T1	65		T3	2		T4	2
auto[0]	len_2_510	2603	1			T1	63		T3	1		T4	1
auto[0]	len_2056	90	1			T62	3		T146	5		T79	3
auto[0]	len_2048	191	1			T4	1		T5	2		T25	2
auto[0]	len_2040	104	1			T11	1		T62	1		T147	2
auto[0]	len_1032	106	1			T147	3		T146	2		T79	5
auto[0]	len_1024	239	1			T1	2		T3	3		T5	2
auto[0]	len_1016	499	1			T1	1		T62	3		T146	2
auto[0]	len_520	103	1			T1	2		T62	3		T147	2
auto[0]	len_512	179	1			T5	1		T25	1		T21	1
auto[0]	len_504	309	1			T1	1		T23	2		T147	1
auto[0]	len_8	60	1			T1	1		T23	1		T149	1
auto[0]	len_0	4826	1			T1	1		T3	1		T7	4
auto[1]	len_2050_plus	44696	1			T3	14		T6	13		T7	18
auto[1]	len_1026_2046	2179	1			T4	1		T5	21		T25	3
auto[1]	len_514_1022	1289	1			T3	1		T4	2		T5	62
auto[1]	len_2_510	1383	1			T3	1		T5	33		T25	1
auto[1]	len_2056	149	1			T57	1		T62	2		T146	3
auto[1]	len_2048	136	1			T5	1		T27	1		T61	1
auto[1]	len_2040	85	1			T11	3		T62	3		T147	1
auto[1]	len_1032	75	1			T62	1		T147	2		T146	2
auto[1]	len_1024	1549	1			T2	112		T3	2		T11	3
auto[1]	len_1016	274	1			T85	3		T150	3		T151	2
auto[1]	len_520	79	1			T62	3		T147	2		T146	1
auto[1]	len_512	112	1			T11	2		T5	2		T21	2
auto[1]	len_504	73	1			T147	1		T146	3		T79	2
auto[1]	len_8	1286	1			T21	21		T22	8		T57	10
auto[1]	len_0	5515	1			T3	1		T7	1		T11	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

70

1

T3

4

T56

2

T148

1

auto[1]

len_upper

55

1

T3

2

T56

2

T61

1