Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5119403

1

T1

147647

T2

5325

T3

6829

auto[1]

3232003

1

T3

7752

T6

2103

T7

7387

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3302363

1

T3

7786

T6

1752

T7

5838

auto[1]

5049043

1

T1

147647

T2

5325

T3

6795

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3628064

1

T1

147647

T3

6989

T6

2021

auto[1]

4723342

1

T2

5325

T3

7592

T6

3405

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5011281

1

T1

147647

T2

5325

T3

6264

auto[1]

3340125

1

T3

8317

T6

3069

T7

6877

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7593749	1			T1	145888		T2	4591		T3	13094
fifo_depth[1]	137646	1			T1	1480		T2	203		T3	225
fifo_depth[2]	106745	1			T1	239		T2	182		T3	229
fifo_depth[3]	83864	1			T1	38		T2	142		T3	234
fifo_depth[4]	74617	1			T1	2		T2	127		T3	217
fifo_depth[5]	58536	1			T2	66		T3	227		T6	81
fifo_depth[6]	47035	1			T2	11		T3	161		T6	50
fifo_depth[7]	30893	1			T2	3		T3	101		T6	33

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

757657

1

T1

1759

T2

734

T3

1487

auto[1]

7593749

1

T1

145888

T2

4591

T3

13094

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8340994

1

T1

147647

T2

5325

T3

14581

auto[1]

10412

1

T21

723

T27

495

T19

1642

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28171

1

T3

96

T6

87

T5

46

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

36665

1

T7

101

T5

62

T25

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27245

1

T3

14

T5

24

T26

21

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29304

1

T3

298

T4

39

T26

39

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

178628

1

T1

1759

T3

151

T6

16

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30590

1

T3

194

T28

85

T21

572

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34254

1

T3

14

T6

256

T7

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31850

1

T3

175

T7

234

T25

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44715

1

T3

14

T4

10

T25

48

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43550

1

T6

147

T7

159

T5

82

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43712

1

T3

70

T6

89

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45584

1

T3

108

T7

189

T21

1897

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46205

1

T2

734

T3

113

T11

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

54816

1

T11

2

T4

1

T28

394

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39934

1

T3

169

T7

131

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42434

1

T3

71

T6

41

T7

77

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

226186

1

T3

903

T6

157

T5

516

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

226148

1

T3

30

T6

181

T7

1378

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

217045

1

T3

543

T6

2

T7

402

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

205536

1

T3

1889

T6

2

T7

1043

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1731241

1

T1

145888

T3

711

T6

244

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

222484

1

T3

1031

T6

2

T7

207

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

204922

1

T3

50

T6

1069

T7

30

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

197795

1

T3

890

T6

5

T7

1040

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

522245

1

T3

1054

T6

1

T11

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

578439

1

T3

1284

T6

646

T7

523

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

541827

1

T3

661

T6

435

T7

410

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

485991

1

T3

822

T6

5

T7

1633

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

590504

1

T2

4591

T3

780

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

558816

1

T3

468

T6

1841

T11

11

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

534447

1

T3

921

T7

1900

T11

69

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

550123

1

T3

1057

T6

199

T7

293

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

254174

1

T3

999

T6

244

T5

562

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

261376

1

T3

30

T6

181

T7

1479

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

244034

1

T3

557

T6

2

T7

402

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

234529

1

T3

2187

T6

2

T7

1043

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1909105

1

T1

147647

T3

862

T6

260

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

252435

1

T3

1225

T6

2

T7

207

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

238750

1

T3

64

T6

1325

T7

35

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

229134

1

T3

1065

T6

5

T7

1274

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

565241

1

T3

1068

T6

1

T11

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

621582

1

T3

1284

T6

793

T7

682

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

585433

1

T3

731

T6

524

T7

410

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

530591

1

T3

930

T6

5

T7

1822

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

635827

1

T2

5325

T3

893

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

613284

1

T3

468

T6

1841

T11

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

573693

1

T3

1090

T7

2031

T11

70

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

591806

1

T3

1128

T6

240

T7

370

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

183

1

T21

6

T27

33

T96

36

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1437

1

T21

1

T27

83

T96

24

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

256

1

T27

24

T19

6

T96

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

311

1

T19

20

T96

3

T131

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

764

1

T21

11

T19

50

T96

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

639

1

T21

91

T27

37

T96

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

426

1

T21

94

T27

60

T19

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

511

1

T27

3

T19

280

T53

41

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1719

1

T21

7

T27

37

T19

1252

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

407

1

T21

1

T156

2

T157

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

106

1

T19

5

T53

5

T9

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

984

1

T21

504

T27

120

T19

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

882

1

T96

9

T158

400

T159

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

348

1

T21

8

T19

7

T34

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

688

1

T27

98

T19

9

T34

130

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

751

1

T34

438

T54

154

T160

4

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

226186

1

T3

903

T6

157

T5

516

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

226148

1

T3

30

T6

181

T7

1378

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

217045

1

T3

543

T6

2

T7

402

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

205536

1

T3

1889

T6

2

T7

1043

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1731241

1

T1

145888

T3

711

T6

244

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

222484

1

T3

1031

T6

2

T7

207

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

204922

1

T3

50

T6

1069

T7

30

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

197795

1

T3

890

T6

5

T7

1040

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

522245

1

T3

1054

T6

1

T11

15

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

578439

1

T3

1284

T6

646

T7

523

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

541827

1

T3

661

T6

435

T7

410

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

485991

1

T3

822

T6

5

T7

1633

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

590504

1

T2

4591

T3

780

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

558816

1

T3

468

T6

1841

T11

11

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

534447

1

T3

921

T7

1900

T11

69

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

550123

1

T3

1057

T6

199

T7

293

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4553

1

T3

14

T6

17

T5

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4749

1

T7

32

T5

6

T25

32

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4319

1

T3

5

T26

14

T55

66

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4242

1

T3

48

T4

5

T26

24

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

46529

1

T1

1480

T3

19

T6

7

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

5079

1

T3

25

T28

14

T21

38

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4649

1

T3

3

T6

36

T7

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3937

1

T3

30

T7

48

T25

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6340

1

T3

1

T21

2

T26

7

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7185

1

T6

23

T7

22

T5

7

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7834

1

T3

14

T6

19

T4

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6674

1

T3

12

T7

59

T21

39

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9273

1

T2

203

T3

18

T11

1

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

8398

1

T11

1

T28

51

T21

7

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6422

1

T3

24

T7

48

T11

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

7463

1

T3

12

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8

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12

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1

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14

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14

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20

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1

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32

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19

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22

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6

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6

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45

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10

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9

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1

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19

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6

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35

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15

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41

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1

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46

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52

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2

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1

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1

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27

fifo_depth[2]

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1

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38

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22

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17

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16

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4

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51

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44

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13

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1

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32

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1

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46

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17

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11

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7

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12

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1

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21

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16

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48

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21

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8

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16

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1

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65

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51

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8

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4

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38

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26

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1

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1

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31

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12

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39

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1

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44

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1

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1

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24

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55

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16

fifo_depth[3]

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2

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1

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3

fifo_depth[3]

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27

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31

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7

fifo_depth[3]

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10

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15

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2

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1

T3

20

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42

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45

fifo_depth[3]

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1

T2

142

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16

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21

fifo_depth[3]

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1

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1

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55

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16

fifo_depth[3]

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1

T3

18

T7

32

T21

87

fifo_depth[3]

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1

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11

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6

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12

fifo_depth[4]

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1

T3

15

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14

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13

fifo_depth[4]

auto[0]

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1

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8

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8

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15

fifo_depth[4]

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1

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4

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65

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3

fifo_depth[4]

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1

T3

53

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5

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2

fifo_depth[4]

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1

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20

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2

fifo_depth[4]

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1

T3

28

T28

12

T21

37

fifo_depth[4]

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1

T3

3

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38

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22

fifo_depth[4]

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1

T3

23

T7

41

T25

1

fifo_depth[4]

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1

T3

2

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6

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20

fifo_depth[4]

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4353

1

T6

22

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24

T5

11

fifo_depth[4]

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4980

1

T3

13

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16

T25

2

fifo_depth[4]

auto[1]

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4740

1

T3

10

T7

18

T21

41

fifo_depth[4]

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1

T2

127

T3

13

T21

53

fifo_depth[4]

auto[1]

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1

T28

64

T21

26

T30

1

fifo_depth[4]

auto[1]

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1

T3

25

T7

5

T21

90

fifo_depth[4]

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1

T3

12

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8

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9

fifo_depth[5]

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1

T3

15

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10

T21

22

fifo_depth[5]

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1

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7

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3

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15

fifo_depth[5]

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1

T3

3

T5

1

T55

76

fifo_depth[5]

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1

T3

44

T4

5

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22

fifo_depth[5]

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1

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25

T21

20

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13

fifo_depth[5]

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1

T3

32

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11

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40

fifo_depth[5]

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1

T3

2

T6

31

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1

fifo_depth[5]

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1

T3

24

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29

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17

fifo_depth[5]

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1

T3

4

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2

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36

fifo_depth[5]

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1

T6

19

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23

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5

fifo_depth[5]

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1

T3

7

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12

T25

1

fifo_depth[5]

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T3

16

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6

T21

49

fifo_depth[5]

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1

T2

66

T3

19

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14

fifo_depth[5]

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1

T28

44

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13

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1

fifo_depth[5]

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1

T3

25

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68

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16

fifo_depth[5]

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1

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11

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9

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12

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1

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10

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6

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4

fifo_depth[6]

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1

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4

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14

fifo_depth[6]

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1

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7

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2

fifo_depth[6]

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1

T3

34

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4

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16

fifo_depth[6]

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1

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15

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6

fifo_depth[6]

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1

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T28

8

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28

fifo_depth[6]

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1

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26

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fifo_depth[6]

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1

T3

27

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10

fifo_depth[6]

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1

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6

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7

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4

fifo_depth[6]

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1

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11

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14

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12

fifo_depth[6]

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1

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6

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5

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1

fifo_depth[6]

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1

T3

10

T7

5

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35

fifo_depth[6]

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T2

11

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12

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10

fifo_depth[6]

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1

T28

45

T21

25

T22

72

fifo_depth[6]

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1

T3

19

T21

64

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10

fifo_depth[6]

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1

T3

6

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2

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9

fifo_depth[7]

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1

T3

4

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6

T5

1

fifo_depth[7]

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1

T5

5

T21

6

T27

22

fifo_depth[7]

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1

T55

37

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7

T61

1

fifo_depth[7]

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1

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13

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10

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9

fifo_depth[7]

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1

T3

16

T21

14

T55

4

fifo_depth[7]

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1

T3

12

T28

6

T21

24

fifo_depth[7]

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1

T3

1

T6

18

T21

9

fifo_depth[7]

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999

1

T3

12

T21

8

T27

43

fifo_depth[7]

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1

T21

5

T27

38

T62

3

fifo_depth[7]

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1

T6

5

T7

13

T5

7

fifo_depth[7]

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auto[0]

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1

T3

4

T6

3

T25

1

fifo_depth[7]

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2229

1

T3

8

T7

4

T21

35

fifo_depth[7]

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auto[0]

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1

T2

3

T3

10

T5

1

fifo_depth[7]

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1

T28

34

T21

12

T22

43

fifo_depth[7]

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1

T3

16

T21

56

T55

7

fifo_depth[7]

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2214

1

T3

5

T6

1

T7

5