Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	20846209	1			T1	441329		T2	20781		T3	29972
all_pins[1]	20846209	1			T1	441329		T2	20781		T3	29972
all_pins[2]	20846209	1			T1	441329		T2	20781		T3	29972

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	53214403	1			T1	117780		T2	51978		T3	77894
values[0x1]	9324224	1			T1	146180		T2	10365		T3	12022
transitions[0x0=>0x1]	9324042	1			T1	146180		T2	10365		T3	12022
transitions[0x1=>0x0]	9324050	1			T1	146180		T2	10365		T3	12022

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	20823899	1			T1	440943		T2	20556		T3	29927
all_pins[0]	values[0x1]	22310	1			T1	386		T2	225		T3	45
all_pins[0]	transitions[0x0=>0x1]	22240	1			T1	386		T2	225		T3	45
all_pins[0]	transitions[0x1=>0x0]	9301433	1			T1	145794		T2	10140		T3	11977
all_pins[1]	values[0x0]	20845790	1			T1	441329		T2	20781		T3	29972
all_pins[1]	values[0x1]	419	1			T21	5		T27	4		T61	2
all_pins[1]	transitions[0x0=>0x1]	371	1			T21	5		T27	4		T61	2
all_pins[1]	transitions[0x1=>0x0]	22262	1			T1	386		T2	225		T3	45
all_pins[2]	values[0x0]	11544714	1			T1	295535		T2	10641		T3	17995
all_pins[2]	values[0x1]	9301495	1			T1	145794		T2	10140		T3	11977
all_pins[2]	transitions[0x0=>0x1]	9301431	1			T1	145794		T2	10140		T3	11977
all_pins[2]	transitions[0x1=>0x0]	355	1			T21	5		T27	4		T61	1