Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1050 1 T61 10 T62 30 T79 7
all_values[1] 1050 1 T61 10 T62 30 T79 7
all_values[2] 1050 1 T61 10 T62 30 T79 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1613 1 T61 18 T62 49 T79 18
auto[1] 1537 1 T61 12 T62 41 T79 3


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1139 1 T61 4 T62 32 T79 12
auto[1] 2011 1 T61 26 T62 58 T79 9


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1829 1 T61 9 T62 54 T79 14
auto[1] 1321 1 T61 21 T62 36 T79 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 201 1 T61 3 T62 7 T79 4
all_values[0] auto[0] auto[0] auto[1] 116 1 T62 6 T85 1 T86 1
all_values[0] auto[0] auto[1] auto[0] 213 1 T62 6 T79 2 T85 2
all_values[0] auto[0] auto[1] auto[1] 97 1 T61 1 T62 2 T85 2
all_values[0] auto[1] auto[0] auto[1] 218 1 T61 2 T62 5 T79 1
all_values[0] auto[1] auto[1] auto[1] 205 1 T61 4 T62 4 T85 4
all_values[1] auto[0] auto[0] auto[0] 153 1 T61 1 T62 4 T79 1
all_values[1] auto[0] auto[0] auto[1] 134 1 T61 3 T62 3 T79 2
all_values[1] auto[0] auto[1] auto[0] 165 1 T62 3 T79 1 T85 3
all_values[1] auto[0] auto[1] auto[1] 131 1 T62 5 T85 2 T133 1
all_values[1] auto[1] auto[0] auto[1] 226 1 T61 4 T62 7 T79 3
all_values[1] auto[1] auto[1] auto[1] 241 1 T61 2 T62 8 T85 2
all_values[2] auto[0] auto[0] auto[0] 228 1 T62 5 T79 4 T85 4
all_values[2] auto[0] auto[0] auto[1] 108 1 T61 1 T62 6 T85 1
all_values[2] auto[0] auto[1] auto[0] 179 1 T62 7 T85 4 T99 1
all_values[2] auto[0] auto[1] auto[1] 104 1 T85 1 T134 2 T131 5
all_values[2] auto[1] auto[0] auto[1] 229 1 T61 4 T62 6 T79 3
all_values[2] auto[1] auto[1] auto[1] 202 1 T61 5 T62 6 T85 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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