Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4900	1			T3	8		T6	20		T7	6
sha2_none	5017	1			T3	7		T6	4		T7	5
sha2_512	8274	1			T1	386		T2	225		T3	10
sha2_384	8081	1			T3	16		T6	8		T7	8
sha2_256	7033	1			T3	6		T6	3		T7	6

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20661

1

T1

386

T2

225

T3

19

auto[1]

13111

1

T3

30

T6

27

T7

20

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13105

1

T3

27

T6

21

T7

16

auto[1]

20667

1

T1

386

T2

225

T3

22

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17578

1

T2

225

T3

22

T6

19

disabled

16194

1

T1

386

T3

27

T6

21

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5450	1			T3	8		T6	15		T7	5
key_none	8343	1			T1	386		T3	4		T6	1
key_1024	4883	1			T2	225		T3	9		T6	7
key_512	4252	1			T3	13		T6	6		T7	5
key_384	3794	1			T3	5		T6	3		T7	8
key_256	3593	1			T3	1		T6	3		T7	1
key_128	3359	1			T3	9		T6	4		T7	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20646

1

T1

386

T2

225

T3

23

auto[1]

13126

1

T3

26

T6

22

T7

21

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33523

1

T1

386

T2

225

T3

49

disabled

249

1

T6

3

T7

3

T58

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1873

1

T3

3

T6

1

T7

1

enabled

auto[0]

auto[0]

auto[1]

1908

1

T3

2

T6

2

T7

1

enabled

auto[0]

auto[1]

auto[0]

1865

1

T3

2

T6

3

T7

1

enabled

auto[0]

auto[1]

auto[1]

1742

1

T3

4

T6

6

T7

5

enabled

auto[1]

auto[0]

auto[0]

4450

1

T2

225

T3

2

T6

1

enabled

auto[1]

auto[0]

auto[1]

1915

1

T3

1

T6

2

T7

1

enabled

auto[1]

auto[1]

auto[0]

1997

1

T3

5

T6

1

T7

3

enabled

auto[1]

auto[1]

auto[1]

1828

1

T3

3

T6

3

T7

1

disabled

auto[0]

auto[0]

auto[0]

1418

1

T3

4

T6

2

T5

4

disabled

auto[0]

auto[0]

auto[1]

1473

1

T3

1

T6

2

T7

4

disabled

auto[0]

auto[1]

auto[0]

1422

1

T3

2

T6

2

T7

2

disabled

auto[0]

auto[1]

auto[1]

1404

1

T3

9

T6

3

T7

2

disabled

auto[1]

auto[0]

auto[0]

6216

1

T1

386

T3

3

T6

2

disabled

auto[1]

auto[0]

auto[1]

1408

1

T3

3

T6

1

T7

3

disabled

auto[1]

auto[1]

auto[0]

1405

1

T3

2

T6

6

T7

2

disabled

auto[1]

auto[1]

auto[1]

1448

1

T3

3

T6

3

T7

4

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17495

1

T2

225

T3

22

T6

18

enabled

disabled

83

1

T6

1

T7

2

T61

2

disabled

disabled

166

1

T6

2

T7

1

T58

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

16028

1

T1

386

T3

27

T6

19

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1288	1			T3	2		T6	14		T7	3
key_invalid	sha2_none	1026	1			T3	1		T6	1		T7	1
key_invalid	sha2_512	1005	1			T3	1		T28	1		T21	8
key_invalid	sha2_384	1019	1			T3	2		T7	1		T5	1
key_invalid	sha2_256	992	1			T3	1		T5	1		T21	5
key_none	sha2_invalid	635	1			T4	1		T5	5		T21	1
key_none	sha2_none	670	1			T3	2		T11	1		T5	2
key_none	sha2_512	2635	1			T1	386		T6	1		T7	3
key_none	sha2_384	2651	1			T3	2		T5	2		T21	3
key_none	sha2_256	1686	1			T7	2		T11	2		T5	2
key_1024	sha2_invalid	589	1			T3	2		T6	1		T11	1
key_1024	sha2_none	685	1			T7	1		T5	1		T25	3
key_1024	sha2_512	1895	1			T2	225		T6	3		T7	2
key_1024	sha2_384	997	1			T3	3		T6	2		T7	2
key_512	sha2_invalid	614	1			T3	2		T6	2		T7	1
key_512	sha2_none	666	1			T3	1		T6	1		T7	1
key_512	sha2_512	710	1			T3	5		T5	1		T25	1
key_512	sha2_384	1281	1			T3	4		T6	3		T7	2
key_512	sha2_256	932	1			T7	1		T5	1		T25	1
key_384	sha2_invalid	582	1			T6	2		T7	1		T4	1
key_384	sha2_none	612	1			T3	1		T7	1		T11	1
key_384	sha2_512	655	1			T7	4		T21	4		T30	1
key_384	sha2_384	735	1			T3	3		T7	2		T4	2
key_384	sha2_256	1142	1			T3	1		T6	1		T5	1
key_256	sha2_invalid	589	1			T11	2		T5	3		T21	3
key_256	sha2_none	644	1			T6	1		T7	1		T11	1
key_256	sha2_512	707	1			T3	1		T6	1		T5	1
key_256	sha2_384	694	1			T5	2		T25	2		T21	8
key_256	sha2_256	896	1			T6	1		T11	1		T4	1
key_128	sha2_invalid	572	1			T3	2		T6	1		T4	1
key_128	sha2_none	692	1			T3	2		T6	1		T5	1
key_128	sha2_512	654	1			T3	3		T5	2		T25	1
key_128	sha2_384	692	1			T3	2		T6	2		T7	1
key_128	sha2_256	706	1			T7	1		T21	4		T30	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

659

1

T3

4

T6

1

T7

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1288	1			T3	2		T6	14		T7	3
key_invalid	sha2_none	1026	1			T3	1		T6	1		T7	1
key_invalid	sha2_512	1005	1			T3	1		T28	1		T21	8
key_invalid	sha2_384	1019	1			T3	2		T7	1		T5	1
key_invalid	sha2_256	992	1			T3	1		T5	1		T21	5
key_none	sha2_invalid	635	1			T4	1		T5	5		T21	1
key_none	sha2_none	670	1			T3	2		T11	1		T5	2
key_none	sha2_512	2635	1			T1	386		T6	1		T7	3
key_none	sha2_384	2651	1			T3	2		T5	2		T21	3
key_none	sha2_256	1686	1			T7	2		T11	2		T5	2
key_1024	sha2_invalid	589	1			T3	2		T6	1		T11	1
key_1024	sha2_none	685	1			T7	1		T5	1		T25	3
key_1024	sha2_512	1895	1			T2	225		T6	3		T7	2
key_1024	sha2_384	997	1			T3	3		T6	2		T7	2
key_1024	sha2_256	659	1			T3	4		T6	1		T7	2
key_512	sha2_invalid	614	1			T3	2		T6	2		T7	1
key_512	sha2_none	666	1			T3	1		T6	1		T7	1
key_512	sha2_512	710	1			T3	5		T5	1		T25	1
key_512	sha2_384	1281	1			T3	4		T6	3		T7	2
key_512	sha2_256	932	1			T7	1		T5	1		T25	1
key_384	sha2_invalid	582	1			T6	2		T7	1		T4	1
key_384	sha2_none	612	1			T3	1		T7	1		T11	1
key_384	sha2_512	655	1			T7	4		T21	4		T30	1
key_384	sha2_384	735	1			T3	3		T7	2		T4	2
key_384	sha2_256	1142	1			T3	1		T6	1		T5	1
key_256	sha2_invalid	589	1			T11	2		T5	3		T21	3
key_256	sha2_none	644	1			T6	1		T7	1		T11	1
key_256	sha2_512	707	1			T3	1		T6	1		T5	1
key_256	sha2_384	694	1			T5	2		T25	2		T21	8
key_256	sha2_256	896	1			T6	1		T11	1		T4	1
key_128	sha2_invalid	572	1			T3	2		T6	1		T4	1
key_128	sha2_none	692	1			T3	2		T6	1		T5	1
key_128	sha2_512	654	1			T3	3		T5	2		T25	1
key_128	sha2_384	692	1			T3	2		T6	2		T7	1
key_128	sha2_256	706	1			T7	1		T21	4		T30	1