Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T532 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1896006585 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:13 PM PDT 24 176297398 ps
T533 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2292679501 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:54 PM PDT 24 200182049 ps
T534 /workspace/coverage/cover_reg_top/16.hmac_intr_test.4261115198 Jul 24 06:51:41 PM PDT 24 Jul 24 06:51:42 PM PDT 24 47108595 ps
T535 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2408795175 Jul 24 06:51:59 PM PDT 24 Jul 24 06:52:00 PM PDT 24 14103562 ps
T536 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1936707515 Jul 24 06:50:52 PM PDT 24 Jul 24 06:51:03 PM PDT 24 711844277 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2807590267 Jul 24 06:51:06 PM PDT 24 Jul 24 06:51:22 PM PDT 24 2097320231 ps
T122 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3188071495 Jul 24 06:51:29 PM PDT 24 Jul 24 06:51:31 PM PDT 24 35542149 ps
T537 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2747665893 Jul 24 06:50:57 PM PDT 24 Jul 24 06:50:58 PM PDT 24 23755673 ps
T538 /workspace/coverage/cover_reg_top/23.hmac_intr_test.929090425 Jul 24 06:52:05 PM PDT 24 Jul 24 06:52:06 PM PDT 24 26063554 ps
T109 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.657624875 Jul 24 06:51:04 PM PDT 24 Jul 24 06:51:12 PM PDT 24 612121738 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3924200109 Jul 24 06:50:58 PM PDT 24 Jul 24 06:51:08 PM PDT 24 623151770 ps
T539 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2420437123 Jul 24 06:50:54 PM PDT 24 Jul 24 06:50:55 PM PDT 24 109146952 ps
T540 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3949318918 Jul 24 06:51:53 PM PDT 24 Jul 24 06:51:55 PM PDT 24 109264804 ps
T541 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.642311776 Jul 24 06:51:58 PM PDT 24 Jul 24 06:52:01 PM PDT 24 342963954 ps
T542 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1722125477 Jul 24 06:52:03 PM PDT 24 Jul 24 06:52:03 PM PDT 24 22928609 ps
T543 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1060821079 Jul 24 06:51:40 PM PDT 24 Jul 24 06:51:43 PM PDT 24 660144067 ps
T123 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2721798614 Jul 24 06:51:24 PM PDT 24 Jul 24 06:51:26 PM PDT 24 146963256 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2610857184 Jul 24 06:51:31 PM PDT 24 Jul 24 06:51:32 PM PDT 24 143261873 ps
T76 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.378583582 Jul 24 06:51:32 PM PDT 24 Jul 24 06:51:35 PM PDT 24 188955413 ps
T544 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2424993922 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:35 PM PDT 24 36950528 ps
T545 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3723067703 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:09 PM PDT 24 11091449 ps
T546 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.690401012 Jul 24 06:51:05 PM PDT 24 Jul 24 06:51:06 PM PDT 24 668964178 ps
T124 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3002143293 Jul 24 06:51:43 PM PDT 24 Jul 24 06:51:46 PM PDT 24 512152958 ps
T547 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2387868918 Jul 24 06:52:13 PM PDT 24 Jul 24 06:52:14 PM PDT 24 40099757 ps
T125 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.254443898 Jul 24 06:51:53 PM PDT 24 Jul 24 06:51:55 PM PDT 24 101507684 ps
T548 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.311944821 Jul 24 06:51:42 PM PDT 24 Jul 24 06:51:43 PM PDT 24 115807031 ps
T549 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2308071193 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 31000109 ps
T550 /workspace/coverage/cover_reg_top/47.hmac_intr_test.423432394 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:11 PM PDT 24 37794322 ps
T126 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2516449722 Jul 24 06:51:28 PM PDT 24 Jul 24 06:51:30 PM PDT 24 30762942 ps
T551 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1818671666 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:55 PM PDT 24 835068676 ps
T127 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2010215752 Jul 24 06:51:58 PM PDT 24 Jul 24 06:52:00 PM PDT 24 122153340 ps
T552 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2243228273 Jul 24 06:51:03 PM PDT 24 Jul 24 06:51:05 PM PDT 24 43166689 ps
T553 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1951287542 Jul 24 06:51:29 PM PDT 24 Jul 24 06:51:31 PM PDT 24 158432104 ps
T554 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.606840864 Jul 24 06:51:38 PM PDT 24 Jul 24 06:51:41 PM PDT 24 583602003 ps
T112 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2232009707 Jul 24 06:51:02 PM PDT 24 Jul 24 06:51:05 PM PDT 24 1136172858 ps
T555 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2792369523 Jul 24 06:51:29 PM PDT 24 Jul 24 06:51:31 PM PDT 24 534196836 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2250279935 Jul 24 06:50:59 PM PDT 24 Jul 24 06:51:01 PM PDT 24 218334466 ps
T557 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.252827731 Jul 24 06:51:41 PM PDT 24 Jul 24 06:51:43 PM PDT 24 60408813 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1930143718 Jul 24 06:51:18 PM PDT 24 Jul 24 06:51:21 PM PDT 24 181816180 ps
T559 /workspace/coverage/cover_reg_top/7.hmac_intr_test.900307924 Jul 24 06:51:17 PM PDT 24 Jul 24 06:51:18 PM PDT 24 14812059 ps
T113 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2529615842 Jul 24 06:50:57 PM PDT 24 Jul 24 06:51:02 PM PDT 24 115730933 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1056427454 Jul 24 06:51:35 PM PDT 24 Jul 24 06:51:37 PM PDT 24 122680657 ps
T77 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.176340813 Jul 24 06:51:18 PM PDT 24 Jul 24 06:51:22 PM PDT 24 286327919 ps
T561 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2266217819 Jul 24 06:51:43 PM PDT 24 Jul 24 06:51:44 PM PDT 24 621797817 ps
T562 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2776325245 Jul 24 06:52:13 PM PDT 24 Jul 24 06:52:14 PM PDT 24 27106776 ps
T563 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1231670543 Jul 24 06:51:37 PM PDT 24 Jul 24 06:51:39 PM PDT 24 308757222 ps
T564 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.43978342 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:04 PM PDT 24 2080615338 ps
T565 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2208318416 Jul 24 06:52:13 PM PDT 24 Jul 24 06:52:14 PM PDT 24 83460445 ps
T566 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1134160331 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:34 PM PDT 24 22345987 ps
T567 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.976859881 Jul 24 06:51:38 PM PDT 24 Jul 24 07:01:55 PM PDT 24 65344195352 ps
T78 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2292510096 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:36 PM PDT 24 204176929 ps
T135 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2105271295 Jul 24 06:52:00 PM PDT 24 Jul 24 06:52:04 PM PDT 24 303319831 ps
T568 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2131734738 Jul 24 06:51:38 PM PDT 24 Jul 24 06:51:41 PM PDT 24 560771714 ps
T140 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1800619047 Jul 24 06:51:40 PM PDT 24 Jul 24 06:51:42 PM PDT 24 83461491 ps
T569 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.491215322 Jul 24 06:51:39 PM PDT 24 Jul 24 06:51:40 PM PDT 24 58643094 ps
T570 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2305265519 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:10 PM PDT 24 15272765 ps
T571 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.617317479 Jul 24 06:51:39 PM PDT 24 Jul 24 06:51:41 PM PDT 24 84377299 ps
T136 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.259053321 Jul 24 06:51:05 PM PDT 24 Jul 24 06:51:07 PM PDT 24 360119546 ps
T138 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2102202424 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:56 PM PDT 24 130134476 ps
T144 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2615110070 Jul 24 06:51:41 PM PDT 24 Jul 24 06:51:45 PM PDT 24 662510164 ps
T137 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2272706306 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:37 PM PDT 24 157477927 ps
T572 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3396942754 Jul 24 06:51:35 PM PDT 24 Jul 24 06:51:36 PM PDT 24 116796933 ps
T114 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4185826527 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:15 PM PDT 24 323502678 ps
T573 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3873762142 Jul 24 06:51:11 PM PDT 24 Jul 24 06:51:13 PM PDT 24 173521782 ps
T574 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1278724982 Jul 24 06:51:27 PM PDT 24 Jul 24 06:51:28 PM PDT 24 41656831 ps
T575 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3977506642 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:12 PM PDT 24 226985854 ps
T576 /workspace/coverage/cover_reg_top/8.hmac_intr_test.109649825 Jul 24 06:51:23 PM PDT 24 Jul 24 06:51:24 PM PDT 24 13616407 ps
T577 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3359025976 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 37888440 ps
T578 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2894436800 Jul 24 06:51:01 PM PDT 24 Jul 24 06:51:05 PM PDT 24 162477921 ps
T579 /workspace/coverage/cover_reg_top/6.hmac_intr_test.709959146 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:09 PM PDT 24 22240746 ps
T115 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.476890487 Jul 24 06:50:53 PM PDT 24 Jul 24 06:50:54 PM PDT 24 29349238 ps
T139 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4287884419 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:04 PM PDT 24 404565436 ps
T580 /workspace/coverage/cover_reg_top/0.hmac_intr_test.701034263 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:53 PM PDT 24 15238245 ps
T116 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3429037954 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:04 PM PDT 24 757641172 ps
T581 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1966863926 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 19487951 ps
T118 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2069788457 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:35 PM PDT 24 169246430 ps
T582 /workspace/coverage/cover_reg_top/24.hmac_intr_test.395163845 Jul 24 06:52:10 PM PDT 24 Jul 24 06:52:11 PM PDT 24 12278641 ps
T583 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2400183805 Jul 24 06:51:36 PM PDT 24 Jul 24 06:51:37 PM PDT 24 74629547 ps
T584 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3740856177 Jul 24 06:51:35 PM PDT 24 Jul 24 06:51:36 PM PDT 24 19726433 ps
T585 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4069924989 Jul 24 06:51:28 PM PDT 24 Jul 24 06:51:30 PM PDT 24 56983869 ps
T119 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1794183207 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:10 PM PDT 24 22925199 ps
T586 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.595612681 Jul 24 06:52:02 PM PDT 24 Jul 24 06:52:04 PM PDT 24 641540350 ps
T587 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.768877685 Jul 24 06:51:02 PM PDT 24 Jul 24 06:51:03 PM PDT 24 72801283 ps
T588 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2668650895 Jul 24 06:51:58 PM PDT 24 Jul 24 06:51:58 PM PDT 24 42533580 ps
T589 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1279970923 Jul 24 06:50:59 PM PDT 24 Jul 24 06:51:00 PM PDT 24 67243360 ps
T590 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1249711960 Jul 24 06:50:50 PM PDT 24 Jul 24 06:50:52 PM PDT 24 385866226 ps
T591 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1968561094 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 29181292 ps
T592 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3329928736 Jul 24 06:50:53 PM PDT 24 Jul 24 06:50:53 PM PDT 24 15688627 ps
T593 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4229335769 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:02 PM PDT 24 104748649 ps
T594 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2079073779 Jul 24 06:51:41 PM PDT 24 Jul 24 06:51:43 PM PDT 24 49847529 ps
T595 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1834813057 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:34 PM PDT 24 56554133 ps
T596 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1028125932 Jul 24 06:51:04 PM PDT 24 Jul 24 06:51:06 PM PDT 24 37497247 ps
T597 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.978189055 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:35 PM PDT 24 34324374 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4148447887 Jul 24 06:51:22 PM PDT 24 Jul 24 06:51:23 PM PDT 24 50083092 ps
T599 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4081512092 Jul 24 06:51:35 PM PDT 24 Jul 24 06:51:36 PM PDT 24 147532615 ps
T600 /workspace/coverage/cover_reg_top/33.hmac_intr_test.331341130 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 34410130 ps
T601 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3972862994 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:37 PM PDT 24 90761645 ps
T602 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4222169157 Jul 24 06:52:06 PM PDT 24 Jul 24 06:52:07 PM PDT 24 23681743 ps
T603 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3736683351 Jul 24 06:51:04 PM PDT 24 Jul 24 06:51:05 PM PDT 24 45203736 ps
T604 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2958461806 Jul 24 06:51:38 PM PDT 24 Jul 24 06:51:42 PM PDT 24 252615360 ps
T605 /workspace/coverage/cover_reg_top/17.hmac_intr_test.382694934 Jul 24 06:51:51 PM PDT 24 Jul 24 06:51:52 PM PDT 24 19492165 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.377208883 Jul 24 06:50:58 PM PDT 24 Jul 24 06:50:59 PM PDT 24 234246322 ps
T607 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3984162482 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:01 PM PDT 24 45716982 ps
T608 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1051486217 Jul 24 06:51:00 PM PDT 24 Jul 24 06:51:01 PM PDT 24 84973588 ps
T609 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2852270219 Jul 24 06:52:05 PM PDT 24 Jul 24 06:52:09 PM PDT 24 125488518 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1092457952 Jul 24 06:51:16 PM PDT 24 Jul 24 06:51:18 PM PDT 24 293938719 ps
T611 /workspace/coverage/cover_reg_top/29.hmac_intr_test.4139009483 Jul 24 06:52:09 PM PDT 24 Jul 24 06:52:10 PM PDT 24 42589901 ps
T612 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1433115524 Jul 24 06:51:38 PM PDT 24 Jul 24 06:51:39 PM PDT 24 70936222 ps
T613 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4063171685 Jul 24 06:50:53 PM PDT 24 Jul 24 06:51:04 PM PDT 24 3900339215 ps
T141 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2905454250 Jul 24 06:52:05 PM PDT 24 Jul 24 06:52:10 PM PDT 24 3058849376 ps
T614 /workspace/coverage/cover_reg_top/25.hmac_intr_test.514378422 Jul 24 06:52:05 PM PDT 24 Jul 24 06:52:06 PM PDT 24 15623742 ps
T615 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3138536543 Jul 24 06:52:04 PM PDT 24 Jul 24 06:52:05 PM PDT 24 18497189 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.659335989 Jul 24 06:50:51 PM PDT 24 Jul 24 06:50:54 PM PDT 24 158282160 ps
T142 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.130000312 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:35 PM PDT 24 84245776 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1030816762 Jul 24 06:51:06 PM PDT 24 Jul 24 06:51:09 PM PDT 24 189347871 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2301158290 Jul 24 06:50:51 PM PDT 24 Jul 24 06:50:55 PM PDT 24 835336977 ps
T619 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2269661817 Jul 24 06:51:53 PM PDT 24 Jul 24 06:51:55 PM PDT 24 80256322 ps
T620 /workspace/coverage/cover_reg_top/30.hmac_intr_test.74955989 Jul 24 06:52:05 PM PDT 24 Jul 24 06:52:06 PM PDT 24 14191697 ps
T621 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1611323716 Jul 24 06:51:10 PM PDT 24 Jul 24 06:51:11 PM PDT 24 32583914 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.492022502 Jul 24 06:51:03 PM PDT 24 Jul 24 06:51:05 PM PDT 24 50191410 ps
T623 /workspace/coverage/cover_reg_top/34.hmac_intr_test.147100642 Jul 24 06:52:14 PM PDT 24 Jul 24 06:52:15 PM PDT 24 13013311 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2230467600 Jul 24 06:51:38 PM PDT 24 Jul 24 06:51:41 PM PDT 24 145866832 ps
T625 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3463526135 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 45343813 ps
T626 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1502041153 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:54 PM PDT 24 242160904 ps
T627 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3440538635 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 14255215 ps
T143 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3313699657 Jul 24 06:51:43 PM PDT 24 Jul 24 06:51:47 PM PDT 24 431419927 ps
T628 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3419378422 Jul 24 06:53:17 PM PDT 24 Jul 24 06:53:19 PM PDT 24 25698552 ps
T629 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1725380527 Jul 24 06:51:33 PM PDT 24 Jul 24 06:51:34 PM PDT 24 15796681 ps
T630 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1550233781 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:11 PM PDT 24 414478400 ps
T631 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3169667130 Jul 24 06:51:09 PM PDT 24 Jul 24 06:51:10 PM PDT 24 74383811 ps
T632 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2393417055 Jul 24 06:51:29 PM PDT 24 Jul 24 06:51:32 PM PDT 24 53744421 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_intr_test.523515895 Jul 24 06:50:58 PM PDT 24 Jul 24 06:50:59 PM PDT 24 26988945 ps
T634 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1614914258 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:35 PM PDT 24 128116657 ps
T635 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.719939915 Jul 24 06:51:21 PM PDT 24 Jul 24 06:51:24 PM PDT 24 89900460 ps
T636 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.517524044 Jul 24 06:51:20 PM PDT 24 Jul 24 06:51:22 PM PDT 24 69078217 ps
T637 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.839895746 Jul 24 06:50:57 PM PDT 24 Jul 24 06:50:59 PM PDT 24 42316376 ps
T638 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2675699955 Jul 24 06:51:53 PM PDT 24 Jul 24 06:51:54 PM PDT 24 20206227 ps
T145 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.214273667 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:38 PM PDT 24 500689336 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.608526581 Jul 24 06:52:02 PM PDT 24 Jul 24 06:52:03 PM PDT 24 94779014 ps
T640 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3421495834 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:36 PM PDT 24 95247539 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.728276239 Jul 24 06:50:59 PM PDT 24 Jul 24 06:51:03 PM PDT 24 179396559 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2291398321 Jul 24 06:51:58 PM PDT 24 Jul 24 06:55:09 PM PDT 24 13341454972 ps
T643 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.701337429 Jul 24 06:51:43 PM PDT 24 Jul 24 06:51:45 PM PDT 24 53481523 ps
T644 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2879814064 Jul 24 06:51:39 PM PDT 24 Jul 24 06:51:40 PM PDT 24 30164583 ps
T645 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3803827241 Jul 24 06:52:09 PM PDT 24 Jul 24 06:52:10 PM PDT 24 21203001 ps
T646 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1979706290 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:39 PM PDT 24 400141012 ps
T647 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1130342971 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 59216139 ps
T648 /workspace/coverage/cover_reg_top/26.hmac_intr_test.730265029 Jul 24 06:52:04 PM PDT 24 Jul 24 06:52:05 PM PDT 24 14011018 ps
T649 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3954501805 Jul 24 06:52:11 PM PDT 24 Jul 24 06:52:12 PM PDT 24 25870458 ps
T650 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2516698703 Jul 24 06:51:34 PM PDT 24 Jul 24 06:51:38 PM PDT 24 246800510 ps
T651 /workspace/coverage/cover_reg_top/15.hmac_intr_test.87301039 Jul 24 06:51:40 PM PDT 24 Jul 24 06:51:41 PM PDT 24 13088943 ps
T652 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3143252407 Jul 24 06:52:06 PM PDT 24 Jul 24 06:52:06 PM PDT 24 33242730 ps
T653 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2103289687 Jul 24 06:52:08 PM PDT 24 Jul 24 06:52:08 PM PDT 24 15542778 ps
T654 /workspace/coverage/cover_reg_top/37.hmac_intr_test.608426945 Jul 24 06:52:14 PM PDT 24 Jul 24 06:52:15 PM PDT 24 15154178 ps
T655 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1567487808 Jul 24 06:50:57 PM PDT 24 Jul 24 06:50:59 PM PDT 24 272909794 ps
T656 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1909125412 Jul 24 06:52:04 PM PDT 24 Jul 24 06:52:05 PM PDT 24 13322704 ps
T657 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2297657416 Jul 24 06:52:12 PM PDT 24 Jul 24 06:52:12 PM PDT 24 18133666 ps
T658 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1752996514 Jul 24 06:50:53 PM PDT 24 Jul 24 06:50:54 PM PDT 24 121684618 ps
T659 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.790912087 Jul 24 06:50:52 PM PDT 24 Jul 24 06:50:56 PM PDT 24 662042621 ps

Test location /workspace/coverage/default/31.hmac_burst_wr.1012324363
Short name T5
Test name
Test status
Simulation time 17832387163 ps
CPU time 78.01 seconds
Started Jul 24 06:55:12 PM PDT 24
Finished Jul 24 06:56:31 PM PDT 24
Peak memory 199788 kb
Host smart-4ce8b5b2-1b34-41d6-aaf0-46f314949eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012324363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1012324363
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1313061698
Short name T13
Test name
Test status
Simulation time 478090174142 ps
CPU time 8640.34 seconds
Started Jul 24 06:52:55 PM PDT 24
Finished Jul 24 09:16:57 PM PDT 24
Peak memory 889516 kb
Host smart-5a031f75-5214-44d7-9f31-65554b8bd53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313061698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1313061698
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3186370021
Short name T3
Test name
Test status
Simulation time 2567693644 ps
CPU time 138.93 seconds
Started Jul 24 06:54:33 PM PDT 24
Finished Jul 24 06:56:52 PM PDT 24
Peak memory 199804 kb
Host smart-a8738376-4335-4a51-9046-61052cc4d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186370021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3186370021
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3113910911
Short name T62
Test name
Test status
Simulation time 19709720793 ps
CPU time 1604.02 seconds
Started Jul 24 06:52:48 PM PDT 24
Finished Jul 24 07:19:33 PM PDT 24
Peak memory 746216 kb
Host smart-26a428e1-366b-4b61-bb73-44c7c69c44b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113910911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3113910911
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.176340813
Short name T77
Test name
Test status
Simulation time 286327919 ps
CPU time 4.64 seconds
Started Jul 24 06:51:18 PM PDT 24
Finished Jul 24 06:51:22 PM PDT 24
Peak memory 199880 kb
Host smart-819f3a18-303e-4d97-8c2c-ec8cd1c938b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176340813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.176340813
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3039327473
Short name T24
Test name
Test status
Simulation time 73631797539 ps
CPU time 5798.02 seconds
Started Jul 24 06:52:42 PM PDT 24
Finished Jul 24 08:29:22 PM PDT 24
Peak memory 848132 kb
Host smart-944d7747-fca8-4aa3-9c21-a932c94bd7c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039327473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3039327473
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3435332460
Short name T21
Test name
Test status
Simulation time 12990085428 ps
CPU time 758.15 seconds
Started Jul 24 06:52:46 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 633948 kb
Host smart-df0cdfa5-3270-4b13-9a92-741607f1e5bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435332460 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3435332460
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3387982903
Short name T59
Test name
Test status
Simulation time 28006273 ps
CPU time 0.63 seconds
Started Jul 24 06:52:59 PM PDT 24
Finished Jul 24 06:53:00 PM PDT 24
Peak memory 195748 kb
Host smart-a201f4dc-0820-4d54-9eb7-4390289ace28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387982903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3387982903
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4138899728
Short name T85
Test name
Test status
Simulation time 223617675671 ps
CPU time 3317.71 seconds
Started Jul 24 06:53:47 PM PDT 24
Finished Jul 24 07:49:06 PM PDT 24
Peak memory 771240 kb
Host smart-66aebc55-74f9-46a1-880a-a1bfda4ab96c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138899728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4138899728
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4048567081
Short name T63
Test name
Test status
Simulation time 76564873 ps
CPU time 0.79 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:52:17 PM PDT 24
Peak memory 218240 kb
Host smart-84387d79-452f-4825-87b1-d463a56bd418
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048567081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4048567081
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2927528765
Short name T19
Test name
Test status
Simulation time 1067066894 ps
CPU time 56.37 seconds
Started Jul 24 06:52:38 PM PDT 24
Finished Jul 24 06:53:35 PM PDT 24
Peak memory 199780 kb
Host smart-7e696d7f-994f-4135-b7d5-e6c7b5e3ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927528765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2927528765
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2905454250
Short name T141
Test name
Test status
Simulation time 3058849376 ps
CPU time 4.39 seconds
Started Jul 24 06:52:05 PM PDT 24
Finished Jul 24 06:52:10 PM PDT 24
Peak memory 200000 kb
Host smart-59856c30-b710-4593-ae92-6d7c7dd99b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905454250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2905454250
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2274218209
Short name T108
Test name
Test status
Simulation time 49655373 ps
CPU time 0.92 seconds
Started Jul 24 06:51:02 PM PDT 24
Finished Jul 24 06:51:03 PM PDT 24
Peak memory 199624 kb
Host smart-ffacab9f-2bc8-497c-a621-36ce00e533f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274218209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2274218209
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2687815479
Short name T146
Test name
Test status
Simulation time 134888513089 ps
CPU time 569.34 seconds
Started Jul 24 06:53:51 PM PDT 24
Finished Jul 24 07:03:20 PM PDT 24
Peak memory 199672 kb
Host smart-e322d2bb-e192-4123-8aae-908dd81ca1ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687815479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2687815479
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2102202424
Short name T138
Test name
Test status
Simulation time 130134476 ps
CPU time 3.89 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:56 PM PDT 24
Peak memory 199856 kb
Host smart-399aee2d-15a4-42d3-9a4e-445ed4c35eed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102202424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2102202424
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2832392354
Short name T503
Test name
Test status
Simulation time 987597414 ps
CPU time 48.37 seconds
Started Jul 24 06:54:33 PM PDT 24
Finished Jul 24 06:55:22 PM PDT 24
Peak memory 199720 kb
Host smart-36dbcb7c-3a49-4f4d-b710-bb61fcb4cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832392354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2832392354
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.715580323
Short name T14
Test name
Test status
Simulation time 2152384409557 ps
CPU time 3193.51 seconds
Started Jul 24 06:52:18 PM PDT 24
Finished Jul 24 07:45:32 PM PDT 24
Peak memory 770444 kb
Host smart-bf85a46d-c1a0-444a-8f2b-291a8a336b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715580323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.715580323
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1818671666
Short name T551
Test name
Test status
Simulation time 835068676 ps
CPU time 3.37 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:55 PM PDT 24
Peak memory 199644 kb
Host smart-4546dfe5-a3d8-4d12-a799-fb45ba54f174
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818671666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1818671666
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4063171685
Short name T613
Test name
Test status
Simulation time 3900339215 ps
CPU time 10.85 seconds
Started Jul 24 06:50:53 PM PDT 24
Finished Jul 24 06:51:04 PM PDT 24
Peak memory 199928 kb
Host smart-bbfc4392-3134-4479-89cb-7843870e6d97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063171685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4063171685
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1752996514
Short name T658
Test name
Test status
Simulation time 121684618 ps
CPU time 0.98 seconds
Started Jul 24 06:50:53 PM PDT 24
Finished Jul 24 06:50:54 PM PDT 24
Peak memory 199476 kb
Host smart-c0ae116b-91ed-45a4-bc7f-9569dd4e518e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752996514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1752996514
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2292679501
Short name T533
Test name
Test status
Simulation time 200182049 ps
CPU time 2.3 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:54 PM PDT 24
Peak memory 199928 kb
Host smart-278e0170-bb45-4362-8963-e889ff6ce8b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292679501 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2292679501
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1249711960
Short name T590
Test name
Test status
Simulation time 385866226 ps
CPU time 0.94 seconds
Started Jul 24 06:50:50 PM PDT 24
Finished Jul 24 06:50:52 PM PDT 24
Peak memory 199740 kb
Host smart-50242240-c64b-4679-b3a4-71968dd4b940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249711960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1249711960
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.701034263
Short name T580
Test name
Test status
Simulation time 15238245 ps
CPU time 0.61 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:53 PM PDT 24
Peak memory 194660 kb
Host smart-7dcd81cd-4968-491d-8a32-d71dcbdf7fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701034263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.701034263
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.659335989
Short name T616
Test name
Test status
Simulation time 158282160 ps
CPU time 2.67 seconds
Started Jul 24 06:50:51 PM PDT 24
Finished Jul 24 06:50:54 PM PDT 24
Peak memory 199876 kb
Host smart-27d48f6b-e91a-43c2-9416-fdfac7806b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659335989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.659335989
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1502041153
Short name T626
Test name
Test status
Simulation time 242160904 ps
CPU time 1.6 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:54 PM PDT 24
Peak memory 199796 kb
Host smart-0a6e6f65-abb6-4c2f-87e9-f56c89a27d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502041153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1502041153
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3429037954
Short name T116
Test name
Test status
Simulation time 757641172 ps
CPU time 3.27 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:04 PM PDT 24
Peak memory 199804 kb
Host smart-a71f61b1-a0bb-4756-aa5b-315af0ac6779
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429037954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3429037954
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1936707515
Short name T536
Test name
Test status
Simulation time 711844277 ps
CPU time 11.34 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:51:03 PM PDT 24
Peak memory 199840 kb
Host smart-c7992a99-4832-44d6-afaf-b913f24a025d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936707515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1936707515
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.476890487
Short name T115
Test name
Test status
Simulation time 29349238 ps
CPU time 0.89 seconds
Started Jul 24 06:50:53 PM PDT 24
Finished Jul 24 06:50:54 PM PDT 24
Peak memory 199292 kb
Host smart-78105bd9-494a-4e66-96a3-5296f384b72e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476890487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.476890487
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1567487808
Short name T655
Test name
Test status
Simulation time 272909794 ps
CPU time 1.87 seconds
Started Jul 24 06:50:57 PM PDT 24
Finished Jul 24 06:50:59 PM PDT 24
Peak memory 199960 kb
Host smart-1ab17aeb-a7bb-490a-9aa0-c5634c02a7a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567487808 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1567487808
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2420437123
Short name T539
Test name
Test status
Simulation time 109146952 ps
CPU time 0.86 seconds
Started Jul 24 06:50:54 PM PDT 24
Finished Jul 24 06:50:55 PM PDT 24
Peak memory 199144 kb
Host smart-eb69e29b-904f-4c59-a700-9b7cbf4e1c5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420437123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2420437123
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3329928736
Short name T592
Test name
Test status
Simulation time 15688627 ps
CPU time 0.64 seconds
Started Jul 24 06:50:53 PM PDT 24
Finished Jul 24 06:50:53 PM PDT 24
Peak memory 194876 kb
Host smart-6004251e-0760-4fa4-b944-706a86177cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329928736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3329928736
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4229335769
Short name T593
Test name
Test status
Simulation time 104748649 ps
CPU time 1.9 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:02 PM PDT 24
Peak memory 199844 kb
Host smart-b5a13204-396e-4521-b4da-ea26fd5b1739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229335769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4229335769
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2301158290
Short name T618
Test name
Test status
Simulation time 835336977 ps
CPU time 3.35 seconds
Started Jul 24 06:50:51 PM PDT 24
Finished Jul 24 06:50:55 PM PDT 24
Peak memory 199828 kb
Host smart-86126cc7-5f13-4e15-9892-3aa8534aca64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301158290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2301158290
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.790912087
Short name T659
Test name
Test status
Simulation time 662042621 ps
CPU time 3 seconds
Started Jul 24 06:50:52 PM PDT 24
Finished Jul 24 06:50:56 PM PDT 24
Peak memory 199856 kb
Host smart-4e5971f4-d693-4d0b-bb1a-45bfaeebfa85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790912087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.790912087
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3396942754
Short name T572
Test name
Test status
Simulation time 116796933 ps
CPU time 1.04 seconds
Started Jul 24 06:51:35 PM PDT 24
Finished Jul 24 06:51:36 PM PDT 24
Peak memory 199680 kb
Host smart-50a9c256-5016-48e1-8929-3db2697d7e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396942754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3396942754
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1614914258
Short name T634
Test name
Test status
Simulation time 128116657 ps
CPU time 0.73 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 198104 kb
Host smart-16d7da48-f3e0-4ead-ad76-745a66afbd77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614914258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1614914258
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2400183805
Short name T583
Test name
Test status
Simulation time 74629547 ps
CPU time 0.57 seconds
Started Jul 24 06:51:36 PM PDT 24
Finished Jul 24 06:51:37 PM PDT 24
Peak memory 194760 kb
Host smart-0923a61a-8283-4179-b32b-a90ecc2ded2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400183805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2400183805
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.978189055
Short name T597
Test name
Test status
Simulation time 34324374 ps
CPU time 1.5 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 199800 kb
Host smart-4a384139-d238-4535-bc96-2a9656f67f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978189055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.978189055
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2516698703
Short name T650
Test name
Test status
Simulation time 246800510 ps
CPU time 3.73 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:38 PM PDT 24
Peak memory 199852 kb
Host smart-8e6e3844-bc82-4116-9b27-d5dba36b9a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516698703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2516698703
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.214273667
Short name T145
Test name
Test status
Simulation time 500689336 ps
CPU time 4.04 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:38 PM PDT 24
Peak memory 199860 kb
Host smart-661006c5-e33a-400c-8302-95ef7c6cb46c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214273667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.214273667
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3419378422
Short name T628
Test name
Test status
Simulation time 25698552 ps
CPU time 1.49 seconds
Started Jul 24 06:53:17 PM PDT 24
Finished Jul 24 06:53:19 PM PDT 24
Peak memory 199920 kb
Host smart-7949e4a6-27b7-4e61-a8c4-f8c08ee5ccfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419378422 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3419378422
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4081512092
Short name T599
Test name
Test status
Simulation time 147532615 ps
CPU time 0.83 seconds
Started Jul 24 06:51:35 PM PDT 24
Finished Jul 24 06:51:36 PM PDT 24
Peak memory 199076 kb
Host smart-72d51436-ea91-441a-affe-14fe25761821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081512092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4081512092
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1134160331
Short name T566
Test name
Test status
Simulation time 22345987 ps
CPU time 0.57 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:34 PM PDT 24
Peak memory 194700 kb
Host smart-ec9b08c2-5eee-4fe0-b88f-4874342e144d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134160331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1134160331
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3972862994
Short name T601
Test name
Test status
Simulation time 90761645 ps
CPU time 2.09 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:37 PM PDT 24
Peak memory 199788 kb
Host smart-2343779d-80ea-4cdf-ad76-afa3e576e08a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972862994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3972862994
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3421495834
Short name T640
Test name
Test status
Simulation time 95247539 ps
CPU time 2.16 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:36 PM PDT 24
Peak memory 199880 kb
Host smart-385a8bcf-467e-43af-8d0e-c9ae872a0735
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421495834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3421495834
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2272706306
Short name T137
Test name
Test status
Simulation time 157477927 ps
CPU time 3.14 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:37 PM PDT 24
Peak memory 199904 kb
Host smart-0529905f-2012-4ac8-842c-f8ad31772413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272706306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2272706306
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1231670543
Short name T563
Test name
Test status
Simulation time 308757222 ps
CPU time 2.27 seconds
Started Jul 24 06:51:37 PM PDT 24
Finished Jul 24 06:51:39 PM PDT 24
Peak memory 199964 kb
Host smart-70fd8298-ad3f-46db-ad4b-05f0d390456d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231670543 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1231670543
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2069788457
Short name T118
Test name
Test status
Simulation time 169246430 ps
CPU time 0.91 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 199672 kb
Host smart-7486c4ec-2441-4d43-bb41-11ab3880fe82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069788457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2069788457
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1725380527
Short name T629
Test name
Test status
Simulation time 15796681 ps
CPU time 0.61 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:34 PM PDT 24
Peak memory 194736 kb
Host smart-8cc2d4e1-ccc5-4dea-b2ce-68608d1668bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725380527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1725380527
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2230467600
Short name T624
Test name
Test status
Simulation time 145866832 ps
CPU time 1.96 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 06:51:41 PM PDT 24
Peak memory 199824 kb
Host smart-8e9bdcca-d3d0-479f-99c6-ea2f363f83e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230467600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2230467600
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1056427454
Short name T560
Test name
Test status
Simulation time 122680657 ps
CPU time 1.52 seconds
Started Jul 24 06:51:35 PM PDT 24
Finished Jul 24 06:51:37 PM PDT 24
Peak memory 199868 kb
Host smart-47f16249-12b8-48b3-a1a9-66a44552ae5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056427454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1056427454
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.130000312
Short name T142
Test name
Test status
Simulation time 84245776 ps
CPU time 1.73 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 199808 kb
Host smart-1d803c46-9862-47e4-b174-4c1876f98aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130000312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.130000312
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2424993922
Short name T544
Test name
Test status
Simulation time 36950528 ps
CPU time 1.24 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 199764 kb
Host smart-b12cc4d5-5cd6-4058-8504-a76acb458828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424993922 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2424993922
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1834813057
Short name T595
Test name
Test status
Simulation time 56554133 ps
CPU time 0.88 seconds
Started Jul 24 06:51:33 PM PDT 24
Finished Jul 24 06:51:34 PM PDT 24
Peak memory 199672 kb
Host smart-9b63de3e-06e3-492b-be85-2aaae5999ad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834813057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1834813057
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3740856177
Short name T584
Test name
Test status
Simulation time 19726433 ps
CPU time 0.63 seconds
Started Jul 24 06:51:35 PM PDT 24
Finished Jul 24 06:51:36 PM PDT 24
Peak memory 194944 kb
Host smart-a6324a59-4236-4a16-bace-c75adc1b6944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740856177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3740856177
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.606840864
Short name T554
Test name
Test status
Simulation time 583602003 ps
CPU time 2.33 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 06:51:41 PM PDT 24
Peak memory 199844 kb
Host smart-9d223e03-d8f5-49c4-83d0-56a0f87a3da4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606840864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.606840864
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1979706290
Short name T646
Test name
Test status
Simulation time 400141012 ps
CPU time 4.37 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:39 PM PDT 24
Peak memory 199876 kb
Host smart-03b89c8c-0325-48e7-8cf4-435bb08ce769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979706290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1979706290
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2292510096
Short name T78
Test name
Test status
Simulation time 204176929 ps
CPU time 1.69 seconds
Started Jul 24 06:51:34 PM PDT 24
Finished Jul 24 06:51:36 PM PDT 24
Peak memory 199808 kb
Host smart-619caa0e-7ed5-4df6-ab23-ab366f716ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292510096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2292510096
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.252827731
Short name T557
Test name
Test status
Simulation time 60408813 ps
CPU time 1.81 seconds
Started Jul 24 06:51:41 PM PDT 24
Finished Jul 24 06:51:43 PM PDT 24
Peak memory 199896 kb
Host smart-810db51a-bcd6-40f0-a6db-fe73da03940e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252827731 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.252827731
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.491215322
Short name T569
Test name
Test status
Simulation time 58643094 ps
CPU time 0.69 seconds
Started Jul 24 06:51:39 PM PDT 24
Finished Jul 24 06:51:40 PM PDT 24
Peak memory 197112 kb
Host smart-353eacaa-f4e8-4029-ab2a-6f0d1281e10a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491215322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.491215322
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1433115524
Short name T612
Test name
Test status
Simulation time 70936222 ps
CPU time 0.6 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 06:51:39 PM PDT 24
Peak memory 194776 kb
Host smart-98015356-07cd-4758-8fb0-8645039e829f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433115524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1433115524
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2266217819
Short name T561
Test name
Test status
Simulation time 621797817 ps
CPU time 1.1 seconds
Started Jul 24 06:51:43 PM PDT 24
Finished Jul 24 06:51:44 PM PDT 24
Peak memory 199720 kb
Host smart-15829f31-e5d9-497c-a444-2b75e4ff2bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266217819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2266217819
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2958461806
Short name T604
Test name
Test status
Simulation time 252615360 ps
CPU time 3.36 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 06:51:42 PM PDT 24
Peak memory 199860 kb
Host smart-ba183efd-30a4-420b-bb14-f2e26ed958c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958461806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2958461806
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3313699657
Short name T143
Test name
Test status
Simulation time 431419927 ps
CPU time 4.23 seconds
Started Jul 24 06:51:43 PM PDT 24
Finished Jul 24 06:51:47 PM PDT 24
Peak memory 199868 kb
Host smart-b57114cb-dbfe-4f78-92dd-83fe37ebe092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313699657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3313699657
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.701337429
Short name T643
Test name
Test status
Simulation time 53481523 ps
CPU time 1.64 seconds
Started Jul 24 06:51:43 PM PDT 24
Finished Jul 24 06:51:45 PM PDT 24
Peak memory 199848 kb
Host smart-45f0c8fb-3f31-406c-ac08-55160a6c73f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701337429 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.701337429
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.311944821
Short name T548
Test name
Test status
Simulation time 115807031 ps
CPU time 0.85 seconds
Started Jul 24 06:51:42 PM PDT 24
Finished Jul 24 06:51:43 PM PDT 24
Peak memory 199092 kb
Host smart-1d36ed24-5c4d-4b4e-b169-77b673768e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311944821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.311944821
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.87301039
Short name T651
Test name
Test status
Simulation time 13088943 ps
CPU time 0.59 seconds
Started Jul 24 06:51:40 PM PDT 24
Finished Jul 24 06:51:41 PM PDT 24
Peak memory 194744 kb
Host smart-406eab39-337f-4d07-a4a7-67f4d8e4236d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87301039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.87301039
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2509477019
Short name T120
Test name
Test status
Simulation time 423130754 ps
CPU time 1.85 seconds
Started Jul 24 06:51:43 PM PDT 24
Finished Jul 24 06:51:45 PM PDT 24
Peak memory 199748 kb
Host smart-d57f48d3-1dbb-4063-b1f9-3e4ef03e1990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509477019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2509477019
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.617317479
Short name T571
Test name
Test status
Simulation time 84377299 ps
CPU time 1.16 seconds
Started Jul 24 06:51:39 PM PDT 24
Finished Jul 24 06:51:41 PM PDT 24
Peak memory 199688 kb
Host smart-164d3906-bb01-4fe8-8003-f7a063146232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617317479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.617317479
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1800619047
Short name T140
Test name
Test status
Simulation time 83461491 ps
CPU time 1.9 seconds
Started Jul 24 06:51:40 PM PDT 24
Finished Jul 24 06:51:42 PM PDT 24
Peak memory 199860 kb
Host smart-11d3cbbf-e391-4622-92ae-9fdd41fd0197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800619047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1800619047
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.976859881
Short name T567
Test name
Test status
Simulation time 65344195352 ps
CPU time 616.14 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 07:01:55 PM PDT 24
Peak memory 215132 kb
Host smart-072ffdbe-c949-4663-a571-c02dd2f25b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976859881 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.976859881
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2879814064
Short name T644
Test name
Test status
Simulation time 30164583 ps
CPU time 0.93 seconds
Started Jul 24 06:51:39 PM PDT 24
Finished Jul 24 06:51:40 PM PDT 24
Peak memory 199680 kb
Host smart-eb58796d-5bae-4408-9c35-90d1b720d94c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879814064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2879814064
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.4261115198
Short name T534
Test name
Test status
Simulation time 47108595 ps
CPU time 0.59 seconds
Started Jul 24 06:51:41 PM PDT 24
Finished Jul 24 06:51:42 PM PDT 24
Peak memory 194812 kb
Host smart-71b47c58-b84d-484c-9f7c-4078b7884133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261115198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.4261115198
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3002143293
Short name T124
Test name
Test status
Simulation time 512152958 ps
CPU time 2.03 seconds
Started Jul 24 06:51:43 PM PDT 24
Finished Jul 24 06:51:46 PM PDT 24
Peak memory 199820 kb
Host smart-de6e5780-9fc8-4531-8faa-f0a995807a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002143293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3002143293
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2131734738
Short name T568
Test name
Test status
Simulation time 560771714 ps
CPU time 2.77 seconds
Started Jul 24 06:51:38 PM PDT 24
Finished Jul 24 06:51:41 PM PDT 24
Peak memory 199780 kb
Host smart-de98c5ae-2ba8-47dc-8495-76371fa605df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131734738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2131734738
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2615110070
Short name T144
Test name
Test status
Simulation time 662510164 ps
CPU time 2.92 seconds
Started Jul 24 06:51:41 PM PDT 24
Finished Jul 24 06:51:45 PM PDT 24
Peak memory 199904 kb
Host smart-95efbb4f-7ada-4870-ace9-1ddd038db2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615110070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2615110070
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2269661817
Short name T619
Test name
Test status
Simulation time 80256322 ps
CPU time 1.91 seconds
Started Jul 24 06:51:53 PM PDT 24
Finished Jul 24 06:51:55 PM PDT 24
Peak memory 199908 kb
Host smart-3433cd47-dc5b-4dbb-abc4-e6285709777a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269661817 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2269661817
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2675699955
Short name T638
Test name
Test status
Simulation time 20206227 ps
CPU time 0.86 seconds
Started Jul 24 06:51:53 PM PDT 24
Finished Jul 24 06:51:54 PM PDT 24
Peak memory 199336 kb
Host smart-e0fca160-a13f-4ae5-8722-ab61b4f3944a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675699955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2675699955
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.382694934
Short name T605
Test name
Test status
Simulation time 19492165 ps
CPU time 0.57 seconds
Started Jul 24 06:51:51 PM PDT 24
Finished Jul 24 06:51:52 PM PDT 24
Peak memory 194764 kb
Host smart-e9937cdf-d4b2-470a-a3dd-8b0cc0fef329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382694934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.382694934
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.254443898
Short name T125
Test name
Test status
Simulation time 101507684 ps
CPU time 1.69 seconds
Started Jul 24 06:51:53 PM PDT 24
Finished Jul 24 06:51:55 PM PDT 24
Peak memory 199912 kb
Host smart-2cacd25a-5b9c-467a-96e9-16590d38d18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254443898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.254443898
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1060821079
Short name T543
Test name
Test status
Simulation time 660144067 ps
CPU time 2.97 seconds
Started Jul 24 06:51:40 PM PDT 24
Finished Jul 24 06:51:43 PM PDT 24
Peak memory 199844 kb
Host smart-6af555ef-8b4b-4cb0-be4f-a095842aefc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060821079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1060821079
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2079073779
Short name T594
Test name
Test status
Simulation time 49847529 ps
CPU time 1.76 seconds
Started Jul 24 06:51:41 PM PDT 24
Finished Jul 24 06:51:43 PM PDT 24
Peak memory 199844 kb
Host smart-ab849459-99ba-4020-9aef-e4b4e05e7230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079073779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2079073779
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2291398321
Short name T642
Test name
Test status
Simulation time 13341454972 ps
CPU time 191.71 seconds
Started Jul 24 06:51:58 PM PDT 24
Finished Jul 24 06:55:09 PM PDT 24
Peak memory 215616 kb
Host smart-edb8be7f-feba-42d5-8fda-950211060322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291398321 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2291398321
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.608526581
Short name T639
Test name
Test status
Simulation time 94779014 ps
CPU time 0.68 seconds
Started Jul 24 06:52:02 PM PDT 24
Finished Jul 24 06:52:03 PM PDT 24
Peak memory 197664 kb
Host smart-9cec0e90-8916-4033-b534-a221f182dfa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608526581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.608526581
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2668650895
Short name T588
Test name
Test status
Simulation time 42533580 ps
CPU time 0.57 seconds
Started Jul 24 06:51:58 PM PDT 24
Finished Jul 24 06:51:58 PM PDT 24
Peak memory 194688 kb
Host smart-3ebe2f24-05b1-4369-9610-4eb485c37f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668650895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2668650895
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.595612681
Short name T586
Test name
Test status
Simulation time 641540350 ps
CPU time 2.39 seconds
Started Jul 24 06:52:02 PM PDT 24
Finished Jul 24 06:52:04 PM PDT 24
Peak memory 199888 kb
Host smart-19993ecd-5121-4dad-adc9-ee497f8e9bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595612681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.595612681
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3949318918
Short name T540
Test name
Test status
Simulation time 109264804 ps
CPU time 2.19 seconds
Started Jul 24 06:51:53 PM PDT 24
Finished Jul 24 06:51:55 PM PDT 24
Peak memory 199936 kb
Host smart-1aaf18a0-9003-40c4-8f17-7358b669e7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949318918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3949318918
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.642311776
Short name T541
Test name
Test status
Simulation time 342963954 ps
CPU time 2.57 seconds
Started Jul 24 06:51:58 PM PDT 24
Finished Jul 24 06:52:01 PM PDT 24
Peak memory 199964 kb
Host smart-7fe63665-ee55-4902-93d9-d34944697f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642311776 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.642311776
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3138536543
Short name T615
Test name
Test status
Simulation time 18497189 ps
CPU time 0.71 seconds
Started Jul 24 06:52:04 PM PDT 24
Finished Jul 24 06:52:05 PM PDT 24
Peak memory 197788 kb
Host smart-96830bdd-8b5b-469e-8251-28c2025a97da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138536543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3138536543
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3195035981
Short name T529
Test name
Test status
Simulation time 15722046 ps
CPU time 0.63 seconds
Started Jul 24 06:52:00 PM PDT 24
Finished Jul 24 06:52:00 PM PDT 24
Peak memory 194896 kb
Host smart-942eeef0-6605-4817-92b0-c6d38531ac89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195035981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3195035981
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2010215752
Short name T127
Test name
Test status
Simulation time 122153340 ps
CPU time 1.55 seconds
Started Jul 24 06:51:58 PM PDT 24
Finished Jul 24 06:52:00 PM PDT 24
Peak memory 199804 kb
Host smart-759da994-8b5d-4441-99db-a0a307848f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010215752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2010215752
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2852270219
Short name T609
Test name
Test status
Simulation time 125488518 ps
CPU time 3.41 seconds
Started Jul 24 06:52:05 PM PDT 24
Finished Jul 24 06:52:09 PM PDT 24
Peak memory 199912 kb
Host smart-c69e3957-0d89-4bf0-b59a-1eabe5b4e6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852270219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2852270219
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2105271295
Short name T135
Test name
Test status
Simulation time 303319831 ps
CPU time 3.24 seconds
Started Jul 24 06:52:00 PM PDT 24
Finished Jul 24 06:52:04 PM PDT 24
Peak memory 199920 kb
Host smart-3e6e2caf-837c-4a91-b62c-29492a1a722f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105271295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2105271295
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2232009707
Short name T112
Test name
Test status
Simulation time 1136172858 ps
CPU time 3.2 seconds
Started Jul 24 06:51:02 PM PDT 24
Finished Jul 24 06:51:05 PM PDT 24
Peak memory 199756 kb
Host smart-51b983e3-aa76-4768-b3e3-00ebfa7e2938
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232009707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2232009707
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4185826527
Short name T114
Test name
Test status
Simulation time 323502678 ps
CPU time 14.55 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:15 PM PDT 24
Peak memory 199836 kb
Host smart-c04c11c0-0c2a-4da8-9e1b-eb74669a9a63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185826527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4185826527
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.377208883
Short name T606
Test name
Test status
Simulation time 234246322 ps
CPU time 0.94 seconds
Started Jul 24 06:50:58 PM PDT 24
Finished Jul 24 06:50:59 PM PDT 24
Peak memory 199416 kb
Host smart-017305ec-c599-4e73-8ee8-d49027198ea2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377208883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.377208883
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2894436800
Short name T578
Test name
Test status
Simulation time 162477921 ps
CPU time 3.19 seconds
Started Jul 24 06:51:01 PM PDT 24
Finished Jul 24 06:51:05 PM PDT 24
Peak memory 208280 kb
Host smart-2bfd9614-4259-4f12-be6b-b528650af572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894436800 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2894436800
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2013920874
Short name T121
Test name
Test status
Simulation time 16242685 ps
CPU time 0.86 seconds
Started Jul 24 06:50:58 PM PDT 24
Finished Jul 24 06:50:59 PM PDT 24
Peak memory 199676 kb
Host smart-4d5814ab-5dac-4da2-945c-b4e5fa3f52a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013920874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2013920874
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.523515895
Short name T633
Test name
Test status
Simulation time 26988945 ps
CPU time 0.6 seconds
Started Jul 24 06:50:58 PM PDT 24
Finished Jul 24 06:50:59 PM PDT 24
Peak memory 194744 kb
Host smart-0ad9920a-beac-49d4-b16a-db56ad4d86bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523515895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.523515895
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.839895746
Short name T637
Test name
Test status
Simulation time 42316376 ps
CPU time 2.06 seconds
Started Jul 24 06:50:57 PM PDT 24
Finished Jul 24 06:50:59 PM PDT 24
Peak memory 199820 kb
Host smart-f5d2fff8-dae6-41b4-8b83-1334accf35be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839895746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.839895746
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3984162482
Short name T607
Test name
Test status
Simulation time 45716982 ps
CPU time 1.28 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:01 PM PDT 24
Peak memory 199920 kb
Host smart-560f91c7-0ea5-4834-aa95-7e212b313a92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984162482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3984162482
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.728276239
Short name T641
Test name
Test status
Simulation time 179396559 ps
CPU time 3.85 seconds
Started Jul 24 06:50:59 PM PDT 24
Finished Jul 24 06:51:03 PM PDT 24
Peak memory 199908 kb
Host smart-6cfc54b0-d627-4ba9-8057-247e7c97d95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728276239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.728276239
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2408795175
Short name T535
Test name
Test status
Simulation time 14103562 ps
CPU time 0.6 seconds
Started Jul 24 06:51:59 PM PDT 24
Finished Jul 24 06:52:00 PM PDT 24
Peak memory 194820 kb
Host smart-98bef67a-bb0d-4da4-bcd3-d241a7b333d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408795175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2408795175
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2103289687
Short name T653
Test name
Test status
Simulation time 15542778 ps
CPU time 0.61 seconds
Started Jul 24 06:52:08 PM PDT 24
Finished Jul 24 06:52:08 PM PDT 24
Peak memory 194832 kb
Host smart-185e1a7f-fcda-432b-8876-616f1a9abde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103289687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2103289687
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4222169157
Short name T602
Test name
Test status
Simulation time 23681743 ps
CPU time 0.63 seconds
Started Jul 24 06:52:06 PM PDT 24
Finished Jul 24 06:52:07 PM PDT 24
Peak memory 194820 kb
Host smart-a2b6012b-3ab5-481b-9d33-5d05ca3be3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222169157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4222169157
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.929090425
Short name T538
Test name
Test status
Simulation time 26063554 ps
CPU time 0.56 seconds
Started Jul 24 06:52:05 PM PDT 24
Finished Jul 24 06:52:06 PM PDT 24
Peak memory 194772 kb
Host smart-cd61c556-2d92-4609-9ed1-341f39f21415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929090425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.929090425
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.395163845
Short name T582
Test name
Test status
Simulation time 12278641 ps
CPU time 0.57 seconds
Started Jul 24 06:52:10 PM PDT 24
Finished Jul 24 06:52:11 PM PDT 24
Peak memory 194792 kb
Host smart-72b3bd14-3cc1-40bd-a0b3-4a431a03a835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395163845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.395163845
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.514378422
Short name T614
Test name
Test status
Simulation time 15623742 ps
CPU time 0.61 seconds
Started Jul 24 06:52:05 PM PDT 24
Finished Jul 24 06:52:06 PM PDT 24
Peak memory 194716 kb
Host smart-7e7da698-69e8-4372-aca0-b5522ff3631f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514378422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.514378422
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.730265029
Short name T648
Test name
Test status
Simulation time 14011018 ps
CPU time 0.61 seconds
Started Jul 24 06:52:04 PM PDT 24
Finished Jul 24 06:52:05 PM PDT 24
Peak memory 194840 kb
Host smart-c821c4d6-a664-4f80-8b2d-7c7730fc8ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730265029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.730265029
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1909125412
Short name T656
Test name
Test status
Simulation time 13322704 ps
CPU time 0.57 seconds
Started Jul 24 06:52:04 PM PDT 24
Finished Jul 24 06:52:05 PM PDT 24
Peak memory 194700 kb
Host smart-9d55b3bf-19e9-444a-864b-776eb9f08af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909125412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1909125412
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1722125477
Short name T542
Test name
Test status
Simulation time 22928609 ps
CPU time 0.62 seconds
Started Jul 24 06:52:03 PM PDT 24
Finished Jul 24 06:52:03 PM PDT 24
Peak memory 194912 kb
Host smart-092950c8-4dae-4d4c-835a-a561df635118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722125477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1722125477
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.4139009483
Short name T611
Test name
Test status
Simulation time 42589901 ps
CPU time 0.58 seconds
Started Jul 24 06:52:09 PM PDT 24
Finished Jul 24 06:52:10 PM PDT 24
Peak memory 194784 kb
Host smart-1dc878dc-0804-4b1f-8973-3b0cf3f68cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139009483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.4139009483
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3924200109
Short name T110
Test name
Test status
Simulation time 623151770 ps
CPU time 9.57 seconds
Started Jul 24 06:50:58 PM PDT 24
Finished Jul 24 06:51:08 PM PDT 24
Peak memory 199852 kb
Host smart-670d0589-cf22-4670-b9cf-c738debb306b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924200109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3924200109
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2529615842
Short name T113
Test name
Test status
Simulation time 115730933 ps
CPU time 5.24 seconds
Started Jul 24 06:50:57 PM PDT 24
Finished Jul 24 06:51:02 PM PDT 24
Peak memory 199848 kb
Host smart-c025e63e-652b-4436-968c-00f45be52cf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529615842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2529615842
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.768877685
Short name T587
Test name
Test status
Simulation time 72801283 ps
CPU time 0.79 seconds
Started Jul 24 06:51:02 PM PDT 24
Finished Jul 24 06:51:03 PM PDT 24
Peak memory 197992 kb
Host smart-db63fb63-4c7e-4351-8e58-5197809475eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768877685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.768877685
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2747665893
Short name T537
Test name
Test status
Simulation time 23755673 ps
CPU time 1.29 seconds
Started Jul 24 06:50:57 PM PDT 24
Finished Jul 24 06:50:58 PM PDT 24
Peak memory 199912 kb
Host smart-6d231dd2-4eae-4823-b059-fbea0f06b48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747665893 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2747665893
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1279970923
Short name T589
Test name
Test status
Simulation time 67243360 ps
CPU time 0.58 seconds
Started Jul 24 06:50:59 PM PDT 24
Finished Jul 24 06:51:00 PM PDT 24
Peak memory 194712 kb
Host smart-df51a8ab-56dd-4306-b4ed-335a514c97a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279970923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1279970923
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1051486217
Short name T608
Test name
Test status
Simulation time 84973588 ps
CPU time 1.16 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:01 PM PDT 24
Peak memory 199656 kb
Host smart-93d1b03c-4ddd-4951-bd5d-d4357f3c77a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051486217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1051486217
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.43978342
Short name T564
Test name
Test status
Simulation time 2080615338 ps
CPU time 4.15 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:04 PM PDT 24
Peak memory 199844 kb
Host smart-ede4d8e8-56ca-490f-85a7-0ffd4db179a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43978342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.43978342
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4287884419
Short name T139
Test name
Test status
Simulation time 404565436 ps
CPU time 3.52 seconds
Started Jul 24 06:51:00 PM PDT 24
Finished Jul 24 06:51:04 PM PDT 24
Peak memory 199900 kb
Host smart-3daa0a82-2eff-4cfb-a49f-1778f344eeee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287884419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4287884419
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.74955989
Short name T620
Test name
Test status
Simulation time 14191697 ps
CPU time 0.6 seconds
Started Jul 24 06:52:05 PM PDT 24
Finished Jul 24 06:52:06 PM PDT 24
Peak memory 194796 kb
Host smart-329468b0-6b10-48c2-b3f4-5ef49d070c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74955989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.74955989
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3143252407
Short name T652
Test name
Test status
Simulation time 33242730 ps
CPU time 0.58 seconds
Started Jul 24 06:52:06 PM PDT 24
Finished Jul 24 06:52:06 PM PDT 24
Peak memory 194732 kb
Host smart-3f52d44a-7fa2-4c49-bd45-763b10dba43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143252407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3143252407
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2776325245
Short name T562
Test name
Test status
Simulation time 27106776 ps
CPU time 0.59 seconds
Started Jul 24 06:52:13 PM PDT 24
Finished Jul 24 06:52:14 PM PDT 24
Peak memory 194880 kb
Host smart-c11a2e49-29ea-4aae-a987-9a16f2a76bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776325245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2776325245
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.331341130
Short name T600
Test name
Test status
Simulation time 34410130 ps
CPU time 0.57 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194792 kb
Host smart-f395a8f6-029f-459f-9759-805801ee19f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331341130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.331341130
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.147100642
Short name T623
Test name
Test status
Simulation time 13013311 ps
CPU time 0.58 seconds
Started Jul 24 06:52:14 PM PDT 24
Finished Jul 24 06:52:15 PM PDT 24
Peak memory 194704 kb
Host smart-edb8bb73-4f67-465f-96f2-7831b81eccea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147100642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.147100642
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.369954244
Short name T530
Test name
Test status
Simulation time 13688767 ps
CPU time 0.62 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194904 kb
Host smart-a3a70c31-a8d0-4be5-adcc-9a1e53e1a08e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369954244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.369954244
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2387868918
Short name T547
Test name
Test status
Simulation time 40099757 ps
CPU time 0.6 seconds
Started Jul 24 06:52:13 PM PDT 24
Finished Jul 24 06:52:14 PM PDT 24
Peak memory 194736 kb
Host smart-c6b4342b-c548-4867-b1e2-7f1b2b954875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387868918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2387868918
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.608426945
Short name T654
Test name
Test status
Simulation time 15154178 ps
CPU time 0.61 seconds
Started Jul 24 06:52:14 PM PDT 24
Finished Jul 24 06:52:15 PM PDT 24
Peak memory 194784 kb
Host smart-7c2f5e93-1cda-496e-81de-f8f8000ecd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608426945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.608426945
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3954501805
Short name T649
Test name
Test status
Simulation time 25870458 ps
CPU time 0.58 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194760 kb
Host smart-b9912c96-1341-41bb-8773-7d87766c6cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954501805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3954501805
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3463526135
Short name T625
Test name
Test status
Simulation time 45343813 ps
CPU time 0.6 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194788 kb
Host smart-eee9e4a4-0b34-4353-8682-4a07b17b6eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463526135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3463526135
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.657624875
Short name T109
Test name
Test status
Simulation time 612121738 ps
CPU time 7.81 seconds
Started Jul 24 06:51:04 PM PDT 24
Finished Jul 24 06:51:12 PM PDT 24
Peak memory 199836 kb
Host smart-6e6ef8f1-e2ad-43d5-9747-88920c05dab9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657624875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.657624875
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2807590267
Short name T117
Test name
Test status
Simulation time 2097320231 ps
CPU time 15.65 seconds
Started Jul 24 06:51:06 PM PDT 24
Finished Jul 24 06:51:22 PM PDT 24
Peak memory 199904 kb
Host smart-85aa425a-0318-4bd0-bc9f-97fa1331b54e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807590267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2807590267
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3736683351
Short name T603
Test name
Test status
Simulation time 45203736 ps
CPU time 1 seconds
Started Jul 24 06:51:04 PM PDT 24
Finished Jul 24 06:51:05 PM PDT 24
Peak memory 199676 kb
Host smart-554a7eab-62f6-4be4-ae67-62398a69b688
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736683351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3736683351
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1030816762
Short name T617
Test name
Test status
Simulation time 189347871 ps
CPU time 2.52 seconds
Started Jul 24 06:51:06 PM PDT 24
Finished Jul 24 06:51:09 PM PDT 24
Peak memory 199912 kb
Host smart-be4c040c-9ffc-4ada-8401-35be650cec33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030816762 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1030816762
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1794183207
Short name T119
Test name
Test status
Simulation time 22925199 ps
CPU time 0.79 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:10 PM PDT 24
Peak memory 197988 kb
Host smart-166cdb3a-5f1c-4c18-8b91-30189197249c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794183207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1794183207
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3723067703
Short name T545
Test name
Test status
Simulation time 11091449 ps
CPU time 0.61 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:09 PM PDT 24
Peak memory 194848 kb
Host smart-66638f96-2934-4191-baa4-84c476d79d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723067703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3723067703
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1550233781
Short name T630
Test name
Test status
Simulation time 414478400 ps
CPU time 1.79 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:11 PM PDT 24
Peak memory 199972 kb
Host smart-1e49017c-f213-443b-b3bc-c45f02956bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550233781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1550233781
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2250279935
Short name T556
Test name
Test status
Simulation time 218334466 ps
CPU time 2.19 seconds
Started Jul 24 06:50:59 PM PDT 24
Finished Jul 24 06:51:01 PM PDT 24
Peak memory 199908 kb
Host smart-d566a526-4c4c-4a9e-90c6-c8d1caac6010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250279935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2250279935
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.259053321
Short name T136
Test name
Test status
Simulation time 360119546 ps
CPU time 1.79 seconds
Started Jul 24 06:51:05 PM PDT 24
Finished Jul 24 06:51:07 PM PDT 24
Peak memory 199952 kb
Host smart-81110679-c607-4b57-be52-b9daecbfda4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259053321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.259053321
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1968561094
Short name T591
Test name
Test status
Simulation time 29181292 ps
CPU time 0.62 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194872 kb
Host smart-55261072-3c84-41a7-be7b-385e2a872061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968561094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1968561094
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1130342971
Short name T647
Test name
Test status
Simulation time 59216139 ps
CPU time 0.65 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194816 kb
Host smart-afb68f05-e68a-4064-86d8-8dd110df9f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130342971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1130342971
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3440538635
Short name T627
Test name
Test status
Simulation time 14255215 ps
CPU time 0.62 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194788 kb
Host smart-ccacec95-06df-4184-b57c-7a05cc654d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440538635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3440538635
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2308071193
Short name T549
Test name
Test status
Simulation time 31000109 ps
CPU time 0.59 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194780 kb
Host smart-ce73858f-856f-4cb6-905a-b725904ec7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308071193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2308071193
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1966863926
Short name T581
Test name
Test status
Simulation time 19487951 ps
CPU time 0.64 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194884 kb
Host smart-d72a09aa-37c0-449c-9445-e3d33e1fa68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966863926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1966863926
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2208318416
Short name T565
Test name
Test status
Simulation time 83460445 ps
CPU time 0.61 seconds
Started Jul 24 06:52:13 PM PDT 24
Finished Jul 24 06:52:14 PM PDT 24
Peak memory 194752 kb
Host smart-c6e74b5c-0ad7-4eb8-ad98-8dcb272e5101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208318416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2208318416
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2297657416
Short name T657
Test name
Test status
Simulation time 18133666 ps
CPU time 0.61 seconds
Started Jul 24 06:52:12 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194760 kb
Host smart-4eec675a-d4c8-4a8e-aabb-2a7198c6db3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297657416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2297657416
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.423432394
Short name T550
Test name
Test status
Simulation time 37794322 ps
CPU time 0.56 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:11 PM PDT 24
Peak memory 194728 kb
Host smart-9dd4a98b-c4df-4e8b-ab87-c6dc47dfb666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423432394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.423432394
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3359025976
Short name T577
Test name
Test status
Simulation time 37888440 ps
CPU time 0.56 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:52:12 PM PDT 24
Peak memory 194724 kb
Host smart-f3fb0381-2b2a-4e01-b131-0dc0c44ed752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359025976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3359025976
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3803827241
Short name T645
Test name
Test status
Simulation time 21203001 ps
CPU time 0.62 seconds
Started Jul 24 06:52:09 PM PDT 24
Finished Jul 24 06:52:10 PM PDT 24
Peak memory 194608 kb
Host smart-63fe796b-3fa5-4bea-a898-c7988fd5a79a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803827241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3803827241
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.690401012
Short name T546
Test name
Test status
Simulation time 668964178 ps
CPU time 1.1 seconds
Started Jul 24 06:51:05 PM PDT 24
Finished Jul 24 06:51:06 PM PDT 24
Peak memory 199624 kb
Host smart-396c6ef0-0a4f-4b5b-adfe-fc48dcd85497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690401012 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.690401012
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3169667130
Short name T631
Test name
Test status
Simulation time 74383811 ps
CPU time 0.86 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:10 PM PDT 24
Peak memory 199324 kb
Host smart-09dac277-6be7-4d31-9bf7-1f9ea57c5f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169667130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3169667130
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2305265519
Short name T570
Test name
Test status
Simulation time 15272765 ps
CPU time 0.63 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:10 PM PDT 24
Peak memory 194860 kb
Host smart-75e4e7db-d92a-47e2-9d5e-0004dd996819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305265519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2305265519
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2243228273
Short name T552
Test name
Test status
Simulation time 43166689 ps
CPU time 1.15 seconds
Started Jul 24 06:51:03 PM PDT 24
Finished Jul 24 06:51:05 PM PDT 24
Peak memory 199848 kb
Host smart-48eda906-db56-4dfb-821a-ab4bfe96697e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243228273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2243228273
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1028125932
Short name T596
Test name
Test status
Simulation time 37497247 ps
CPU time 2.03 seconds
Started Jul 24 06:51:04 PM PDT 24
Finished Jul 24 06:51:06 PM PDT 24
Peak memory 199872 kb
Host smart-c5b5f85a-00b1-47d6-9183-7589ae5812ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028125932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1028125932
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.492022502
Short name T622
Test name
Test status
Simulation time 50191410 ps
CPU time 1.95 seconds
Started Jul 24 06:51:03 PM PDT 24
Finished Jul 24 06:51:05 PM PDT 24
Peak memory 199796 kb
Host smart-fcaad919-f187-4056-b5f3-50c92c4a21bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492022502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.492022502
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1930143718
Short name T558
Test name
Test status
Simulation time 181816180 ps
CPU time 2.59 seconds
Started Jul 24 06:51:18 PM PDT 24
Finished Jul 24 06:51:21 PM PDT 24
Peak memory 199904 kb
Host smart-280c8518-1875-442e-bbd6-88626855cc9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930143718 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1930143718
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1611323716
Short name T621
Test name
Test status
Simulation time 32583914 ps
CPU time 0.69 seconds
Started Jul 24 06:51:10 PM PDT 24
Finished Jul 24 06:51:11 PM PDT 24
Peak memory 197732 kb
Host smart-4f4ca011-b40a-4851-9017-7f17432bf6df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611323716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1611323716
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.709959146
Short name T579
Test name
Test status
Simulation time 22240746 ps
CPU time 0.59 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:09 PM PDT 24
Peak memory 194832 kb
Host smart-520ca1ea-ca0d-40d5-8436-b2251295c078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709959146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.709959146
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3977506642
Short name T575
Test name
Test status
Simulation time 226985854 ps
CPU time 2.35 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:12 PM PDT 24
Peak memory 199896 kb
Host smart-d08ab714-5b8c-4042-a099-edadf04a63be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977506642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3977506642
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1896006585
Short name T532
Test name
Test status
Simulation time 176297398 ps
CPU time 3.14 seconds
Started Jul 24 06:51:09 PM PDT 24
Finished Jul 24 06:51:13 PM PDT 24
Peak memory 199912 kb
Host smart-e8f91487-5930-4abc-b8b8-d30103feeb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896006585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1896006585
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3873762142
Short name T573
Test name
Test status
Simulation time 173521782 ps
CPU time 1.74 seconds
Started Jul 24 06:51:11 PM PDT 24
Finished Jul 24 06:51:13 PM PDT 24
Peak memory 199948 kb
Host smart-f5ca57f6-736c-4506-a582-58a87e18a225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873762142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3873762142
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4148447887
Short name T598
Test name
Test status
Simulation time 50083092 ps
CPU time 1.23 seconds
Started Jul 24 06:51:22 PM PDT 24
Finished Jul 24 06:51:23 PM PDT 24
Peak memory 199668 kb
Host smart-1c92a8e3-7541-4496-9733-fe59e2922072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148447887 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4148447887
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1278724982
Short name T574
Test name
Test status
Simulation time 41656831 ps
CPU time 0.7 seconds
Started Jul 24 06:51:27 PM PDT 24
Finished Jul 24 06:51:28 PM PDT 24
Peak memory 197332 kb
Host smart-a80832c1-c525-4618-b43b-5b8093ea4fc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278724982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1278724982
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.900307924
Short name T559
Test name
Test status
Simulation time 14812059 ps
CPU time 0.64 seconds
Started Jul 24 06:51:17 PM PDT 24
Finished Jul 24 06:51:18 PM PDT 24
Peak memory 194748 kb
Host smart-40cc1cbd-f497-4d68-80b9-b8ab0d12bd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900307924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.900307924
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2721798614
Short name T123
Test name
Test status
Simulation time 146963256 ps
CPU time 1.6 seconds
Started Jul 24 06:51:24 PM PDT 24
Finished Jul 24 06:51:26 PM PDT 24
Peak memory 199780 kb
Host smart-18f0e8e6-c5ad-4c5c-8ccd-ef20630651ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721798614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2721798614
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1092457952
Short name T610
Test name
Test status
Simulation time 293938719 ps
CPU time 1.76 seconds
Started Jul 24 06:51:16 PM PDT 24
Finished Jul 24 06:51:18 PM PDT 24
Peak memory 199860 kb
Host smart-39bcd1ae-ac32-4a9b-a0db-2b41fb5a2b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092457952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1092457952
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4069924989
Short name T585
Test name
Test status
Simulation time 56983869 ps
CPU time 1.23 seconds
Started Jul 24 06:51:28 PM PDT 24
Finished Jul 24 06:51:30 PM PDT 24
Peak memory 199948 kb
Host smart-6a96caba-d754-4cc5-939d-10c589256f29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069924989 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4069924989
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2610857184
Short name T111
Test name
Test status
Simulation time 143261873 ps
CPU time 0.9 seconds
Started Jul 24 06:51:31 PM PDT 24
Finished Jul 24 06:51:32 PM PDT 24
Peak memory 199272 kb
Host smart-3b53965a-87d4-4aba-b534-a307d0a8a41d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610857184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2610857184
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.109649825
Short name T576
Test name
Test status
Simulation time 13616407 ps
CPU time 0.62 seconds
Started Jul 24 06:51:23 PM PDT 24
Finished Jul 24 06:51:24 PM PDT 24
Peak memory 194792 kb
Host smart-f67d7129-9e52-4350-afa4-1009bcfe72d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109649825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.109649825
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3188071495
Short name T122
Test name
Test status
Simulation time 35542149 ps
CPU time 1.63 seconds
Started Jul 24 06:51:29 PM PDT 24
Finished Jul 24 06:51:31 PM PDT 24
Peak memory 199808 kb
Host smart-a1127587-af56-4be1-9013-c76bf7760624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188071495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3188071495
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.517524044
Short name T636
Test name
Test status
Simulation time 69078217 ps
CPU time 1.55 seconds
Started Jul 24 06:51:20 PM PDT 24
Finished Jul 24 06:51:22 PM PDT 24
Peak memory 199900 kb
Host smart-0a74ab9d-d8b9-476d-a8be-adecd37d2554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517524044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.517524044
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.719939915
Short name T635
Test name
Test status
Simulation time 89900460 ps
CPU time 2.92 seconds
Started Jul 24 06:51:21 PM PDT 24
Finished Jul 24 06:51:24 PM PDT 24
Peak memory 199900 kb
Host smart-6ca04d77-19a5-4625-b715-c522ef73b013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719939915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.719939915
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1951287542
Short name T553
Test name
Test status
Simulation time 158432104 ps
CPU time 2.72 seconds
Started Jul 24 06:51:29 PM PDT 24
Finished Jul 24 06:51:31 PM PDT 24
Peak memory 208092 kb
Host smart-d7e17aeb-3c6d-4c61-ac9f-d17abe2ab853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951287542 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1951287542
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2516449722
Short name T126
Test name
Test status
Simulation time 30762942 ps
CPU time 0.95 seconds
Started Jul 24 06:51:28 PM PDT 24
Finished Jul 24 06:51:30 PM PDT 24
Peak memory 199688 kb
Host smart-5ca1b62b-ca60-48fa-9e8d-2737e9ebd342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516449722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2516449722
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.394431331
Short name T531
Test name
Test status
Simulation time 10539759 ps
CPU time 0.57 seconds
Started Jul 24 06:51:29 PM PDT 24
Finished Jul 24 06:51:30 PM PDT 24
Peak memory 194672 kb
Host smart-a59e1454-da62-435d-9d02-d596a5a544fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394431331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.394431331
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2792369523
Short name T555
Test name
Test status
Simulation time 534196836 ps
CPU time 1.77 seconds
Started Jul 24 06:51:29 PM PDT 24
Finished Jul 24 06:51:31 PM PDT 24
Peak memory 199872 kb
Host smart-0745b358-94c7-4c49-a283-d52158a851e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792369523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2792369523
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2393417055
Short name T632
Test name
Test status
Simulation time 53744421 ps
CPU time 2.56 seconds
Started Jul 24 06:51:29 PM PDT 24
Finished Jul 24 06:51:32 PM PDT 24
Peak memory 199852 kb
Host smart-3c89e947-38e0-4889-b1ab-9e5c04ce1f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393417055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2393417055
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.378583582
Short name T76
Test name
Test status
Simulation time 188955413 ps
CPU time 3.2 seconds
Started Jul 24 06:51:32 PM PDT 24
Finished Jul 24 06:51:35 PM PDT 24
Peak memory 199840 kb
Host smart-508f103a-0a97-45df-8a62-69db92052c06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378583582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.378583582
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2888706086
Short name T499
Test name
Test status
Simulation time 12738972 ps
CPU time 0.6 seconds
Started Jul 24 06:52:21 PM PDT 24
Finished Jul 24 06:52:22 PM PDT 24
Peak memory 195740 kb
Host smart-083e7480-601f-407d-8789-898b6d3677be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888706086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2888706086
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3351200342
Short name T254
Test name
Test status
Simulation time 3625382284 ps
CPU time 52.79 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:53:09 PM PDT 24
Peak memory 216000 kb
Host smart-734435e8-91ba-4ba4-a4a7-f45c9afc04c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351200342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3351200342
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2499327121
Short name T475
Test name
Test status
Simulation time 7953763607 ps
CPU time 5.48 seconds
Started Jul 24 06:52:12 PM PDT 24
Finished Jul 24 06:52:18 PM PDT 24
Peak memory 199764 kb
Host smart-2c95ffb5-0ddd-450a-9fed-335291aaab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499327121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2499327121
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2058738712
Short name T522
Test name
Test status
Simulation time 2349654222 ps
CPU time 61.01 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:53:12 PM PDT 24
Peak memory 320124 kb
Host smart-10596cfd-db94-4607-8434-83aff21254ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058738712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2058738712
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2904327929
Short name T190
Test name
Test status
Simulation time 13226699136 ps
CPU time 170.32 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 06:55:02 PM PDT 24
Peak memory 199848 kb
Host smart-6205614b-5df3-439f-99c1-cd7ec8329fc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904327929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2904327929
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.512090293
Short name T308
Test name
Test status
Simulation time 57493607583 ps
CPU time 193.22 seconds
Started Jul 24 06:52:10 PM PDT 24
Finished Jul 24 06:55:24 PM PDT 24
Peak memory 199820 kb
Host smart-617d20fe-a02c-4d87-a36e-3b9e4515f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512090293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.512090293
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1836353984
Short name T74
Test name
Test status
Simulation time 106850838 ps
CPU time 0.77 seconds
Started Jul 24 06:52:17 PM PDT 24
Finished Jul 24 06:52:18 PM PDT 24
Peak memory 196524 kb
Host smart-39e5e258-b884-4e35-b9ef-12c07af58a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836353984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1836353984
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3027275160
Short name T208
Test name
Test status
Simulation time 6372612336 ps
CPU time 52.92 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:53:10 PM PDT 24
Peak memory 199872 kb
Host smart-50eb34f9-fb98-46c8-b5e1-81b127eedf78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3027275160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3027275160
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.570127340
Short name T342
Test name
Test status
Simulation time 18116888721 ps
CPU time 101.01 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:53:58 PM PDT 24
Peak memory 199712 kb
Host smart-0a67cbd9-34b7-472f-8346-2fc8a0cb391c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=570127340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.570127340
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2474838858
Short name T176
Test name
Test status
Simulation time 17072860197 ps
CPU time 123.49 seconds
Started Jul 24 06:52:18 PM PDT 24
Finished Jul 24 06:54:22 PM PDT 24
Peak memory 199728 kb
Host smart-a54bd152-c299-41aa-8819-ae76d6c8721c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474838858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2474838858
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1851841219
Short name T368
Test name
Test status
Simulation time 52887116471 ps
CPU time 696.96 seconds
Started Jul 24 06:52:12 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 199748 kb
Host smart-e44e423c-0ad5-490f-9194-77d7ddf84b10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1851841219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1851841219
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1254233798
Short name T360
Test name
Test status
Simulation time 77852843667 ps
CPU time 2058.6 seconds
Started Jul 24 06:52:11 PM PDT 24
Finished Jul 24 07:26:30 PM PDT 24
Peak memory 215544 kb
Host smart-a73048a8-bc2f-4e0b-8c88-4103c0da5abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1254233798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1254233798
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3672302657
Short name T472
Test name
Test status
Simulation time 77429352140 ps
CPU time 2130.73 seconds
Started Jul 24 06:52:14 PM PDT 24
Finished Jul 24 07:27:45 PM PDT 24
Peak memory 215864 kb
Host smart-05ec1536-6a82-4ac9-8dfc-371f34bcbc93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3672302657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3672302657
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3066654185
Short name T437
Test name
Test status
Simulation time 672674635 ps
CPU time 33.21 seconds
Started Jul 24 06:52:15 PM PDT 24
Finished Jul 24 06:52:48 PM PDT 24
Peak memory 199736 kb
Host smart-cac120de-6043-4d45-81f0-c051de66480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066654185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3066654185
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3820953713
Short name T274
Test name
Test status
Simulation time 42565502 ps
CPU time 0.59 seconds
Started Jul 24 06:52:23 PM PDT 24
Finished Jul 24 06:52:24 PM PDT 24
Peak memory 195728 kb
Host smart-fb9043f9-8ee1-4921-b35c-20f80d4a4342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820953713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3820953713
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1278523561
Short name T521
Test name
Test status
Simulation time 1486338540 ps
CPU time 85.03 seconds
Started Jul 24 06:52:18 PM PDT 24
Finished Jul 24 06:53:43 PM PDT 24
Peak memory 199744 kb
Host smart-fd0ef5aa-c6a4-4991-bfcd-8c9c86cd092d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278523561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1278523561
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.508719716
Short name T340
Test name
Test status
Simulation time 2361230583 ps
CPU time 66.35 seconds
Started Jul 24 06:52:17 PM PDT 24
Finished Jul 24 06:53:24 PM PDT 24
Peak memory 199812 kb
Host smart-fc84e7ae-eb5d-4995-976d-9c8c5893e7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508719716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.508719716
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1637399891
Short name T468
Test name
Test status
Simulation time 4473087546 ps
CPU time 990.01 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 07:08:47 PM PDT 24
Peak memory 754472 kb
Host smart-2558f1b1-a0fd-49c4-a74c-4e31781d4fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637399891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1637399891
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2051940598
Short name T354
Test name
Test status
Simulation time 14784836596 ps
CPU time 63.13 seconds
Started Jul 24 06:52:15 PM PDT 24
Finished Jul 24 06:53:18 PM PDT 24
Peak memory 199640 kb
Host smart-eb63ceb4-7d66-4032-809f-7f88ebf72edb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051940598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2051940598
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1922006162
Short name T271
Test name
Test status
Simulation time 19841558234 ps
CPU time 113.91 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:54:10 PM PDT 24
Peak memory 199780 kb
Host smart-9f359a95-9366-4a74-a45f-f86fceb7b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922006162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1922006162
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.863007075
Short name T65
Test name
Test status
Simulation time 135417004 ps
CPU time 0.91 seconds
Started Jul 24 06:52:24 PM PDT 24
Finished Jul 24 06:52:25 PM PDT 24
Peak memory 218292 kb
Host smart-968f7fbb-1d5d-45fa-a647-473784feca6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863007075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.863007075
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1325615493
Short name T363
Test name
Test status
Simulation time 125350339 ps
CPU time 2.1 seconds
Started Jul 24 06:52:16 PM PDT 24
Finished Jul 24 06:52:18 PM PDT 24
Peak memory 199768 kb
Host smart-44a163ea-e1be-44cc-a0c5-f985bf23a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325615493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1325615493
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3627356972
Short name T89
Test name
Test status
Simulation time 211694693708 ps
CPU time 447.13 seconds
Started Jul 24 06:52:23 PM PDT 24
Finished Jul 24 06:59:50 PM PDT 24
Peak memory 208000 kb
Host smart-a6c840eb-9d59-4075-b124-d7cdd9572570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627356972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3627356972
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2136062091
Short name T10
Test name
Test status
Simulation time 195836634918 ps
CPU time 2360.66 seconds
Started Jul 24 06:52:24 PM PDT 24
Finished Jul 24 07:31:45 PM PDT 24
Peak memory 748104 kb
Host smart-4f02c2b2-f9a5-40f0-b396-67e5d464a7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136062091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2136062091
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1647749455
Short name T40
Test name
Test status
Simulation time 18770466629 ps
CPU time 81.09 seconds
Started Jul 24 06:52:24 PM PDT 24
Finished Jul 24 06:53:45 PM PDT 24
Peak memory 199728 kb
Host smart-ba48a76f-e185-488b-8b75-85097a7bbd28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1647749455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1647749455
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1503202786
Short name T514
Test name
Test status
Simulation time 7606138829 ps
CPU time 60.51 seconds
Started Jul 24 06:52:25 PM PDT 24
Finished Jul 24 06:53:25 PM PDT 24
Peak memory 199820 kb
Host smart-22e4e1ff-b3a5-443f-bd8e-e74cc62d492a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1503202786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1503202786
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1770327075
Short name T439
Test name
Test status
Simulation time 43394920907 ps
CPU time 82.98 seconds
Started Jul 24 06:52:27 PM PDT 24
Finished Jul 24 06:53:51 PM PDT 24
Peak memory 199836 kb
Host smart-444a4e90-6fb7-43d3-9951-bf666fc4c5d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1770327075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1770327075
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.490485926
Short name T94
Test name
Test status
Simulation time 10456480517 ps
CPU time 566.47 seconds
Started Jul 24 06:52:17 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 199784 kb
Host smart-bbc1ba40-8d27-498f-b4d3-39bd8683f9a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=490485926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.490485926
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.559169168
Short name T449
Test name
Test status
Simulation time 39703976645 ps
CPU time 2259.99 seconds
Started Jul 24 06:52:18 PM PDT 24
Finished Jul 24 07:29:59 PM PDT 24
Peak memory 215220 kb
Host smart-74466203-ea65-4bd5-af75-48c481b0e6c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=559169168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.559169168
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3759927610
Short name T253
Test name
Test status
Simulation time 138870457827 ps
CPU time 2364.58 seconds
Started Jul 24 06:52:25 PM PDT 24
Finished Jul 24 07:31:50 PM PDT 24
Peak memory 215488 kb
Host smart-4f05c9bb-4478-4f7a-a692-e39748c357db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3759927610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3759927610
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1814949962
Short name T187
Test name
Test status
Simulation time 1204791501 ps
CPU time 55.6 seconds
Started Jul 24 06:52:18 PM PDT 24
Finished Jul 24 06:53:14 PM PDT 24
Peak memory 199688 kb
Host smart-c0a078e3-7919-4b05-8501-7c6ad93a0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814949962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1814949962
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3646429425
Short name T70
Test name
Test status
Simulation time 22904205 ps
CPU time 0.58 seconds
Started Jul 24 06:53:14 PM PDT 24
Finished Jul 24 06:53:15 PM PDT 24
Peak memory 195680 kb
Host smart-7fc339f9-913e-4c80-b50c-a486bcbe6f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646429425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3646429425
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2123575731
Short name T474
Test name
Test status
Simulation time 2938286094 ps
CPU time 42.75 seconds
Started Jul 24 06:53:09 PM PDT 24
Finished Jul 24 06:53:52 PM PDT 24
Peak memory 199788 kb
Host smart-34aad96f-cad1-42b6-89c3-f07467744b9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123575731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2123575731
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4261290403
Short name T341
Test name
Test status
Simulation time 402912683 ps
CPU time 21.64 seconds
Started Jul 24 06:53:15 PM PDT 24
Finished Jul 24 06:53:37 PM PDT 24
Peak memory 199732 kb
Host smart-35451ff6-656a-4ae0-8aef-258d6d770c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261290403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4261290403
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2333893986
Short name T232
Test name
Test status
Simulation time 6074014045 ps
CPU time 1241.7 seconds
Started Jul 24 06:53:10 PM PDT 24
Finished Jul 24 07:13:52 PM PDT 24
Peak memory 693552 kb
Host smart-daca4422-54cb-4438-891f-f32c8f783950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333893986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2333893986
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3402650321
Short name T291
Test name
Test status
Simulation time 37571412841 ps
CPU time 172.63 seconds
Started Jul 24 06:53:15 PM PDT 24
Finished Jul 24 06:56:07 PM PDT 24
Peak memory 199656 kb
Host smart-6de69e68-71ac-4b78-8a2f-89bd0fd6c947
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402650321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3402650321
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.376662288
Short name T222
Test name
Test status
Simulation time 177869567 ps
CPU time 3.55 seconds
Started Jul 24 06:53:09 PM PDT 24
Finished Jul 24 06:53:13 PM PDT 24
Peak memory 199604 kb
Host smart-48b4da24-73ca-42a8-869b-8e84f71b2140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376662288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.376662288
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4036913965
Short name T460
Test name
Test status
Simulation time 215796702 ps
CPU time 4.05 seconds
Started Jul 24 06:53:07 PM PDT 24
Finished Jul 24 06:53:12 PM PDT 24
Peak memory 199720 kb
Host smart-52d29685-1cda-45d1-8e68-83bf2e025eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036913965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4036913965
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3728140538
Short name T61
Test name
Test status
Simulation time 140385356897 ps
CPU time 1930.16 seconds
Started Jul 24 06:53:16 PM PDT 24
Finished Jul 24 07:25:26 PM PDT 24
Peak memory 747428 kb
Host smart-ec2e7dc7-d36e-442e-9e9c-99bf996c5913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728140538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3728140538
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.416289190
Short name T43
Test name
Test status
Simulation time 3471632441 ps
CPU time 49.09 seconds
Started Jul 24 06:53:13 PM PDT 24
Finished Jul 24 06:54:02 PM PDT 24
Peak memory 199780 kb
Host smart-aa3659f0-0175-45d2-8b7f-03bce8c42908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416289190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.416289190
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2533766091
Short name T218
Test name
Test status
Simulation time 40087113 ps
CPU time 0.61 seconds
Started Jul 24 06:53:19 PM PDT 24
Finished Jul 24 06:53:20 PM PDT 24
Peak memory 194668 kb
Host smart-38c4d7e9-0a32-4f1a-9ded-2a8329b8915d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533766091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2533766091
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.372043484
Short name T494
Test name
Test status
Simulation time 3413984375 ps
CPU time 47.29 seconds
Started Jul 24 06:53:16 PM PDT 24
Finished Jul 24 06:54:03 PM PDT 24
Peak memory 199808 kb
Host smart-9ea2b810-1a9c-4f8d-a354-734f639744ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372043484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.372043484
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4021970779
Short name T382
Test name
Test status
Simulation time 4760394926 ps
CPU time 60.19 seconds
Started Jul 24 06:53:16 PM PDT 24
Finished Jul 24 06:54:16 PM PDT 24
Peak memory 199816 kb
Host smart-ac55bfa2-7a6d-45ce-9eb0-f064f7bfc612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021970779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4021970779
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2407450863
Short name T512
Test name
Test status
Simulation time 6621043988 ps
CPU time 129.97 seconds
Started Jul 24 06:53:16 PM PDT 24
Finished Jul 24 06:55:26 PM PDT 24
Peak memory 463800 kb
Host smart-f020d92c-64d4-4667-ae6a-db22d0c94c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407450863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2407450863
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4105110587
Short name T371
Test name
Test status
Simulation time 1588509710 ps
CPU time 81.15 seconds
Started Jul 24 06:53:17 PM PDT 24
Finished Jul 24 06:54:38 PM PDT 24
Peak memory 199784 kb
Host smart-09bb4576-9088-4a8d-8802-d8ed193a7ec9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105110587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4105110587
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3745112720
Short name T256
Test name
Test status
Simulation time 9376437695 ps
CPU time 138.11 seconds
Started Jul 24 06:53:14 PM PDT 24
Finished Jul 24 06:55:32 PM PDT 24
Peak memory 199940 kb
Host smart-7010fa62-976e-4342-9307-9aebc56dae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745112720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3745112720
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.797574490
Short name T234
Test name
Test status
Simulation time 4694305191 ps
CPU time 15.1 seconds
Started Jul 24 06:53:15 PM PDT 24
Finished Jul 24 06:53:30 PM PDT 24
Peak memory 199816 kb
Host smart-e84a1432-177d-409e-803d-62b663ebe367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797574490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.797574490
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.686584468
Short name T91
Test name
Test status
Simulation time 216537086744 ps
CPU time 694.81 seconds
Started Jul 24 06:53:19 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 199760 kb
Host smart-8beb973e-5f27-4d31-971d-dccc1e5059b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686584468 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.686584468
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4002272645
Short name T401
Test name
Test status
Simulation time 41074735989 ps
CPU time 132.69 seconds
Started Jul 24 06:53:15 PM PDT 24
Finished Jul 24 06:55:28 PM PDT 24
Peak memory 199836 kb
Host smart-14e720c6-126e-46f2-8312-126900cbe54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002272645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4002272645
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.252662315
Short name T60
Test name
Test status
Simulation time 12364372 ps
CPU time 0.58 seconds
Started Jul 24 06:53:29 PM PDT 24
Finished Jul 24 06:53:30 PM PDT 24
Peak memory 195396 kb
Host smart-1f44b606-a3cc-4831-a5df-8771fe02472d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252662315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.252662315
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.491622185
Short name T299
Test name
Test status
Simulation time 5265904382 ps
CPU time 38.11 seconds
Started Jul 24 06:53:20 PM PDT 24
Finished Jul 24 06:53:58 PM PDT 24
Peak memory 199888 kb
Host smart-4d16807c-1671-4d63-a852-24127600931b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491622185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.491622185
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2782208182
Short name T349
Test name
Test status
Simulation time 3437947071 ps
CPU time 15.25 seconds
Started Jul 24 06:53:23 PM PDT 24
Finished Jul 24 06:53:39 PM PDT 24
Peak memory 199828 kb
Host smart-c801a8f3-a888-44af-b383-ccbc22c5c771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782208182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2782208182
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1695368872
Short name T284
Test name
Test status
Simulation time 5961271708 ps
CPU time 244.56 seconds
Started Jul 24 06:53:25 PM PDT 24
Finished Jul 24 06:57:30 PM PDT 24
Peak memory 584600 kb
Host smart-9634a73f-8ae9-4e48-ad36-a9db82f31306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695368872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1695368872
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3246273557
Short name T320
Test name
Test status
Simulation time 6467803703 ps
CPU time 111.71 seconds
Started Jul 24 06:53:28 PM PDT 24
Finished Jul 24 06:55:19 PM PDT 24
Peak memory 199816 kb
Host smart-c0b6aa8f-21f4-40d2-8248-352522379f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246273557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3246273557
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.155647137
Short name T504
Test name
Test status
Simulation time 4297329902 ps
CPU time 57.82 seconds
Started Jul 24 06:53:20 PM PDT 24
Finished Jul 24 06:54:18 PM PDT 24
Peak memory 199788 kb
Host smart-9426b7b6-50f4-412c-9533-13df154e9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155647137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.155647137
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.200082490
Short name T224
Test name
Test status
Simulation time 268941608 ps
CPU time 4.94 seconds
Started Jul 24 06:53:20 PM PDT 24
Finished Jul 24 06:53:25 PM PDT 24
Peak memory 199696 kb
Host smart-3e9b0e32-3d89-4e43-b6b3-5104541e9008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200082490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.200082490
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2817290343
Short name T473
Test name
Test status
Simulation time 28989390643 ps
CPU time 512.75 seconds
Started Jul 24 06:53:24 PM PDT 24
Finished Jul 24 07:01:57 PM PDT 24
Peak memory 199704 kb
Host smart-12f1f1b0-7fa2-4417-9679-99d4678b9f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817290343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2817290343
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3885740405
Short name T378
Test name
Test status
Simulation time 6454364155 ps
CPU time 106.81 seconds
Started Jul 24 06:53:26 PM PDT 24
Finished Jul 24 06:55:13 PM PDT 24
Peak memory 199784 kb
Host smart-8417cb87-6391-4709-8065-2cf13dc770a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885740405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3885740405
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3571142880
Short name T440
Test name
Test status
Simulation time 12387031 ps
CPU time 0.6 seconds
Started Jul 24 06:53:36 PM PDT 24
Finished Jul 24 06:53:37 PM PDT 24
Peak memory 195732 kb
Host smart-110c4f93-d92b-4988-a159-8538ad557046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571142880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3571142880
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3682836807
Short name T444
Test name
Test status
Simulation time 1680781291 ps
CPU time 49.01 seconds
Started Jul 24 06:53:31 PM PDT 24
Finished Jul 24 06:54:20 PM PDT 24
Peak memory 199712 kb
Host smart-82b7276d-76f5-48b5-8bee-39c81a31d0a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682836807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3682836807
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4256484665
Short name T431
Test name
Test status
Simulation time 13567551177 ps
CPU time 52.51 seconds
Started Jul 24 06:53:35 PM PDT 24
Finished Jul 24 06:54:27 PM PDT 24
Peak memory 199900 kb
Host smart-a8f650a8-747d-47b0-9aa0-43d3108d2c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256484665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4256484665
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1318514290
Short name T446
Test name
Test status
Simulation time 10714310104 ps
CPU time 485.8 seconds
Started Jul 24 06:53:31 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 669444 kb
Host smart-0e1ad7a1-c5e5-47b0-a2eb-22a8eba19ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318514290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1318514290
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.89631973
Short name T248
Test name
Test status
Simulation time 8004575991 ps
CPU time 132.38 seconds
Started Jul 24 06:53:35 PM PDT 24
Finished Jul 24 06:55:47 PM PDT 24
Peak memory 199804 kb
Host smart-db691f91-5ba4-4b1e-85f4-3d7fe00488dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89631973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.89631973
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1595449455
Short name T488
Test name
Test status
Simulation time 22571976827 ps
CPU time 138.39 seconds
Started Jul 24 06:53:29 PM PDT 24
Finished Jul 24 06:55:48 PM PDT 24
Peak memory 199860 kb
Host smart-b9a35a06-354a-4bd4-bf5d-a7b58961f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595449455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1595449455
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3579461172
Short name T344
Test name
Test status
Simulation time 134578740 ps
CPU time 1.39 seconds
Started Jul 24 06:53:30 PM PDT 24
Finished Jul 24 06:53:32 PM PDT 24
Peak memory 199768 kb
Host smart-90bf5632-60a5-4cf0-b615-c2a797908ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579461172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3579461172
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.161165201
Short name T47
Test name
Test status
Simulation time 281934476119 ps
CPU time 3367.94 seconds
Started Jul 24 06:53:34 PM PDT 24
Finished Jul 24 07:49:43 PM PDT 24
Peak memory 818644 kb
Host smart-3d53c11a-d92d-4a7d-9f3e-f393ce429318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161165201 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.161165201
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3577501264
Short name T162
Test name
Test status
Simulation time 584072498 ps
CPU time 32.07 seconds
Started Jul 24 06:53:36 PM PDT 24
Finished Jul 24 06:54:08 PM PDT 24
Peak memory 199740 kb
Host smart-21cef66d-9008-4a84-b810-67b01aca30c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577501264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3577501264
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2975385652
Short name T515
Test name
Test status
Simulation time 25505854 ps
CPU time 0.55 seconds
Started Jul 24 06:53:43 PM PDT 24
Finished Jul 24 06:53:44 PM PDT 24
Peak memory 194616 kb
Host smart-24778fc1-b282-4bb2-802b-cc921d37d15f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975385652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2975385652
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2162919756
Short name T511
Test name
Test status
Simulation time 292033834 ps
CPU time 17.86 seconds
Started Jul 24 06:53:35 PM PDT 24
Finished Jul 24 06:53:53 PM PDT 24
Peak memory 199576 kb
Host smart-cb7bea83-507a-4d1e-9ac1-1f749eb9a358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162919756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2162919756
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3704565800
Short name T37
Test name
Test status
Simulation time 35929086 ps
CPU time 1.99 seconds
Started Jul 24 06:53:43 PM PDT 24
Finished Jul 24 06:53:45 PM PDT 24
Peak memory 199688 kb
Host smart-bf32daef-19a7-4d62-82bc-4b9febbde8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704565800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3704565800
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3170834671
Short name T500
Test name
Test status
Simulation time 179991122 ps
CPU time 14.64 seconds
Started Jul 24 06:53:35 PM PDT 24
Finished Jul 24 06:53:50 PM PDT 24
Peak memory 224168 kb
Host smart-7ef15121-958a-4cd7-9ca9-4ca0970b55f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170834671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3170834671
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2389438419
Short name T194
Test name
Test status
Simulation time 1045031289 ps
CPU time 5.31 seconds
Started Jul 24 06:53:42 PM PDT 24
Finished Jul 24 06:53:47 PM PDT 24
Peak memory 199680 kb
Host smart-09dedd55-cd6c-47b7-a81f-4766b385072f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389438419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2389438419
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3754291243
Short name T210
Test name
Test status
Simulation time 63669680232 ps
CPU time 198.27 seconds
Started Jul 24 06:53:36 PM PDT 24
Finished Jul 24 06:56:54 PM PDT 24
Peak memory 199824 kb
Host smart-12314847-2c0b-40f2-a809-8b4c2dd78cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754291243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3754291243
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2122754829
Short name T92
Test name
Test status
Simulation time 295049306 ps
CPU time 5.29 seconds
Started Jul 24 06:53:35 PM PDT 24
Finished Jul 24 06:53:40 PM PDT 24
Peak memory 199728 kb
Host smart-ec3ed64b-c9aa-455f-b406-9eab91094069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122754829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2122754829
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.139008801
Short name T414
Test name
Test status
Simulation time 39673964172 ps
CPU time 266.27 seconds
Started Jul 24 06:53:40 PM PDT 24
Finished Jul 24 06:58:07 PM PDT 24
Peak memory 622048 kb
Host smart-b8a039ea-3b41-4f49-8f89-170ee2f1838b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139008801 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.139008801
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2668947502
Short name T409
Test name
Test status
Simulation time 134525413 ps
CPU time 7.4 seconds
Started Jul 24 06:53:41 PM PDT 24
Finished Jul 24 06:53:49 PM PDT 24
Peak memory 199736 kb
Host smart-fd7c12e2-ed80-4e9c-8927-e05b886a323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668947502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2668947502
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1960719276
Short name T432
Test name
Test status
Simulation time 23164922 ps
CPU time 0.54 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 06:53:46 PM PDT 24
Peak memory 194500 kb
Host smart-9e27f4f0-03c5-4101-b653-70a2cbf0c1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960719276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1960719276
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1802531812
Short name T280
Test name
Test status
Simulation time 117292942 ps
CPU time 6.92 seconds
Started Jul 24 06:53:43 PM PDT 24
Finished Jul 24 06:53:50 PM PDT 24
Peak memory 199544 kb
Host smart-cc2f693c-0062-4258-abc0-32297832eee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802531812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1802531812
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1632669545
Short name T520
Test name
Test status
Simulation time 11902852781 ps
CPU time 50.12 seconds
Started Jul 24 06:53:43 PM PDT 24
Finished Jul 24 06:54:34 PM PDT 24
Peak memory 199676 kb
Host smart-04f91be5-bc4c-40e7-801f-d7939e6e9b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632669545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1632669545
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2805778744
Short name T182
Test name
Test status
Simulation time 14553634781 ps
CPU time 556.63 seconds
Started Jul 24 06:53:42 PM PDT 24
Finished Jul 24 07:02:59 PM PDT 24
Peak memory 513396 kb
Host smart-b3b598b3-a5ab-437f-b620-695e171af415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805778744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2805778744
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1452841741
Short name T338
Test name
Test status
Simulation time 154348911170 ps
CPU time 210.52 seconds
Started Jul 24 06:53:42 PM PDT 24
Finished Jul 24 06:57:13 PM PDT 24
Peak memory 199760 kb
Host smart-a58fad57-08bd-41c1-9733-cf87e2816596
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452841741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1452841741
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1630963969
Short name T97
Test name
Test status
Simulation time 8260396531 ps
CPU time 99.46 seconds
Started Jul 24 06:53:48 PM PDT 24
Finished Jul 24 06:55:28 PM PDT 24
Peak memory 199748 kb
Host smart-ad2c5a55-cf02-41d0-8998-3f45d4ecf97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630963969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1630963969
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1435594865
Short name T11
Test name
Test status
Simulation time 359262106 ps
CPU time 5.17 seconds
Started Jul 24 06:53:40 PM PDT 24
Finished Jul 24 06:53:46 PM PDT 24
Peak memory 199672 kb
Host smart-2085049d-316b-4e5f-b463-1cb400d4e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435594865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1435594865
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.538525171
Short name T104
Test name
Test status
Simulation time 12526358904 ps
CPU time 35.95 seconds
Started Jul 24 06:53:46 PM PDT 24
Finished Jul 24 06:54:22 PM PDT 24
Peak memory 199828 kb
Host smart-32163e53-89dc-43a4-aa03-9844b4a6cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538525171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.538525171
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1864973621
Short name T518
Test name
Test status
Simulation time 32084662 ps
CPU time 0.58 seconds
Started Jul 24 06:53:49 PM PDT 24
Finished Jul 24 06:53:50 PM PDT 24
Peak memory 196388 kb
Host smart-b97bb518-4828-472e-9957-1b6c6880a86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864973621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1864973621
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2447181291
Short name T42
Test name
Test status
Simulation time 4530699086 ps
CPU time 64.55 seconds
Started Jul 24 06:53:48 PM PDT 24
Finished Jul 24 06:54:53 PM PDT 24
Peak memory 216056 kb
Host smart-a09f4c54-5c56-42ad-8c9c-868ba1f92e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447181291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2447181291
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1197351921
Short name T461
Test name
Test status
Simulation time 1543252974 ps
CPU time 50.44 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 06:54:36 PM PDT 24
Peak memory 199604 kb
Host smart-aa182fc0-d700-442b-9435-599023f55b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197351921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1197351921
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2375801749
Short name T319
Test name
Test status
Simulation time 11504084761 ps
CPU time 1097.67 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 07:12:03 PM PDT 24
Peak memory 722856 kb
Host smart-2c82065b-9c86-4276-aa56-0b0d02183f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375801749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2375801749
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2245944201
Short name T315
Test name
Test status
Simulation time 45551454278 ps
CPU time 164.14 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 06:56:30 PM PDT 24
Peak memory 199820 kb
Host smart-652ecad0-7469-4607-9d79-bbc292b79dde
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245944201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2245944201
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1370814783
Short name T257
Test name
Test status
Simulation time 31238693292 ps
CPU time 100.83 seconds
Started Jul 24 06:53:49 PM PDT 24
Finished Jul 24 06:55:30 PM PDT 24
Peak memory 199800 kb
Host smart-dc52c2f0-d709-4452-b9a1-c71a94d9bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370814783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1370814783
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1010574878
Short name T471
Test name
Test status
Simulation time 66319602 ps
CPU time 3.23 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 06:53:49 PM PDT 24
Peak memory 199748 kb
Host smart-29a11e03-34c9-4452-8892-2a7a308f044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010574878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1010574878
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3021791947
Short name T501
Test name
Test status
Simulation time 100154613124 ps
CPU time 309.77 seconds
Started Jul 24 06:53:46 PM PDT 24
Finished Jul 24 06:58:56 PM PDT 24
Peak memory 199780 kb
Host smart-9e7405d0-2386-4599-9e3a-6c6a43320f6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021791947 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3021791947
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1063345943
Short name T331
Test name
Test status
Simulation time 1488989233 ps
CPU time 66.39 seconds
Started Jul 24 06:53:46 PM PDT 24
Finished Jul 24 06:54:52 PM PDT 24
Peak memory 199732 kb
Host smart-7cf93d24-a3ba-4524-8efe-d42853b3d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063345943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1063345943
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1116001536
Short name T346
Test name
Test status
Simulation time 22259299 ps
CPU time 0.59 seconds
Started Jul 24 06:53:52 PM PDT 24
Finished Jul 24 06:53:52 PM PDT 24
Peak memory 195316 kb
Host smart-897ffffd-99fc-4488-b61e-99b6295bd5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116001536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1116001536
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3170547867
Short name T18
Test name
Test status
Simulation time 2764213853 ps
CPU time 75.34 seconds
Started Jul 24 06:53:51 PM PDT 24
Finished Jul 24 06:55:06 PM PDT 24
Peak memory 199800 kb
Host smart-68efe192-1dea-47ff-abd8-f108c6a9ea35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170547867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3170547867
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1234407359
Short name T337
Test name
Test status
Simulation time 1062098139 ps
CPU time 3.92 seconds
Started Jul 24 06:53:53 PM PDT 24
Finished Jul 24 06:53:57 PM PDT 24
Peak memory 199724 kb
Host smart-183c6b01-445b-4294-ba36-606b1f26a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234407359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1234407359
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2134614784
Short name T387
Test name
Test status
Simulation time 8031151980 ps
CPU time 801.35 seconds
Started Jul 24 06:53:51 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 720184 kb
Host smart-e1aea29c-79ce-446a-91e3-e7d3b8bb8381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134614784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2134614784
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3619330304
Short name T58
Test name
Test status
Simulation time 54551074325 ps
CPU time 102.21 seconds
Started Jul 24 06:53:51 PM PDT 24
Finished Jul 24 06:55:34 PM PDT 24
Peak memory 199752 kb
Host smart-5e58286c-fbd3-4c22-8388-af86b8994a5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619330304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3619330304
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4023470157
Short name T377
Test name
Test status
Simulation time 2801317543 ps
CPU time 49.22 seconds
Started Jul 24 06:53:52 PM PDT 24
Finished Jul 24 06:54:41 PM PDT 24
Peak memory 199740 kb
Host smart-17f21c76-fd0c-496c-bb32-376afc17a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023470157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4023470157
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3769777626
Short name T186
Test name
Test status
Simulation time 232336962 ps
CPU time 5.31 seconds
Started Jul 24 06:53:45 PM PDT 24
Finished Jul 24 06:53:50 PM PDT 24
Peak memory 199736 kb
Host smart-4628fa06-8d0a-44b0-b15d-97c906f21492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769777626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3769777626
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.469332513
Short name T357
Test name
Test status
Simulation time 11073488921 ps
CPU time 67.74 seconds
Started Jul 24 06:53:52 PM PDT 24
Finished Jul 24 06:55:00 PM PDT 24
Peak memory 199852 kb
Host smart-08bd1d48-a8da-469d-b029-f2fe4a65be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469332513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.469332513
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.481029812
Short name T171
Test name
Test status
Simulation time 11509004 ps
CPU time 0.6 seconds
Started Jul 24 06:53:58 PM PDT 24
Finished Jul 24 06:53:59 PM PDT 24
Peak memory 195720 kb
Host smart-a395a529-a56c-4111-8743-4f0da1a0d138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481029812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.481029812
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3752805838
Short name T32
Test name
Test status
Simulation time 1838543987 ps
CPU time 26.24 seconds
Started Jul 24 06:53:58 PM PDT 24
Finished Jul 24 06:54:24 PM PDT 24
Peak memory 199720 kb
Host smart-259290b8-5e44-42ae-975f-89d6d5a0b8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752805838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3752805838
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2937609757
Short name T415
Test name
Test status
Simulation time 5793213591 ps
CPU time 54.22 seconds
Started Jul 24 06:54:00 PM PDT 24
Finished Jul 24 06:54:54 PM PDT 24
Peak memory 199864 kb
Host smart-2095748b-b5ab-4446-a03b-9eaa0c833271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937609757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2937609757
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.48990389
Short name T298
Test name
Test status
Simulation time 6808581656 ps
CPU time 400.01 seconds
Started Jul 24 06:53:57 PM PDT 24
Finished Jul 24 07:00:37 PM PDT 24
Peak memory 658248 kb
Host smart-7df106c7-15ef-41b8-8aa3-ef9333a5696d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48990389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.48990389
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2042602596
Short name T505
Test name
Test status
Simulation time 104176786002 ps
CPU time 259.97 seconds
Started Jul 24 06:54:04 PM PDT 24
Finished Jul 24 06:58:24 PM PDT 24
Peak memory 199772 kb
Host smart-4f33ed42-b1be-42d4-99bd-5a4cbb530238
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042602596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2042602596
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3111726901
Short name T312
Test name
Test status
Simulation time 33272135165 ps
CPU time 75.6 seconds
Started Jul 24 06:53:52 PM PDT 24
Finished Jul 24 06:55:08 PM PDT 24
Peak memory 199800 kb
Host smart-bec66666-6d20-4126-88e1-098c7021e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111726901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3111726901
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.915998348
Short name T466
Test name
Test status
Simulation time 1674926684 ps
CPU time 4.45 seconds
Started Jul 24 06:53:53 PM PDT 24
Finished Jul 24 06:53:58 PM PDT 24
Peak memory 199712 kb
Host smart-0efd6d5b-d8ae-4644-baf9-bf3acd19f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915998348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.915998348
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.126191929
Short name T99
Test name
Test status
Simulation time 135406675492 ps
CPU time 2103.57 seconds
Started Jul 24 06:53:59 PM PDT 24
Finished Jul 24 07:29:02 PM PDT 24
Peak memory 765268 kb
Host smart-0c371a87-1d7a-4a21-ab22-47341f4a8f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126191929 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.126191929
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3916278841
Short name T215
Test name
Test status
Simulation time 1809558478 ps
CPU time 32.06 seconds
Started Jul 24 06:53:57 PM PDT 24
Finished Jul 24 06:54:30 PM PDT 24
Peak memory 199712 kb
Host smart-64bea62b-2390-454a-9d5d-db448c79ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916278841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3916278841
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.78676488
Short name T247
Test name
Test status
Simulation time 36559128 ps
CPU time 0.6 seconds
Started Jul 24 06:54:06 PM PDT 24
Finished Jul 24 06:54:06 PM PDT 24
Peak memory 194720 kb
Host smart-73ab0b4b-fa70-4e83-90ce-2559a2f9d089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78676488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.78676488
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.872685481
Short name T233
Test name
Test status
Simulation time 588692308 ps
CPU time 5.08 seconds
Started Jul 24 06:54:05 PM PDT 24
Finished Jul 24 06:54:10 PM PDT 24
Peak memory 199704 kb
Host smart-03aa9acd-a038-4b79-8f2c-0f254bc7929f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872685481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.872685481
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.885994099
Short name T214
Test name
Test status
Simulation time 9260412694 ps
CPU time 29.59 seconds
Started Jul 24 06:54:04 PM PDT 24
Finished Jul 24 06:54:34 PM PDT 24
Peak memory 216160 kb
Host smart-f26e88e1-05f8-4019-9848-d953b66b843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885994099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.885994099
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1313876958
Short name T155
Test name
Test status
Simulation time 15443136049 ps
CPU time 502.67 seconds
Started Jul 24 06:54:02 PM PDT 24
Finished Jul 24 07:02:25 PM PDT 24
Peak memory 654640 kb
Host smart-ac079e10-856c-4214-9861-73e17ed08d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313876958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1313876958
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.376773296
Short name T102
Test name
Test status
Simulation time 980012440 ps
CPU time 4.88 seconds
Started Jul 24 06:54:03 PM PDT 24
Finished Jul 24 06:54:08 PM PDT 24
Peak memory 199684 kb
Host smart-155b54dc-1e8a-45e3-9ae1-7e9df495df11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376773296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.376773296
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2193910444
Short name T205
Test name
Test status
Simulation time 7255280970 ps
CPU time 109.45 seconds
Started Jul 24 06:53:59 PM PDT 24
Finished Jul 24 06:55:48 PM PDT 24
Peak memory 199696 kb
Host smart-264dc0e9-d56e-421f-9cf5-e445b9fef00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193910444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2193910444
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2627633932
Short name T276
Test name
Test status
Simulation time 950629072 ps
CPU time 3.28 seconds
Started Jul 24 06:53:59 PM PDT 24
Finished Jul 24 06:54:02 PM PDT 24
Peak memory 199668 kb
Host smart-075762ac-02ae-4262-b06d-dc64432b063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627633932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2627633932
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3664424890
Short name T133
Test name
Test status
Simulation time 3494291947 ps
CPU time 66.52 seconds
Started Jul 24 06:54:02 PM PDT 24
Finished Jul 24 06:55:08 PM PDT 24
Peak memory 216100 kb
Host smart-9bf49030-fefd-4b2a-a4e3-e835b6e98532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664424890 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3664424890
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.470232559
Short name T480
Test name
Test status
Simulation time 794360498 ps
CPU time 42.12 seconds
Started Jul 24 06:54:03 PM PDT 24
Finished Jul 24 06:54:45 PM PDT 24
Peak memory 199756 kb
Host smart-0cb7ad05-3316-4332-baec-b1dce49843a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470232559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.470232559
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1107424723
Short name T39
Test name
Test status
Simulation time 29592032 ps
CPU time 0.57 seconds
Started Jul 24 06:52:31 PM PDT 24
Finished Jul 24 06:52:32 PM PDT 24
Peak memory 195344 kb
Host smart-6ad2d21b-94a6-4626-83a0-0b9f2d644d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107424723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1107424723
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3054413072
Short name T246
Test name
Test status
Simulation time 1213879676 ps
CPU time 16.84 seconds
Started Jul 24 06:52:22 PM PDT 24
Finished Jul 24 06:52:39 PM PDT 24
Peak memory 199708 kb
Host smart-29c0aeec-c13a-47f5-ba0d-99bc3c488cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054413072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3054413072
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.687640070
Short name T27
Test name
Test status
Simulation time 3313497925 ps
CPU time 43.58 seconds
Started Jul 24 06:52:27 PM PDT 24
Finished Jul 24 06:53:11 PM PDT 24
Peak memory 199848 kb
Host smart-c7fe9332-f49b-497e-8489-bc18511563ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687640070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.687640070
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.145871309
Short name T388
Test name
Test status
Simulation time 2262327422 ps
CPU time 382.48 seconds
Started Jul 24 06:52:25 PM PDT 24
Finished Jul 24 06:58:48 PM PDT 24
Peak memory 676012 kb
Host smart-173a3efb-f557-4d7b-9ca4-9a1ce0a723bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145871309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.145871309
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4289059896
Short name T251
Test name
Test status
Simulation time 26863778481 ps
CPU time 165.06 seconds
Started Jul 24 06:52:28 PM PDT 24
Finished Jul 24 06:55:13 PM PDT 24
Peak memory 199788 kb
Host smart-97498c83-0b5c-4e64-9953-8b08f57d1e31
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289059896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4289059896
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.828884712
Short name T161
Test name
Test status
Simulation time 145454305 ps
CPU time 7.75 seconds
Started Jul 24 06:52:25 PM PDT 24
Finished Jul 24 06:52:33 PM PDT 24
Peak memory 199776 kb
Host smart-32e14156-975f-413b-a4a9-3392b425d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828884712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.828884712
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3073698822
Short name T64
Test name
Test status
Simulation time 115263592 ps
CPU time 0.95 seconds
Started Jul 24 06:52:37 PM PDT 24
Finished Jul 24 06:52:38 PM PDT 24
Peak memory 218332 kb
Host smart-1b91bffa-2f80-466a-b411-958ee6d1a5dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073698822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3073698822
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1420303438
Short name T46
Test name
Test status
Simulation time 3977684078 ps
CPU time 12.57 seconds
Started Jul 24 06:52:25 PM PDT 24
Finished Jul 24 06:52:38 PM PDT 24
Peak memory 199768 kb
Host smart-9d5d3b8a-b6f4-4a9b-ab8f-f355fc096328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420303438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1420303438
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4116208074
Short name T419
Test name
Test status
Simulation time 133897643583 ps
CPU time 4423.22 seconds
Started Jul 24 06:52:32 PM PDT 24
Finished Jul 24 08:06:16 PM PDT 24
Peak memory 825240 kb
Host smart-bffe926f-95dd-492c-a942-914347c2d917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116208074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4116208074
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.395440038
Short name T9
Test name
Test status
Simulation time 29089872975 ps
CPU time 1838.48 seconds
Started Jul 24 06:52:30 PM PDT 24
Finished Jul 24 07:23:09 PM PDT 24
Peak memory 649660 kb
Host smart-abfa6ec1-2cde-432a-b6b7-bc8247049d45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395440038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.395440038
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3824299896
Short name T345
Test name
Test status
Simulation time 2608283256 ps
CPU time 42.48 seconds
Started Jul 24 06:52:31 PM PDT 24
Finished Jul 24 06:53:13 PM PDT 24
Peak memory 199780 kb
Host smart-c684bba3-1312-4b4a-93dd-aaa9d4ded534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3824299896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3824299896
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2016799451
Short name T68
Test name
Test status
Simulation time 6714707267 ps
CPU time 52.84 seconds
Started Jul 24 06:52:30 PM PDT 24
Finished Jul 24 06:53:23 PM PDT 24
Peak memory 199800 kb
Host smart-177b4e49-e175-42c3-8025-e4d515fd9038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2016799451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2016799451
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1490396725
Short name T188
Test name
Test status
Simulation time 11876429227 ps
CPU time 112.23 seconds
Started Jul 24 06:52:38 PM PDT 24
Finished Jul 24 06:54:31 PM PDT 24
Peak memory 199872 kb
Host smart-0b8adea9-efce-45f9-8838-050faea5033e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1490396725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1490396725
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3998853513
Short name T35
Test name
Test status
Simulation time 39980368974 ps
CPU time 687.5 seconds
Started Jul 24 06:52:27 PM PDT 24
Finished Jul 24 07:03:55 PM PDT 24
Peak memory 199808 kb
Host smart-829da62d-d92b-4873-aaea-9468716d399f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3998853513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3998853513
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1404356398
Short name T428
Test name
Test status
Simulation time 141406069420 ps
CPU time 2320.85 seconds
Started Jul 24 06:52:29 PM PDT 24
Finished Jul 24 07:31:10 PM PDT 24
Peak memory 208016 kb
Host smart-733d0491-dcc9-493b-9461-10754cc92173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1404356398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1404356398
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.90330731
Short name T379
Test name
Test status
Simulation time 276189156113 ps
CPU time 2296.66 seconds
Started Jul 24 06:52:36 PM PDT 24
Finished Jul 24 07:30:53 PM PDT 24
Peak memory 215300 kb
Host smart-a7cadbbe-e489-4463-a6a4-25640ebd8bbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=90330731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.90330731
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3216458751
Short name T72
Test name
Test status
Simulation time 8978854129 ps
CPU time 59.47 seconds
Started Jul 24 06:52:22 PM PDT 24
Finished Jul 24 06:53:22 PM PDT 24
Peak memory 199760 kb
Host smart-1dbd6568-d473-4239-8cc4-dcecf3540c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216458751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3216458751
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4073806315
Short name T175
Test name
Test status
Simulation time 12378576 ps
CPU time 0.59 seconds
Started Jul 24 06:54:19 PM PDT 24
Finished Jul 24 06:54:20 PM PDT 24
Peak memory 194684 kb
Host smart-8311ae99-e2a8-4d24-92e0-8f00b39490ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073806315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4073806315
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2132425598
Short name T394
Test name
Test status
Simulation time 930996177 ps
CPU time 54.91 seconds
Started Jul 24 06:54:11 PM PDT 24
Finished Jul 24 06:55:06 PM PDT 24
Peak memory 199776 kb
Host smart-adec71f6-6306-46dc-93e5-c97e00d8960b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132425598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2132425598
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1496264758
Short name T4
Test name
Test status
Simulation time 4341482110 ps
CPU time 13.03 seconds
Started Jul 24 06:54:11 PM PDT 24
Finished Jul 24 06:54:25 PM PDT 24
Peak memory 199756 kb
Host smart-0cb06650-36d7-42e9-8836-5d9f2c442bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496264758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1496264758
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4273118648
Short name T289
Test name
Test status
Simulation time 1927020062 ps
CPU time 128.26 seconds
Started Jul 24 06:54:10 PM PDT 24
Finished Jul 24 06:56:19 PM PDT 24
Peak memory 325788 kb
Host smart-d82df7ec-8566-475d-9b99-db412f1ef62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273118648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4273118648
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1168315642
Short name T508
Test name
Test status
Simulation time 8853280450 ps
CPU time 244.94 seconds
Started Jul 24 06:54:16 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 199772 kb
Host smart-a47637ba-2c1a-485f-ba9c-6c89aa8c31e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168315642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1168315642
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3558353151
Short name T283
Test name
Test status
Simulation time 23355957847 ps
CPU time 163.34 seconds
Started Jul 24 06:54:10 PM PDT 24
Finished Jul 24 06:56:54 PM PDT 24
Peak memory 199832 kb
Host smart-84601c42-d607-45ab-8aaa-8cea334d81f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558353151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3558353151
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1172368911
Short name T81
Test name
Test status
Simulation time 250823248 ps
CPU time 9.76 seconds
Started Jul 24 06:54:06 PM PDT 24
Finished Jul 24 06:54:16 PM PDT 24
Peak memory 199700 kb
Host smart-41ef70bc-dd6f-427e-9217-7434c54810c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172368911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1172368911
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.649169997
Short name T107
Test name
Test status
Simulation time 6643916210 ps
CPU time 363.14 seconds
Started Jul 24 06:54:17 PM PDT 24
Finished Jul 24 07:00:20 PM PDT 24
Peak memory 199800 kb
Host smart-b22360b0-7617-4257-8cfd-4febd10153af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649169997 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.649169997
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3159033304
Short name T510
Test name
Test status
Simulation time 40751359008 ps
CPU time 71.8 seconds
Started Jul 24 06:54:17 PM PDT 24
Finished Jul 24 06:55:29 PM PDT 24
Peak memory 199816 kb
Host smart-fc034e4d-829b-4932-9825-c0f04b042db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159033304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3159033304
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2250452973
Short name T163
Test name
Test status
Simulation time 43722947 ps
CPU time 0.59 seconds
Started Jul 24 06:54:24 PM PDT 24
Finished Jul 24 06:54:25 PM PDT 24
Peak memory 195748 kb
Host smart-cae8fc5d-3caf-4570-95e3-0b120be114bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250452973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2250452973
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2737915317
Short name T343
Test name
Test status
Simulation time 5250135530 ps
CPU time 70.48 seconds
Started Jul 24 06:54:17 PM PDT 24
Finished Jul 24 06:55:28 PM PDT 24
Peak memory 208112 kb
Host smart-458d9717-0a1c-407f-9713-caa0170c558e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737915317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2737915317
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2043173447
Short name T453
Test name
Test status
Simulation time 9865135795 ps
CPU time 45.8 seconds
Started Jul 24 06:54:16 PM PDT 24
Finished Jul 24 06:55:02 PM PDT 24
Peak memory 199700 kb
Host smart-29de739c-9011-4128-a6ea-43702e521049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043173447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2043173447
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3318773373
Short name T517
Test name
Test status
Simulation time 4114619461 ps
CPU time 120.97 seconds
Started Jul 24 06:54:16 PM PDT 24
Finished Jul 24 06:56:18 PM PDT 24
Peak memory 330852 kb
Host smart-c79e66cb-e9da-4471-be63-d3aa07be7078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318773373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3318773373
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3485749464
Short name T405
Test name
Test status
Simulation time 33676887 ps
CPU time 0.69 seconds
Started Jul 24 06:54:16 PM PDT 24
Finished Jul 24 06:54:17 PM PDT 24
Peak memory 196184 kb
Host smart-c6459954-7173-423b-9c9f-0512b106b732
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485749464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3485749464
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2881760388
Short name T507
Test name
Test status
Simulation time 1749793125 ps
CPU time 24.83 seconds
Started Jul 24 06:54:22 PM PDT 24
Finished Jul 24 06:54:47 PM PDT 24
Peak memory 199688 kb
Host smart-e03ab2ac-bef5-45b0-b9b3-8d20a48f8be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881760388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2881760388
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2780907741
Short name T442
Test name
Test status
Simulation time 9639058950 ps
CPU time 12.66 seconds
Started Jul 24 06:54:18 PM PDT 24
Finished Jul 24 06:54:31 PM PDT 24
Peak memory 199872 kb
Host smart-5a09dfd0-d2d1-4ac9-b629-6e7c0714f191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780907741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2780907741
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1721110739
Short name T287
Test name
Test status
Simulation time 33136172712 ps
CPU time 842.35 seconds
Started Jul 24 06:54:27 PM PDT 24
Finished Jul 24 07:08:29 PM PDT 24
Peak memory 648888 kb
Host smart-312e7aec-c633-40c7-bc63-10e118ec8b53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721110739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1721110739
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1070909884
Short name T438
Test name
Test status
Simulation time 11925410440 ps
CPU time 106.35 seconds
Started Jul 24 06:54:16 PM PDT 24
Finished Jul 24 06:56:03 PM PDT 24
Peak memory 199832 kb
Host smart-aad4a99a-4f28-4e6e-98b6-24fe108a54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070909884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1070909884
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3860261054
Short name T238
Test name
Test status
Simulation time 39751426 ps
CPU time 0.58 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:54:27 PM PDT 24
Peak memory 196276 kb
Host smart-32ae8393-0226-4c50-917f-901b1c1de3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860261054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3860261054
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3854663280
Short name T273
Test name
Test status
Simulation time 87199866 ps
CPU time 5.14 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:54:32 PM PDT 24
Peak memory 199612 kb
Host smart-ee96943e-9990-43ab-bf13-304c04a2ca50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854663280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3854663280
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.792020235
Short name T481
Test name
Test status
Simulation time 6524900027 ps
CPU time 29.36 seconds
Started Jul 24 06:54:34 PM PDT 24
Finished Jul 24 06:55:04 PM PDT 24
Peak memory 207984 kb
Host smart-4dbc3177-2be8-49bf-a741-40ff6b198762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792020235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.792020235
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3213051341
Short name T217
Test name
Test status
Simulation time 2169683922 ps
CPU time 336.09 seconds
Started Jul 24 06:54:25 PM PDT 24
Finished Jul 24 07:00:01 PM PDT 24
Peak memory 475076 kb
Host smart-803fc87b-711c-4665-af8b-0792aee1547d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213051341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3213051341
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1034131522
Short name T333
Test name
Test status
Simulation time 1808346467 ps
CPU time 98.35 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:56:05 PM PDT 24
Peak memory 199688 kb
Host smart-e4471d8b-0630-4d22-9db5-580eef3ad9b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034131522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1034131522
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2261052279
Short name T279
Test name
Test status
Simulation time 5475940982 ps
CPU time 161.29 seconds
Started Jul 24 06:54:35 PM PDT 24
Finished Jul 24 06:57:16 PM PDT 24
Peak memory 199772 kb
Host smart-a98c1958-7c5e-4376-8d7c-862bdd5fa9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261052279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2261052279
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1191226256
Short name T245
Test name
Test status
Simulation time 640640275 ps
CPU time 10.78 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:54:37 PM PDT 24
Peak memory 199732 kb
Host smart-8bd8de4e-80c7-44e3-ac61-e10877300f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191226256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1191226256
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2305239661
Short name T486
Test name
Test status
Simulation time 73091618548 ps
CPU time 1297.8 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 07:16:05 PM PDT 24
Peak memory 762260 kb
Host smart-e3434235-e131-4582-967d-a0dc2c0c7a5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305239661 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2305239661
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3179388257
Short name T132
Test name
Test status
Simulation time 2634438054 ps
CPU time 49.14 seconds
Started Jul 24 06:54:25 PM PDT 24
Finished Jul 24 06:55:15 PM PDT 24
Peak memory 199868 kb
Host smart-6939cf90-ac4d-4dde-8546-729ebebd66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179388257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3179388257
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4044198391
Short name T374
Test name
Test status
Simulation time 39557198 ps
CPU time 0.58 seconds
Started Jul 24 06:54:35 PM PDT 24
Finished Jul 24 06:54:36 PM PDT 24
Peak memory 194728 kb
Host smart-a1925b1e-3084-4d14-9b7d-f85f99fece62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044198391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4044198391
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3999322669
Short name T212
Test name
Test status
Simulation time 4267696878 ps
CPU time 33.04 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:54:59 PM PDT 24
Peak memory 199724 kb
Host smart-c4b84d96-47ac-4321-9ec5-7c1291593ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999322669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3999322669
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2744071823
Short name T389
Test name
Test status
Simulation time 11985292683 ps
CPU time 37.49 seconds
Started Jul 24 06:54:31 PM PDT 24
Finished Jul 24 06:55:09 PM PDT 24
Peak memory 199784 kb
Host smart-8d4564b0-dac9-4bf5-bae1-c1ca7e7daaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744071823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2744071823
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1058491833
Short name T170
Test name
Test status
Simulation time 2555791440 ps
CPU time 79.15 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:55:46 PM PDT 24
Peak memory 414820 kb
Host smart-afd57dd9-2386-448a-9270-59139ccd0fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058491833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1058491833
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.85297856
Short name T351
Test name
Test status
Simulation time 2648502500 ps
CPU time 49.65 seconds
Started Jul 24 06:54:33 PM PDT 24
Finished Jul 24 06:55:23 PM PDT 24
Peak memory 199812 kb
Host smart-b5806d24-b92a-4b64-b8f8-50ccf1f189c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85297856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.85297856
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3684436117
Short name T513
Test name
Test status
Simulation time 2550754155 ps
CPU time 46.44 seconds
Started Jul 24 06:54:27 PM PDT 24
Finished Jul 24 06:55:14 PM PDT 24
Peak memory 199816 kb
Host smart-ab0d4761-88be-4606-b021-a51650593eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684436117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3684436117
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.575977650
Short name T356
Test name
Test status
Simulation time 1641886299 ps
CPU time 14.57 seconds
Started Jul 24 06:54:26 PM PDT 24
Finished Jul 24 06:54:41 PM PDT 24
Peak memory 199588 kb
Host smart-27531da3-ffa1-4c1a-893c-bd5cb23e6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575977650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.575977650
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4262530523
Short name T88
Test name
Test status
Simulation time 156598600302 ps
CPU time 972.11 seconds
Started Jul 24 06:54:38 PM PDT 24
Finished Jul 24 07:10:50 PM PDT 24
Peak memory 703204 kb
Host smart-1c7b0169-349e-4ad4-92ff-a801ae8c19d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262530523 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4262530523
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.218570727
Short name T249
Test name
Test status
Simulation time 973166231 ps
CPU time 51.5 seconds
Started Jul 24 06:54:36 PM PDT 24
Finished Jul 24 06:55:27 PM PDT 24
Peak memory 199800 kb
Host smart-0c6d781c-0e5f-4895-8708-b7b232b58356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218570727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.218570727
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1746086369
Short name T180
Test name
Test status
Simulation time 49534146 ps
CPU time 0.58 seconds
Started Jul 24 06:54:34 PM PDT 24
Finished Jul 24 06:54:35 PM PDT 24
Peak memory 195416 kb
Host smart-00171437-48e3-4f27-b37a-a51fae63402e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746086369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1746086369
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2643663732
Short name T448
Test name
Test status
Simulation time 6697875772 ps
CPU time 51.06 seconds
Started Jul 24 06:54:32 PM PDT 24
Finished Jul 24 06:55:23 PM PDT 24
Peak memory 216092 kb
Host smart-7b3a06e4-38dd-4f61-bd60-32424455c806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643663732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2643663732
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2694735326
Short name T100
Test name
Test status
Simulation time 13627827452 ps
CPU time 1254.28 seconds
Started Jul 24 06:54:32 PM PDT 24
Finished Jul 24 07:15:26 PM PDT 24
Peak memory 746176 kb
Host smart-29207857-0b2a-44fd-b4d4-c96180170f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694735326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2694735326
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1189653010
Short name T420
Test name
Test status
Simulation time 55621327759 ps
CPU time 164.68 seconds
Started Jul 24 06:54:31 PM PDT 24
Finished Jul 24 06:57:16 PM PDT 24
Peak memory 199804 kb
Host smart-7f492243-1c5f-43a0-a302-001bbc4fb965
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189653010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1189653010
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2965949556
Short name T277
Test name
Test status
Simulation time 18049656080 ps
CPU time 159.45 seconds
Started Jul 24 06:54:36 PM PDT 24
Finished Jul 24 06:57:16 PM PDT 24
Peak memory 199852 kb
Host smart-d007e9a5-1380-4e94-b3ac-1ed2ea1472c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965949556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2965949556
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.984770951
Short name T404
Test name
Test status
Simulation time 457086691 ps
CPU time 7.77 seconds
Started Jul 24 06:54:35 PM PDT 24
Finished Jul 24 06:54:43 PM PDT 24
Peak memory 199740 kb
Host smart-cf091911-7c88-4323-9a8d-3d1377fab489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984770951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.984770951
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2425878810
Short name T87
Test name
Test status
Simulation time 546339537578 ps
CPU time 3679.65 seconds
Started Jul 24 06:54:39 PM PDT 24
Finished Jul 24 07:55:59 PM PDT 24
Peak memory 824232 kb
Host smart-0235af0f-bdef-4a71-bd4c-049ca9d6a8bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425878810 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2425878810
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.685277393
Short name T105
Test name
Test status
Simulation time 2221032896 ps
CPU time 115.69 seconds
Started Jul 24 06:54:34 PM PDT 24
Finished Jul 24 06:56:30 PM PDT 24
Peak memory 199772 kb
Host smart-878d04a3-2e2e-4317-ba9d-54d275aa2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685277393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.685277393
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.863203800
Short name T179
Test name
Test status
Simulation time 14880634 ps
CPU time 0.6 seconds
Started Jul 24 06:54:38 PM PDT 24
Finished Jul 24 06:54:39 PM PDT 24
Peak memory 196364 kb
Host smart-75370ed3-2463-4b9f-b588-e06bf3648a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863203800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.863203800
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2817796012
Short name T268
Test name
Test status
Simulation time 6273501697 ps
CPU time 93.68 seconds
Started Jul 24 06:54:32 PM PDT 24
Finished Jul 24 06:56:06 PM PDT 24
Peak memory 208056 kb
Host smart-f3b32d41-b46e-4226-95b0-298ceabe2d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817796012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2817796012
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3758223195
Short name T467
Test name
Test status
Simulation time 2548156798 ps
CPU time 35.78 seconds
Started Jul 24 06:54:39 PM PDT 24
Finished Jul 24 06:55:15 PM PDT 24
Peak memory 199788 kb
Host smart-7bac0b4b-8cba-4836-b325-a17be8dc6156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758223195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3758223195
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1587584623
Short name T455
Test name
Test status
Simulation time 6030870006 ps
CPU time 1095.2 seconds
Started Jul 24 06:54:31 PM PDT 24
Finished Jul 24 07:12:46 PM PDT 24
Peak memory 735976 kb
Host smart-8acd70cd-e605-4e96-b65e-88696ef2eacc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587584623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1587584623
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4280870003
Short name T322
Test name
Test status
Simulation time 37364474236 ps
CPU time 224.54 seconds
Started Jul 24 06:54:40 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 199772 kb
Host smart-591a5be6-439d-4544-afc3-736a47f36dde
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280870003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4280870003
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_smoke.2211447637
Short name T525
Test name
Test status
Simulation time 2879709938 ps
CPU time 9.49 seconds
Started Jul 24 06:54:31 PM PDT 24
Finished Jul 24 06:54:41 PM PDT 24
Peak memory 199824 kb
Host smart-f8f1644a-2767-4bcf-91c3-5b4ca1b105ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211447637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2211447637
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1623406031
Short name T131
Test name
Test status
Simulation time 51508003323 ps
CPU time 1444.44 seconds
Started Jul 24 06:54:40 PM PDT 24
Finished Jul 24 07:18:45 PM PDT 24
Peak memory 459092 kb
Host smart-6e8cc462-0671-4299-bd33-52a2534b079f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623406031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1623406031
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1900745910
Short name T227
Test name
Test status
Simulation time 27912819533 ps
CPU time 103.18 seconds
Started Jul 24 06:54:38 PM PDT 24
Finished Jul 24 06:56:21 PM PDT 24
Peak memory 199736 kb
Host smart-7dffeaf2-73f9-4314-b898-0b90aa885ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900745910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1900745910
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.87456601
Short name T396
Test name
Test status
Simulation time 45387851 ps
CPU time 0.59 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:54:46 PM PDT 24
Peak memory 195696 kb
Host smart-4ad818a8-0740-467a-88e3-03836c6cf043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87456601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.87456601
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3370279901
Short name T153
Test name
Test status
Simulation time 452847760 ps
CPU time 27.19 seconds
Started Jul 24 06:54:40 PM PDT 24
Finished Jul 24 06:55:07 PM PDT 24
Peak memory 199736 kb
Host smart-8bbba579-db97-4e03-a8f1-ce8b1f6834fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370279901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3370279901
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2830043322
Short name T423
Test name
Test status
Simulation time 2823728488 ps
CPU time 40.37 seconds
Started Jul 24 06:54:38 PM PDT 24
Finished Jul 24 06:55:19 PM PDT 24
Peak memory 199768 kb
Host smart-456fcfb4-2d14-41e2-874e-f4f9043d9bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830043322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2830043322
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1246900393
Short name T462
Test name
Test status
Simulation time 9208158321 ps
CPU time 335.25 seconds
Started Jul 24 06:54:39 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 447524 kb
Host smart-1b4d9df3-8e4c-46f8-a413-ad7652623813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246900393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1246900393
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.602894850
Short name T470
Test name
Test status
Simulation time 4711529302 ps
CPU time 117.17 seconds
Started Jul 24 06:54:39 PM PDT 24
Finished Jul 24 06:56:36 PM PDT 24
Peak memory 199776 kb
Host smart-07c5e1dd-0ce3-4612-9181-2101bf98fdff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602894850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.602894850
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.482936814
Short name T189
Test name
Test status
Simulation time 818956920 ps
CPU time 45.36 seconds
Started Jul 24 06:54:47 PM PDT 24
Finished Jul 24 06:55:33 PM PDT 24
Peak memory 199768 kb
Host smart-a3842acd-2ce2-4777-9982-5b9342811ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482936814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.482936814
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2185679954
Short name T380
Test name
Test status
Simulation time 47024726 ps
CPU time 1.11 seconds
Started Jul 24 06:54:40 PM PDT 24
Finished Jul 24 06:54:41 PM PDT 24
Peak memory 199548 kb
Host smart-f87adaba-cd45-4464-888b-cb16b7acba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185679954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2185679954
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3861367928
Short name T307
Test name
Test status
Simulation time 80037393 ps
CPU time 0.66 seconds
Started Jul 24 06:54:48 PM PDT 24
Finished Jul 24 06:54:49 PM PDT 24
Peak memory 195556 kb
Host smart-860e9a0d-2987-4ce4-87e2-6b383c1be7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861367928 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3861367928
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4025642648
Short name T128
Test name
Test status
Simulation time 4449558537 ps
CPU time 57.95 seconds
Started Jul 24 06:54:41 PM PDT 24
Finished Jul 24 06:55:39 PM PDT 24
Peak memory 199792 kb
Host smart-6070de15-3778-4909-a9e6-c5c478a587ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025642648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4025642648
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.587585507
Short name T169
Test name
Test status
Simulation time 19021082 ps
CPU time 0.61 seconds
Started Jul 24 06:54:47 PM PDT 24
Finished Jul 24 06:54:48 PM PDT 24
Peak memory 195624 kb
Host smart-d2f48db2-40d9-494d-bfb0-4258cc47608c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587585507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.587585507
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.782336665
Short name T148
Test name
Test status
Simulation time 541933915 ps
CPU time 30.41 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:55:16 PM PDT 24
Peak memory 199736 kb
Host smart-332a05f1-2daa-41c6-97ad-039da7060a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782336665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.782336665
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.914850919
Short name T523
Test name
Test status
Simulation time 9753113271 ps
CPU time 31.3 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:55:17 PM PDT 24
Peak memory 200044 kb
Host smart-99550d98-b31c-4ab2-ac14-ee9f1a1d3c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914850919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.914850919
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3476708471
Short name T83
Test name
Test status
Simulation time 4728476871 ps
CPU time 811.9 seconds
Started Jul 24 06:54:48 PM PDT 24
Finished Jul 24 07:08:20 PM PDT 24
Peak memory 706420 kb
Host smart-860562fb-ebd2-42c2-a98e-9663a11ecb1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476708471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3476708471
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.242347537
Short name T450
Test name
Test status
Simulation time 42668492583 ps
CPU time 119.56 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:56:45 PM PDT 24
Peak memory 199832 kb
Host smart-69f346f1-7565-4a3e-b3f8-acd9c9e6b56e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242347537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.242347537
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.495284558
Short name T252
Test name
Test status
Simulation time 51873366500 ps
CPU time 152.61 seconds
Started Jul 24 06:54:48 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 199780 kb
Host smart-dc12f73c-9935-4ca0-a3c5-aff93f7efb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495284558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.495284558
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.977457321
Short name T211
Test name
Test status
Simulation time 5074142403 ps
CPU time 8.01 seconds
Started Jul 24 06:54:46 PM PDT 24
Finished Jul 24 06:54:54 PM PDT 24
Peak memory 199780 kb
Host smart-0e4102ec-2d27-4b2c-a51c-d0e7b100b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977457321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.977457321
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3390439193
Short name T90
Test name
Test status
Simulation time 528694109764 ps
CPU time 2600.26 seconds
Started Jul 24 06:54:46 PM PDT 24
Finished Jul 24 07:38:07 PM PDT 24
Peak memory 771124 kb
Host smart-a5cd3061-8b54-47b6-bcaa-37e27764c143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390439193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3390439193
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1370814607
Short name T296
Test name
Test status
Simulation time 5285778308 ps
CPU time 97.08 seconds
Started Jul 24 06:54:48 PM PDT 24
Finished Jul 24 06:56:25 PM PDT 24
Peak memory 199756 kb
Host smart-e319c8e5-cdfe-4bdd-83c4-9bc206d71ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370814607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1370814607
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3144724942
Short name T347
Test name
Test status
Simulation time 46198827 ps
CPU time 0.58 seconds
Started Jul 24 06:54:51 PM PDT 24
Finished Jul 24 06:54:51 PM PDT 24
Peak memory 195340 kb
Host smart-2330b1db-0a5d-4004-9d3c-47e71b708a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144724942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3144724942
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4262577598
Short name T262
Test name
Test status
Simulation time 162609168 ps
CPU time 1.7 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:54:47 PM PDT 24
Peak memory 199652 kb
Host smart-04a6e029-55f8-4e17-9977-d31a7c450ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262577598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4262577598
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1037827422
Short name T96
Test name
Test status
Simulation time 713918991 ps
CPU time 39 seconds
Started Jul 24 06:54:54 PM PDT 24
Finished Jul 24 06:55:34 PM PDT 24
Peak memory 199736 kb
Host smart-2340b5aa-b04f-42e6-9f43-47fe59b5585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037827422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1037827422
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.448764353
Short name T22
Test name
Test status
Simulation time 16178164114 ps
CPU time 785.84 seconds
Started Jul 24 06:54:52 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 703864 kb
Host smart-56a7749a-df58-4067-9982-96117a0d64d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448764353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.448764353
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4009109611
Short name T355
Test name
Test status
Simulation time 15338996205 ps
CPU time 120.69 seconds
Started Jul 24 06:54:53 PM PDT 24
Finished Jul 24 06:56:54 PM PDT 24
Peak memory 199772 kb
Host smart-cfef1dff-497d-4bc8-8657-e8520720e87a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009109611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4009109611
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1324324869
Short name T195
Test name
Test status
Simulation time 28152974612 ps
CPU time 112.96 seconds
Started Jul 24 06:54:47 PM PDT 24
Finished Jul 24 06:56:40 PM PDT 24
Peak memory 199784 kb
Host smart-7ed2c888-0431-4950-a849-8a37d38069cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324324869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1324324869
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2078865618
Short name T181
Test name
Test status
Simulation time 787623552 ps
CPU time 11.23 seconds
Started Jul 24 06:54:45 PM PDT 24
Finished Jul 24 06:54:57 PM PDT 24
Peak memory 199764 kb
Host smart-7b52608d-840b-4ad1-a2f2-cdd6ac4f451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078865618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2078865618
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3929469302
Short name T86
Test name
Test status
Simulation time 176154119720 ps
CPU time 2248.03 seconds
Started Jul 24 06:54:51 PM PDT 24
Finished Jul 24 07:32:20 PM PDT 24
Peak memory 803696 kb
Host smart-59d8317e-d4c3-4412-a2b8-8f3cb0fdd1ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929469302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3929469302
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1910581806
Short name T497
Test name
Test status
Simulation time 19826399564 ps
CPU time 86.01 seconds
Started Jul 24 06:54:54 PM PDT 24
Finished Jul 24 06:56:21 PM PDT 24
Peak memory 199808 kb
Host smart-6c8d43a4-fff3-4d10-bb04-52d17e642c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910581806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1910581806
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2436943365
Short name T393
Test name
Test status
Simulation time 50995269 ps
CPU time 0.61 seconds
Started Jul 24 06:54:58 PM PDT 24
Finished Jul 24 06:54:59 PM PDT 24
Peak memory 195728 kb
Host smart-bbdf143a-59a9-43ee-8751-c4bc0fc491f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436943365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2436943365
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.324429243
Short name T178
Test name
Test status
Simulation time 5291357107 ps
CPU time 80.5 seconds
Started Jul 24 06:55:01 PM PDT 24
Finished Jul 24 06:56:21 PM PDT 24
Peak memory 199796 kb
Host smart-044972e1-8dd1-4bbb-ac7d-b463d7e0e980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324429243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.324429243
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.962315668
Short name T54
Test name
Test status
Simulation time 3540397314 ps
CPU time 46.52 seconds
Started Jul 24 06:54:59 PM PDT 24
Finished Jul 24 06:55:46 PM PDT 24
Peak memory 199840 kb
Host smart-03e6478c-270d-4fc2-a286-6f64e387621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962315668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.962315668
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1255724118
Short name T57
Test name
Test status
Simulation time 35885616098 ps
CPU time 1549.25 seconds
Started Jul 24 06:55:02 PM PDT 24
Finished Jul 24 07:20:51 PM PDT 24
Peak memory 787352 kb
Host smart-8f72cf10-ebb6-40e7-9a0a-5ff1779e1c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255724118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1255724118
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2000638688
Short name T400
Test name
Test status
Simulation time 21316472568 ps
CPU time 181.08 seconds
Started Jul 24 06:54:58 PM PDT 24
Finished Jul 24 06:58:00 PM PDT 24
Peak memory 199828 kb
Host smart-c90fcc8e-c8e2-4dd4-b100-fa07c73d6c29
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000638688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2000638688
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2098680757
Short name T350
Test name
Test status
Simulation time 51854172293 ps
CPU time 152.22 seconds
Started Jul 24 06:54:52 PM PDT 24
Finished Jul 24 06:57:25 PM PDT 24
Peak memory 199804 kb
Host smart-49c61668-729d-4cac-86e4-5564138e5ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098680757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2098680757
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.57067881
Short name T359
Test name
Test status
Simulation time 999527202 ps
CPU time 12.87 seconds
Started Jul 24 06:54:51 PM PDT 24
Finished Jul 24 06:55:04 PM PDT 24
Peak memory 199712 kb
Host smart-b3898777-83eb-49e2-9ee6-5ea2415b5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57067881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.57067881
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3484074886
Short name T34
Test name
Test status
Simulation time 16401442752 ps
CPU time 1782.02 seconds
Started Jul 24 06:55:02 PM PDT 24
Finished Jul 24 07:24:44 PM PDT 24
Peak memory 754644 kb
Host smart-66b62bf6-e826-408e-ba0a-9c8db46882fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484074886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3484074886
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2124945886
Short name T300
Test name
Test status
Simulation time 7894804149 ps
CPU time 81.39 seconds
Started Jul 24 06:55:01 PM PDT 24
Finished Jul 24 06:56:23 PM PDT 24
Peak memory 199808 kb
Host smart-06d07b48-ea56-4f6a-ac58-1366622ec4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124945886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2124945886
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1298989826
Short name T213
Test name
Test status
Simulation time 12367414 ps
CPU time 0.56 seconds
Started Jul 24 06:52:40 PM PDT 24
Finished Jul 24 06:52:41 PM PDT 24
Peak memory 194752 kb
Host smart-26a283a1-399a-4ad2-b917-e1c6f7846265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298989826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1298989826
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2857709620
Short name T282
Test name
Test status
Simulation time 1563825537 ps
CPU time 44.47 seconds
Started Jul 24 06:52:31 PM PDT 24
Finished Jul 24 06:53:16 PM PDT 24
Peak memory 199696 kb
Host smart-385b3a1f-e199-4c0a-99e4-f92ac6ae5df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857709620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2857709620
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.54848450
Short name T206
Test name
Test status
Simulation time 4076009117 ps
CPU time 804.94 seconds
Started Jul 24 06:52:38 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 709952 kb
Host smart-9b6ce0c7-cf23-432f-baac-43dd4259d95b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54848450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.54848450
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2038963338
Short name T82
Test name
Test status
Simulation time 25698756903 ps
CPU time 177.49 seconds
Started Jul 24 06:52:37 PM PDT 24
Finished Jul 24 06:55:34 PM PDT 24
Peak memory 199844 kb
Host smart-93b5b116-dfdc-46b1-abf3-3edfb7455f49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038963338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2038963338
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2015944987
Short name T392
Test name
Test status
Simulation time 2740390499 ps
CPU time 33.25 seconds
Started Jul 24 06:52:31 PM PDT 24
Finished Jul 24 06:53:04 PM PDT 24
Peak memory 199804 kb
Host smart-e6b8ad3f-5475-4f23-aa1d-dd8cf36731d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015944987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2015944987
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1951099278
Short name T67
Test name
Test status
Simulation time 569051613 ps
CPU time 0.82 seconds
Started Jul 24 06:52:39 PM PDT 24
Finished Jul 24 06:52:40 PM PDT 24
Peak memory 218204 kb
Host smart-bfb1440a-ac47-4693-8c2b-36bba76e98d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951099278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1951099278
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2948833679
Short name T231
Test name
Test status
Simulation time 124041688 ps
CPU time 2.04 seconds
Started Jul 24 06:52:32 PM PDT 24
Finished Jul 24 06:52:34 PM PDT 24
Peak memory 199752 kb
Host smart-69daab94-90e0-4c41-9408-0e82dc1c75b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948833679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2948833679
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1636037579
Short name T226
Test name
Test status
Simulation time 1957003870 ps
CPU time 101.6 seconds
Started Jul 24 06:52:38 PM PDT 24
Finished Jul 24 06:54:19 PM PDT 24
Peak memory 216112 kb
Host smart-0a6b9b80-3d4e-4737-bdee-7b81530f9070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636037579 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1636037579
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.131116115
Short name T80
Test name
Test status
Simulation time 106917046600 ps
CPU time 514.39 seconds
Started Jul 24 06:52:39 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 216324 kb
Host smart-78eef9aa-dc92-4e45-8bbf-2e61fa5c1cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131116115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.131116115
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.390517428
Short name T406
Test name
Test status
Simulation time 3297861529 ps
CPU time 50.61 seconds
Started Jul 24 06:52:39 PM PDT 24
Finished Jul 24 06:53:29 PM PDT 24
Peak memory 199796 kb
Host smart-76c22702-87bb-46c9-bb9b-bfcabaf5bffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=390517428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.390517428
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3556323815
Short name T398
Test name
Test status
Simulation time 26177368579 ps
CPU time 57.59 seconds
Started Jul 24 06:52:40 PM PDT 24
Finished Jul 24 06:53:37 PM PDT 24
Peak memory 199880 kb
Host smart-a0a9d3c7-49e3-482e-af32-74cdc86ae046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3556323815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3556323815
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3777510720
Short name T2
Test name
Test status
Simulation time 6366741504 ps
CPU time 124.32 seconds
Started Jul 24 06:52:37 PM PDT 24
Finished Jul 24 06:54:41 PM PDT 24
Peak memory 199728 kb
Host smart-e66490e4-42b8-4c1f-8d93-9c6f82c39dcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3777510720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3777510720
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1802845285
Short name T49
Test name
Test status
Simulation time 41327056040 ps
CPU time 538.03 seconds
Started Jul 24 06:52:36 PM PDT 24
Finished Jul 24 07:01:35 PM PDT 24
Peak memory 199728 kb
Host smart-08b783b7-f7c8-4c92-82d3-5c63d9db4296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1802845285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1802845285
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1025417336
Short name T149
Test name
Test status
Simulation time 161170785502 ps
CPU time 2131.04 seconds
Started Jul 24 06:52:40 PM PDT 24
Finished Jul 24 07:28:11 PM PDT 24
Peak memory 215840 kb
Host smart-252a39d8-f140-4d1a-9dc6-5412377dec7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1025417336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1025417336
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2032860236
Short name T435
Test name
Test status
Simulation time 224755870459 ps
CPU time 2237.36 seconds
Started Jul 24 06:52:37 PM PDT 24
Finished Jul 24 07:29:55 PM PDT 24
Peak memory 215360 kb
Host smart-08c6e0a2-86bd-4455-aa5d-8de39ff9e988
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2032860236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2032860236
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3691747719
Short name T372
Test name
Test status
Simulation time 7719640006 ps
CPU time 106.15 seconds
Started Jul 24 06:52:29 PM PDT 24
Finished Jul 24 06:54:16 PM PDT 24
Peak memory 199860 kb
Host smart-758ad7ab-d005-4d4a-900f-e5349bf4b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691747719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3691747719
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.488675569
Short name T390
Test name
Test status
Simulation time 15463281 ps
CPU time 0.58 seconds
Started Jul 24 06:55:08 PM PDT 24
Finished Jul 24 06:55:09 PM PDT 24
Peak memory 196388 kb
Host smart-54e7e4b2-8dda-4c2b-bba0-2ed9018bb7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488675569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.488675569
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.617415442
Short name T207
Test name
Test status
Simulation time 2334749372 ps
CPU time 36.08 seconds
Started Jul 24 06:55:05 PM PDT 24
Finished Jul 24 06:55:41 PM PDT 24
Peak memory 199732 kb
Host smart-b4ee196b-74b3-425f-acb8-0c4ab148e232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617415442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.617415442
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.486257992
Short name T159
Test name
Test status
Simulation time 2866452852 ps
CPU time 77.44 seconds
Started Jul 24 06:55:05 PM PDT 24
Finished Jul 24 06:56:22 PM PDT 24
Peak memory 199752 kb
Host smart-a7037f9f-1ce4-4b5d-bc8e-c4823c126517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486257992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.486257992
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3630295086
Short name T365
Test name
Test status
Simulation time 13713861138 ps
CPU time 617.31 seconds
Started Jul 24 06:55:08 PM PDT 24
Finished Jul 24 07:05:25 PM PDT 24
Peak memory 646400 kb
Host smart-97f680d8-3de9-4f74-810c-583b1eba5b66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630295086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3630295086
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4291877972
Short name T223
Test name
Test status
Simulation time 20353625072 ps
CPU time 67.49 seconds
Started Jul 24 06:55:08 PM PDT 24
Finished Jul 24 06:56:16 PM PDT 24
Peak memory 199780 kb
Host smart-9dbe4776-ad97-4a8c-bba4-029ac0250f88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291877972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4291877972
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.696272089
Short name T166
Test name
Test status
Simulation time 3292681390 ps
CPU time 14.6 seconds
Started Jul 24 06:55:00 PM PDT 24
Finished Jul 24 06:55:15 PM PDT 24
Peak memory 199824 kb
Host smart-9b933c1a-22ce-464f-a7e6-f806e7de67bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696272089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.696272089
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1968915399
Short name T434
Test name
Test status
Simulation time 571900326 ps
CPU time 7.4 seconds
Started Jul 24 06:54:58 PM PDT 24
Finished Jul 24 06:55:06 PM PDT 24
Peak memory 199756 kb
Host smart-6e5c4315-e4e6-4a34-b9cd-d7fa70cf2875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968915399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1968915399
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.466225334
Short name T45
Test name
Test status
Simulation time 932074370 ps
CPU time 15.58 seconds
Started Jul 24 06:55:08 PM PDT 24
Finished Jul 24 06:55:24 PM PDT 24
Peak memory 199872 kb
Host smart-4180e1b5-7a23-42fd-9a88-7537ccec5b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466225334 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.466225334
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.4077944587
Short name T242
Test name
Test status
Simulation time 3132281455 ps
CPU time 81.14 seconds
Started Jul 24 06:55:05 PM PDT 24
Finished Jul 24 06:56:26 PM PDT 24
Peak memory 199824 kb
Host smart-153b1e92-21dd-405e-939f-838a3fe4a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077944587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.4077944587
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2047980958
Short name T477
Test name
Test status
Simulation time 40270562 ps
CPU time 0.58 seconds
Started Jul 24 06:55:11 PM PDT 24
Finished Jul 24 06:55:11 PM PDT 24
Peak memory 194752 kb
Host smart-204c69da-1613-4ce0-8555-e097da3fc78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047980958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2047980958
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.968611889
Short name T230
Test name
Test status
Simulation time 1549178142 ps
CPU time 83.9 seconds
Started Jul 24 06:55:11 PM PDT 24
Finished Jul 24 06:56:35 PM PDT 24
Peak memory 199704 kb
Host smart-aea7f157-762f-4e6a-9276-57ecb62b1112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968611889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.968611889
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3182312922
Short name T424
Test name
Test status
Simulation time 43551815254 ps
CPU time 1318.09 seconds
Started Jul 24 06:55:12 PM PDT 24
Finished Jul 24 07:17:10 PM PDT 24
Peak memory 756188 kb
Host smart-b56e8423-63d1-4ce1-9b80-b54fa507f71f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182312922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3182312922
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.879169549
Short name T174
Test name
Test status
Simulation time 210388026386 ps
CPU time 203.83 seconds
Started Jul 24 06:55:13 PM PDT 24
Finished Jul 24 06:58:37 PM PDT 24
Peak memory 199876 kb
Host smart-af080f49-7e5f-4ce1-adc2-ab021f2dfdb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879169549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.879169549
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3063260989
Short name T314
Test name
Test status
Simulation time 7193928151 ps
CPU time 57.18 seconds
Started Jul 24 06:55:11 PM PDT 24
Finished Jul 24 06:56:09 PM PDT 24
Peak memory 215980 kb
Host smart-a90ae376-9891-4f2a-b559-4f8d48342787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063260989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3063260989
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1630036275
Short name T375
Test name
Test status
Simulation time 1072466586 ps
CPU time 13.16 seconds
Started Jul 24 06:55:04 PM PDT 24
Finished Jul 24 06:55:17 PM PDT 24
Peak memory 199720 kb
Host smart-abf042c1-2b09-4e3b-9edf-c3bcf169d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630036275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1630036275
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.251483860
Short name T134
Test name
Test status
Simulation time 295846070490 ps
CPU time 2358.66 seconds
Started Jul 24 06:55:13 PM PDT 24
Finished Jul 24 07:34:32 PM PDT 24
Peak memory 759456 kb
Host smart-96c37464-af46-4e23-b923-d58f02b3a22d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251483860 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.251483860
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.854027440
Short name T295
Test name
Test status
Simulation time 11186299399 ps
CPU time 103.51 seconds
Started Jul 24 06:55:13 PM PDT 24
Finished Jul 24 06:56:56 PM PDT 24
Peak memory 199824 kb
Host smart-2fc7cd22-8f2e-4008-821e-8039110b335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854027440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.854027440
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3678568538
Short name T93
Test name
Test status
Simulation time 174224804 ps
CPU time 0.65 seconds
Started Jul 24 06:55:18 PM PDT 24
Finished Jul 24 06:55:18 PM PDT 24
Peak memory 194704 kb
Host smart-50652caa-9d6f-4df9-bea6-ff7ad752f00f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678568538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3678568538
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3276283627
Short name T487
Test name
Test status
Simulation time 6434426657 ps
CPU time 51.14 seconds
Started Jul 24 06:55:17 PM PDT 24
Finished Jul 24 06:56:08 PM PDT 24
Peak memory 200004 kb
Host smart-092fa7d1-667e-485b-861c-a1eb779a4a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276283627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3276283627
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.432739611
Short name T272
Test name
Test status
Simulation time 26925441955 ps
CPU time 24.43 seconds
Started Jul 24 06:55:17 PM PDT 24
Finished Jul 24 06:55:41 PM PDT 24
Peak memory 199692 kb
Host smart-fba68673-9828-4bd9-96da-b681f06d6b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432739611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.432739611
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2635458140
Short name T290
Test name
Test status
Simulation time 11373982395 ps
CPU time 964.64 seconds
Started Jul 24 06:55:19 PM PDT 24
Finished Jul 24 07:11:23 PM PDT 24
Peak memory 703700 kb
Host smart-f7557cb3-d59b-4615-957e-994516f24de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635458140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2635458140
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1840483314
Short name T192
Test name
Test status
Simulation time 6807340077 ps
CPU time 200.95 seconds
Started Jul 24 06:55:19 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 199780 kb
Host smart-c6c100ce-7530-4c96-aad4-e4ae55458a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840483314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1840483314
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4050823435
Short name T311
Test name
Test status
Simulation time 2384901861 ps
CPU time 140.77 seconds
Started Jul 24 06:55:12 PM PDT 24
Finished Jul 24 06:57:33 PM PDT 24
Peak memory 199836 kb
Host smart-4843ff63-5887-416c-864d-b123c3b83fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050823435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4050823435
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.979179553
Short name T197
Test name
Test status
Simulation time 101816641 ps
CPU time 1.72 seconds
Started Jul 24 06:55:12 PM PDT 24
Finished Jul 24 06:55:14 PM PDT 24
Peak memory 199724 kb
Host smart-523890ff-b78f-43c7-b5a3-35275c737c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979179553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.979179553
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.277299438
Short name T156
Test name
Test status
Simulation time 73848665938 ps
CPU time 1535.21 seconds
Started Jul 24 06:55:17 PM PDT 24
Finished Jul 24 07:20:53 PM PDT 24
Peak memory 660460 kb
Host smart-6c772d3b-276e-4f5e-816f-591f3d9b5ed0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277299438 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.277299438
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1284723869
Short name T330
Test name
Test status
Simulation time 4073828704 ps
CPU time 46.95 seconds
Started Jul 24 06:55:17 PM PDT 24
Finished Jul 24 06:56:05 PM PDT 24
Peak memory 199748 kb
Host smart-e1fdb056-5b76-449c-b5a7-4671563533cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284723869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1284723869
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1051678614
Short name T395
Test name
Test status
Simulation time 13129712 ps
CPU time 0.59 seconds
Started Jul 24 06:55:19 PM PDT 24
Finished Jul 24 06:55:20 PM PDT 24
Peak memory 195736 kb
Host smart-2c764f5f-7e97-4115-aaba-bf39fdb9206f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051678614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1051678614
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.901166520
Short name T200
Test name
Test status
Simulation time 3053870510 ps
CPU time 35.44 seconds
Started Jul 24 06:55:18 PM PDT 24
Finished Jul 24 06:55:54 PM PDT 24
Peak memory 199764 kb
Host smart-8b7872a5-584a-4ac7-ab2d-31463e55b2b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901166520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.901166520
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1578182283
Short name T158
Test name
Test status
Simulation time 141425491 ps
CPU time 8.81 seconds
Started Jul 24 06:55:20 PM PDT 24
Finished Jul 24 06:55:28 PM PDT 24
Peak memory 199736 kb
Host smart-7851cdd6-563b-494f-a34c-1fa46db45b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578182283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1578182283
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2615100907
Short name T177
Test name
Test status
Simulation time 1151382860 ps
CPU time 210.2 seconds
Started Jul 24 06:55:16 PM PDT 24
Finished Jul 24 06:58:47 PM PDT 24
Peak memory 588440 kb
Host smart-70436d46-e425-4616-9d44-eb0166f73127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615100907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2615100907
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.668960274
Short name T75
Test name
Test status
Simulation time 8738066479 ps
CPU time 164.35 seconds
Started Jul 24 06:55:20 PM PDT 24
Finished Jul 24 06:58:04 PM PDT 24
Peak memory 199800 kb
Host smart-e75449ae-a2ba-4199-8994-08be1f685204
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668960274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.668960274
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2731281111
Short name T426
Test name
Test status
Simulation time 27925261734 ps
CPU time 62.7 seconds
Started Jul 24 06:55:17 PM PDT 24
Finished Jul 24 06:56:20 PM PDT 24
Peak memory 199852 kb
Host smart-7370e537-1ea3-48a4-9c8c-228183153e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731281111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2731281111
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2117357448
Short name T496
Test name
Test status
Simulation time 1790460932 ps
CPU time 6.98 seconds
Started Jul 24 06:55:16 PM PDT 24
Finished Jul 24 06:55:24 PM PDT 24
Peak memory 199712 kb
Host smart-4a3559c6-af67-4437-9944-d23fe08f235e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117357448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2117357448
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1481877016
Short name T225
Test name
Test status
Simulation time 1648772281 ps
CPU time 15.95 seconds
Started Jul 24 06:55:19 PM PDT 24
Finished Jul 24 06:55:35 PM PDT 24
Peak memory 199768 kb
Host smart-60ae0670-dd2d-4286-ba32-da3d46fba809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481877016 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1481877016
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1107702409
Short name T339
Test name
Test status
Simulation time 22748458685 ps
CPU time 101.58 seconds
Started Jul 24 06:55:18 PM PDT 24
Finished Jul 24 06:57:00 PM PDT 24
Peak memory 199860 kb
Host smart-34c9a4fc-d8e4-4c3e-84a4-7574116a058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107702409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1107702409
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3677454313
Short name T358
Test name
Test status
Simulation time 12010971 ps
CPU time 0.57 seconds
Started Jul 24 06:55:29 PM PDT 24
Finished Jul 24 06:55:29 PM PDT 24
Peak memory 195368 kb
Host smart-362d10ac-507b-42ff-866a-38733aa7f948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677454313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3677454313
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1805370600
Short name T485
Test name
Test status
Simulation time 1389312510 ps
CPU time 38.86 seconds
Started Jul 24 06:55:23 PM PDT 24
Finished Jul 24 06:56:02 PM PDT 24
Peak memory 199824 kb
Host smart-768f9593-d6f6-4be2-92e5-c955c8813118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805370600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1805370600
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1546888843
Short name T463
Test name
Test status
Simulation time 5106688679 ps
CPU time 25.56 seconds
Started Jul 24 06:55:25 PM PDT 24
Finished Jul 24 06:55:51 PM PDT 24
Peak memory 199656 kb
Host smart-1021e12a-f257-4c7d-b8d4-3c7d2a13127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546888843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1546888843
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1951450380
Short name T209
Test name
Test status
Simulation time 54928734862 ps
CPU time 538.21 seconds
Started Jul 24 06:55:24 PM PDT 24
Finished Jul 24 07:04:22 PM PDT 24
Peak memory 638252 kb
Host smart-44796b58-af4f-4bfb-b4ca-59b5be9b19ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951450380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1951450380
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.152665037
Short name T425
Test name
Test status
Simulation time 33989359872 ps
CPU time 223.68 seconds
Started Jul 24 06:55:24 PM PDT 24
Finished Jul 24 06:59:08 PM PDT 24
Peak memory 199836 kb
Host smart-b1a0b526-320b-4ae7-aa7d-5dfdd8cce058
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152665037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.152665037
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2370251489
Short name T288
Test name
Test status
Simulation time 7911328753 ps
CPU time 103.81 seconds
Started Jul 24 06:55:23 PM PDT 24
Finished Jul 24 06:57:07 PM PDT 24
Peak memory 199812 kb
Host smart-6dc81f29-8193-4fc3-9f0e-f687ac0f5f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370251489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2370251489
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4278048735
Short name T366
Test name
Test status
Simulation time 272375291 ps
CPU time 2.29 seconds
Started Jul 24 06:55:23 PM PDT 24
Finished Jul 24 06:55:26 PM PDT 24
Peak memory 199652 kb
Host smart-8b0fc6bb-2047-42a6-b5d8-98d074d8f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278048735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4278048735
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.771337370
Short name T157
Test name
Test status
Simulation time 38307475677 ps
CPU time 1326.59 seconds
Started Jul 24 06:55:30 PM PDT 24
Finished Jul 24 07:17:37 PM PDT 24
Peak memory 717288 kb
Host smart-60b3ceaa-04e1-42b1-9081-710192f4093f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771337370 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.771337370
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2567771227
Short name T332
Test name
Test status
Simulation time 2233538653 ps
CPU time 23.87 seconds
Started Jul 24 06:55:25 PM PDT 24
Finished Jul 24 06:55:49 PM PDT 24
Peak memory 199664 kb
Host smart-ff705788-d67a-403e-9bb7-bad56f4c6a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567771227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2567771227
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1353806666
Short name T17
Test name
Test status
Simulation time 24268920 ps
CPU time 0.57 seconds
Started Jul 24 06:55:34 PM PDT 24
Finished Jul 24 06:55:35 PM PDT 24
Peak memory 194708 kb
Host smart-6122ec8d-9510-4cce-a1bd-9f2816e18a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353806666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1353806666
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1799550824
Short name T12
Test name
Test status
Simulation time 6800666958 ps
CPU time 82.65 seconds
Started Jul 24 06:55:32 PM PDT 24
Finished Jul 24 06:56:54 PM PDT 24
Peak memory 199752 kb
Host smart-a82a0947-d2a4-44af-af78-cbaa9e7dec20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799550824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1799550824
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.645021999
Short name T193
Test name
Test status
Simulation time 8876722391 ps
CPU time 66.14 seconds
Started Jul 24 06:55:29 PM PDT 24
Finished Jul 24 06:56:35 PM PDT 24
Peak memory 207944 kb
Host smart-ac8117db-d9a2-406c-81a0-79973819d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645021999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.645021999
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.90559528
Short name T44
Test name
Test status
Simulation time 15159962181 ps
CPU time 879.63 seconds
Started Jul 24 06:55:30 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 703172 kb
Host smart-defc45f7-af00-4754-8f6f-f8573d8f0770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90559528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.90559528
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3479482867
Short name T352
Test name
Test status
Simulation time 4612663022 ps
CPU time 82.57 seconds
Started Jul 24 06:55:29 PM PDT 24
Finished Jul 24 06:56:52 PM PDT 24
Peak memory 199768 kb
Host smart-2dda3bc8-c420-4a4e-b243-e021d8bfe62f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479482867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3479482867
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3244147649
Short name T55
Test name
Test status
Simulation time 18139051291 ps
CPU time 160.49 seconds
Started Jul 24 06:55:29 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 199772 kb
Host smart-89b35178-5e8b-4ee8-b5d2-32c2bf0874af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244147649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3244147649
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2953891002
Short name T263
Test name
Test status
Simulation time 3388136141 ps
CPU time 13.98 seconds
Started Jul 24 06:55:31 PM PDT 24
Finished Jul 24 06:55:45 PM PDT 24
Peak memory 199816 kb
Host smart-f138cdbc-2779-4fb6-a443-66857d76aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953891002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2953891002
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2400468099
Short name T324
Test name
Test status
Simulation time 333326160201 ps
CPU time 1343.48 seconds
Started Jul 24 06:55:37 PM PDT 24
Finished Jul 24 07:18:01 PM PDT 24
Peak memory 462992 kb
Host smart-8e933d9c-d105-432e-88ef-dcf8b7f17321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400468099 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2400468099
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4256049295
Short name T129
Test name
Test status
Simulation time 10879817164 ps
CPU time 33.26 seconds
Started Jul 24 06:55:33 PM PDT 24
Finished Jul 24 06:56:07 PM PDT 24
Peak memory 199772 kb
Host smart-81849754-1908-4f39-91ba-29571c99f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256049295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4256049295
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3355386066
Short name T236
Test name
Test status
Simulation time 14970254 ps
CPU time 0.58 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:55:45 PM PDT 24
Peak memory 194720 kb
Host smart-b3194172-e909-4ebe-a795-e59c7753fbfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355386066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3355386066
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3424072014
Short name T240
Test name
Test status
Simulation time 205095776 ps
CPU time 11.13 seconds
Started Jul 24 06:55:36 PM PDT 24
Finished Jul 24 06:55:47 PM PDT 24
Peak memory 199792 kb
Host smart-e623e47d-b815-4b30-a7fe-2cbe8eb82618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424072014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3424072014
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3187987348
Short name T459
Test name
Test status
Simulation time 2256744764 ps
CPU time 21.07 seconds
Started Jul 24 06:55:37 PM PDT 24
Finished Jul 24 06:55:58 PM PDT 24
Peak memory 199724 kb
Host smart-8875c8c2-5b5c-4692-8f1a-b890222a4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187987348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3187987348
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2647600092
Short name T458
Test name
Test status
Simulation time 18841733986 ps
CPU time 880.76 seconds
Started Jul 24 06:55:37 PM PDT 24
Finished Jul 24 07:10:17 PM PDT 24
Peak memory 749136 kb
Host smart-d12bafb6-acfe-470b-b4b8-0d05700499b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647600092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2647600092
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3888509070
Short name T302
Test name
Test status
Simulation time 10503900413 ps
CPU time 185.24 seconds
Started Jul 24 06:55:37 PM PDT 24
Finished Jul 24 06:58:43 PM PDT 24
Peak memory 199748 kb
Host smart-e023b3a2-9050-4ec6-a904-5055a2f7735e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888509070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3888509070
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4272455363
Short name T457
Test name
Test status
Simulation time 3906627974 ps
CPU time 105.29 seconds
Started Jul 24 06:55:35 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 199740 kb
Host smart-6a55f388-a327-4dc5-8dc7-b7915281b1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272455363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4272455363
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3870004614
Short name T235
Test name
Test status
Simulation time 126298788 ps
CPU time 3.22 seconds
Started Jul 24 06:55:35 PM PDT 24
Finished Jul 24 06:55:38 PM PDT 24
Peak memory 199728 kb
Host smart-7e002bde-b593-4f0b-b367-3701ea1cd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870004614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3870004614
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3511768382
Short name T433
Test name
Test status
Simulation time 5262906222 ps
CPU time 95.93 seconds
Started Jul 24 06:55:42 PM PDT 24
Finished Jul 24 06:57:19 PM PDT 24
Peak memory 199788 kb
Host smart-c89c10fe-0dc2-465d-a393-2751a1da70c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511768382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3511768382
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1248452198
Short name T106
Test name
Test status
Simulation time 52825031343 ps
CPU time 135.63 seconds
Started Jul 24 06:55:43 PM PDT 24
Finished Jul 24 06:57:59 PM PDT 24
Peak memory 199824 kb
Host smart-b08dcbb7-574b-4db7-9a9f-ad76cf1c8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248452198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1248452198
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3224339584
Short name T266
Test name
Test status
Simulation time 48109895 ps
CPU time 0.62 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:55:45 PM PDT 24
Peak memory 196376 kb
Host smart-86bc23c6-f4da-4450-ac88-b60874883764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224339584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3224339584
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.857330912
Short name T237
Test name
Test status
Simulation time 5085799314 ps
CPU time 67.96 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:56:52 PM PDT 24
Peak memory 199748 kb
Host smart-786f8631-1d9d-46fe-afb5-28c88a4f4981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857330912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.857330912
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2885981805
Short name T53
Test name
Test status
Simulation time 1824464754 ps
CPU time 24.57 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:56:09 PM PDT 24
Peak memory 199704 kb
Host smart-1a32c22a-f95e-4b34-8332-c66c16b45ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885981805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2885981805
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3716177307
Short name T421
Test name
Test status
Simulation time 27299928762 ps
CPU time 1206.24 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 07:15:51 PM PDT 24
Peak memory 726460 kb
Host smart-2d5ecdc6-bc64-40ce-873d-99429cd0babc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716177307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3716177307
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2377522940
Short name T479
Test name
Test status
Simulation time 27551128237 ps
CPU time 86.66 seconds
Started Jul 24 06:55:43 PM PDT 24
Finished Jul 24 06:57:10 PM PDT 24
Peak memory 199768 kb
Host smart-4dc13cae-0e7f-4ff8-b59d-91a4a537f07f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377522940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2377522940
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.961444379
Short name T383
Test name
Test status
Simulation time 4002460071 ps
CPU time 78.82 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:57:03 PM PDT 24
Peak memory 199792 kb
Host smart-d60fc16e-25c9-4011-9e8b-ad938d447a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961444379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.961444379
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3461893352
Short name T502
Test name
Test status
Simulation time 571355025 ps
CPU time 13.86 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:55:58 PM PDT 24
Peak memory 199668 kb
Host smart-294d8304-0c19-4a14-8856-73ef5a80ad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461893352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3461893352
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3946368086
Short name T516
Test name
Test status
Simulation time 38546099932 ps
CPU time 477.62 seconds
Started Jul 24 06:55:43 PM PDT 24
Finished Jul 24 07:03:41 PM PDT 24
Peak memory 337708 kb
Host smart-0bc65f4b-d3b8-4ed4-9052-36bdbb61651e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946368086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3946368086
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3109306348
Short name T26
Test name
Test status
Simulation time 6876363074 ps
CPU time 117.25 seconds
Started Jul 24 06:55:44 PM PDT 24
Finished Jul 24 06:57:42 PM PDT 24
Peak memory 199800 kb
Host smart-3c077e2c-ae18-4e0c-b177-431bfa847d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109306348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3109306348
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3926669540
Short name T478
Test name
Test status
Simulation time 30559717 ps
CPU time 0.58 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 06:55:49 PM PDT 24
Peak memory 195384 kb
Host smart-bd8ced00-2218-4e5f-9ad8-8401c36dc318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926669540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3926669540
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.207000591
Short name T370
Test name
Test status
Simulation time 1544233241 ps
CPU time 22.78 seconds
Started Jul 24 06:55:49 PM PDT 24
Finished Jul 24 06:56:12 PM PDT 24
Peak memory 199712 kb
Host smart-18989e7e-9744-4ee3-86d5-56fe63baf292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207000591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.207000591
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3928842195
Short name T469
Test name
Test status
Simulation time 2166530372 ps
CPU time 38.46 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 06:56:27 PM PDT 24
Peak memory 199824 kb
Host smart-c58969d6-8eab-4b6c-b518-fe0dd6986ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928842195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3928842195
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3253416802
Short name T278
Test name
Test status
Simulation time 7099812862 ps
CPU time 1413.81 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 07:19:22 PM PDT 24
Peak memory 732876 kb
Host smart-c50b2d67-a948-49cd-ad6b-c3c30d5ad525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253416802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3253416802
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2304010110
Short name T250
Test name
Test status
Simulation time 213457018 ps
CPU time 4.71 seconds
Started Jul 24 06:55:47 PM PDT 24
Finished Jul 24 06:55:52 PM PDT 24
Peak memory 199628 kb
Host smart-dee5c37f-2e2b-455f-b84a-20b72f73751f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304010110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2304010110
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3748402050
Short name T447
Test name
Test status
Simulation time 5271789644 ps
CPU time 150.03 seconds
Started Jul 24 06:55:47 PM PDT 24
Finished Jul 24 06:58:18 PM PDT 24
Peak memory 199792 kb
Host smart-8e7fdd54-2862-48c1-90d7-a5348b6be78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748402050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3748402050
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.591525317
Short name T454
Test name
Test status
Simulation time 95996927 ps
CPU time 1.56 seconds
Started Jul 24 06:55:49 PM PDT 24
Finished Jul 24 06:55:51 PM PDT 24
Peak memory 199632 kb
Host smart-e3a935a5-f9c0-4b4b-94e5-ab7d1130d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591525317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.591525317
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2672059352
Short name T482
Test name
Test status
Simulation time 8273256214 ps
CPU time 33.7 seconds
Started Jul 24 06:55:47 PM PDT 24
Finished Jul 24 06:56:21 PM PDT 24
Peak memory 199660 kb
Host smart-4303ad2e-c13f-4897-ab8f-a8466fd8cf20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672059352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2672059352
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1388274628
Short name T286
Test name
Test status
Simulation time 14431907382 ps
CPU time 128.63 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 06:57:56 PM PDT 24
Peak memory 199800 kb
Host smart-f8a40d1e-1396-4e52-a8d7-53a4ab831727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388274628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1388274628
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.447646817
Short name T165
Test name
Test status
Simulation time 12495657 ps
CPU time 0.6 seconds
Started Jul 24 06:55:54 PM PDT 24
Finished Jul 24 06:55:55 PM PDT 24
Peak memory 195740 kb
Host smart-ed028ad8-9758-423c-ba7c-cc66a3c8f10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447646817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.447646817
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.90285239
Short name T203
Test name
Test status
Simulation time 1302015799 ps
CPU time 72.27 seconds
Started Jul 24 06:55:47 PM PDT 24
Finished Jul 24 06:57:00 PM PDT 24
Peak memory 199780 kb
Host smart-ae6cd0d4-5a84-425b-9f3e-786947a824d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90285239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.90285239
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.897131009
Short name T323
Test name
Test status
Simulation time 94471497 ps
CPU time 1.66 seconds
Started Jul 24 06:55:49 PM PDT 24
Finished Jul 24 06:55:51 PM PDT 24
Peak memory 199644 kb
Host smart-d07312bf-c761-4030-8568-93845e10c08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897131009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.897131009
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3285138653
Short name T285
Test name
Test status
Simulation time 1572963267 ps
CPU time 253.89 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 07:00:02 PM PDT 24
Peak memory 443092 kb
Host smart-2885596c-0a25-48b4-975e-0531c33197e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285138653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3285138653
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1904179150
Short name T418
Test name
Test status
Simulation time 39731529909 ps
CPU time 124.1 seconds
Started Jul 24 06:55:54 PM PDT 24
Finished Jul 24 06:57:58 PM PDT 24
Peak memory 199720 kb
Host smart-8e88ace9-6a73-4c38-84d4-166e35ffc0a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904179150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1904179150
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.611342880
Short name T244
Test name
Test status
Simulation time 11191860770 ps
CPU time 135.29 seconds
Started Jul 24 06:55:47 PM PDT 24
Finished Jul 24 06:58:02 PM PDT 24
Peak memory 199740 kb
Host smart-2952ae50-75ef-4aff-9563-440c80cd1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611342880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.611342880
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2502108885
Short name T329
Test name
Test status
Simulation time 452669043 ps
CPU time 7.36 seconds
Started Jul 24 06:55:48 PM PDT 24
Finished Jul 24 06:55:56 PM PDT 24
Peak memory 199708 kb
Host smart-49510174-9956-4fba-9025-d86a951f51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502108885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2502108885
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1647258315
Short name T204
Test name
Test status
Simulation time 49348299043 ps
CPU time 1244.61 seconds
Started Jul 24 06:55:54 PM PDT 24
Finished Jul 24 07:16:39 PM PDT 24
Peak memory 704816 kb
Host smart-9db4319b-d8f0-4476-a500-f3238e0534a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647258315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1647258315
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3567790202
Short name T229
Test name
Test status
Simulation time 10084922977 ps
CPU time 127.64 seconds
Started Jul 24 06:55:53 PM PDT 24
Finished Jul 24 06:58:01 PM PDT 24
Peak memory 199800 kb
Host smart-9d36f339-581b-4a01-bea5-4d2031146374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567790202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3567790202
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3717578438
Short name T228
Test name
Test status
Simulation time 11646108 ps
CPU time 0.57 seconds
Started Jul 24 06:52:42 PM PDT 24
Finished Jul 24 06:52:43 PM PDT 24
Peak memory 195336 kb
Host smart-ab25f49e-2a21-45cc-be28-78d3b7321ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717578438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3717578438
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4122324496
Short name T73
Test name
Test status
Simulation time 1691959705 ps
CPU time 25.57 seconds
Started Jul 24 06:52:40 PM PDT 24
Finished Jul 24 06:53:06 PM PDT 24
Peak memory 199720 kb
Host smart-9638f43f-a706-4c96-9fcc-6989a058086e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122324496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4122324496
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3400008731
Short name T317
Test name
Test status
Simulation time 2973062616 ps
CPU time 56.2 seconds
Started Jul 24 06:52:46 PM PDT 24
Finished Jul 24 06:53:42 PM PDT 24
Peak memory 199772 kb
Host smart-79d38489-fd24-4c11-a835-ddcc4d8941ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400008731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3400008731
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.495552780
Short name T185
Test name
Test status
Simulation time 11500611877 ps
CPU time 1148.21 seconds
Started Jul 24 06:52:42 PM PDT 24
Finished Jul 24 07:11:50 PM PDT 24
Peak memory 681968 kb
Host smart-a0d863ab-2781-4100-8b20-db2e3569edf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495552780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.495552780
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4111131425
Short name T191
Test name
Test status
Simulation time 4606057079 ps
CPU time 85.36 seconds
Started Jul 24 06:52:44 PM PDT 24
Finished Jul 24 06:54:10 PM PDT 24
Peak memory 199796 kb
Host smart-fd69417d-4af1-4f02-bd58-72085ad5f78f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111131425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4111131425
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1555295779
Short name T386
Test name
Test status
Simulation time 8023562821 ps
CPU time 121.2 seconds
Started Jul 24 06:52:37 PM PDT 24
Finished Jul 24 06:54:39 PM PDT 24
Peak memory 216092 kb
Host smart-52068628-ee1c-4a40-9c56-bc57c0ab9f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555295779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1555295779
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4044547976
Short name T66
Test name
Test status
Simulation time 113329870 ps
CPU time 0.81 seconds
Started Jul 24 06:52:46 PM PDT 24
Finished Jul 24 06:52:47 PM PDT 24
Peak memory 218416 kb
Host smart-2a69c171-93d0-441b-aa79-d083be7407fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044547976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4044547976
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.355416850
Short name T451
Test name
Test status
Simulation time 921753610 ps
CPU time 4.85 seconds
Started Jul 24 06:52:38 PM PDT 24
Finished Jul 24 06:52:43 PM PDT 24
Peak memory 199684 kb
Host smart-c08b7443-299b-44d0-8084-97d0f12ea806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355416850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.355416850
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3908048888
Short name T407
Test name
Test status
Simulation time 1536394828 ps
CPU time 62.51 seconds
Started Jul 24 06:52:45 PM PDT 24
Finished Jul 24 06:53:48 PM PDT 24
Peak memory 199632 kb
Host smart-9200571a-74f7-4859-ad30-6bb82e19f6f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3908048888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3908048888
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3783109163
Short name T422
Test name
Test status
Simulation time 3701852894 ps
CPU time 59.41 seconds
Started Jul 24 06:52:42 PM PDT 24
Finished Jul 24 06:53:41 PM PDT 24
Peak memory 199752 kb
Host smart-2f7f8599-2121-476a-9e44-9281848e6644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3783109163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3783109163
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.949862503
Short name T417
Test name
Test status
Simulation time 30701551665 ps
CPU time 84.79 seconds
Started Jul 24 06:52:41 PM PDT 24
Finished Jul 24 06:54:06 PM PDT 24
Peak memory 199784 kb
Host smart-36387735-33c8-49a6-9fe8-ccef7d7bdd7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=949862503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.949862503
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2154848867
Short name T23
Test name
Test status
Simulation time 242593537068 ps
CPU time 671.75 seconds
Started Jul 24 06:52:46 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 199824 kb
Host smart-f8a3d306-5306-40de-8702-017694277d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2154848867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2154848867
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2080055386
Short name T69
Test name
Test status
Simulation time 190593729373 ps
CPU time 2417.19 seconds
Started Jul 24 06:52:42 PM PDT 24
Finished Jul 24 07:33:00 PM PDT 24
Peak memory 216184 kb
Host smart-e3db30a9-d9e3-40d1-9bf4-120dec97f691
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2080055386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2080055386
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1311050861
Short name T1
Test name
Test status
Simulation time 208155419348 ps
CPU time 2487.44 seconds
Started Jul 24 06:52:44 PM PDT 24
Finished Jul 24 07:34:12 PM PDT 24
Peak memory 216208 kb
Host smart-10460b33-cf3e-4a9a-8832-595f9bd0c7c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1311050861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1311050861
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.976854671
Short name T441
Test name
Test status
Simulation time 15829322535 ps
CPU time 116.5 seconds
Started Jul 24 06:52:43 PM PDT 24
Finished Jul 24 06:54:40 PM PDT 24
Peak memory 199864 kb
Host smart-8db244b8-9f8a-4661-8a45-275cc90c27db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976854671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.976854671
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3037812673
Short name T325
Test name
Test status
Simulation time 20444866 ps
CPU time 0.61 seconds
Started Jul 24 06:56:04 PM PDT 24
Finished Jul 24 06:56:04 PM PDT 24
Peak memory 195352 kb
Host smart-1fbe5814-2506-4af2-af5b-a167fa07f444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037812673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3037812673
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.119296224
Short name T33
Test name
Test status
Simulation time 3189728404 ps
CPU time 87.22 seconds
Started Jul 24 06:55:57 PM PDT 24
Finished Jul 24 06:57:24 PM PDT 24
Peak memory 199800 kb
Host smart-44a24969-183d-41e9-98f4-6c5af8086371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119296224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.119296224
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3956895746
Short name T402
Test name
Test status
Simulation time 6263296137 ps
CPU time 13.26 seconds
Started Jul 24 06:55:56 PM PDT 24
Finished Jul 24 06:56:09 PM PDT 24
Peak memory 199824 kb
Host smart-1b9fe135-b3d4-45e1-8686-f29f1fdb62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956895746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3956895746
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1306215675
Short name T305
Test name
Test status
Simulation time 16164550956 ps
CPU time 911.89 seconds
Started Jul 24 06:55:56 PM PDT 24
Finished Jul 24 07:11:08 PM PDT 24
Peak memory 722172 kb
Host smart-3f4ed27b-b650-485b-b30f-c71cfa79918f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306215675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1306215675
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3939579664
Short name T220
Test name
Test status
Simulation time 6474794624 ps
CPU time 80.33 seconds
Started Jul 24 06:55:57 PM PDT 24
Finished Jul 24 06:57:17 PM PDT 24
Peak memory 199716 kb
Host smart-7a200a6f-7599-4729-9237-0c006029a616
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939579664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3939579664
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2666474615
Short name T413
Test name
Test status
Simulation time 6037726792 ps
CPU time 181.88 seconds
Started Jul 24 06:55:53 PM PDT 24
Finished Jul 24 06:58:55 PM PDT 24
Peak memory 208024 kb
Host smart-5e2490d3-5134-4b55-9431-5fe80256e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666474615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2666474615
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2755243160
Short name T50
Test name
Test status
Simulation time 38967391 ps
CPU time 1.24 seconds
Started Jul 24 06:55:53 PM PDT 24
Finished Jul 24 06:55:55 PM PDT 24
Peak memory 199692 kb
Host smart-f98fc890-51c9-4e6d-9316-90625c500095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755243160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2755243160
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2667610218
Short name T79
Test name
Test status
Simulation time 263592906214 ps
CPU time 2082.13 seconds
Started Jul 24 06:55:55 PM PDT 24
Finished Jul 24 07:30:37 PM PDT 24
Peak memory 766868 kb
Host smart-cd86ae18-0583-4277-b0bf-05ef8ca119e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667610218 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2667610218
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2191205966
Short name T335
Test name
Test status
Simulation time 12998903825 ps
CPU time 112.24 seconds
Started Jul 24 06:55:54 PM PDT 24
Finished Jul 24 06:57:47 PM PDT 24
Peak memory 199780 kb
Host smart-cf7817d5-ba7c-4d10-9e52-a30c6b575e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191205966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2191205966
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.337814274
Short name T476
Test name
Test status
Simulation time 14357703 ps
CPU time 0.58 seconds
Started Jul 24 06:56:05 PM PDT 24
Finished Jul 24 06:56:06 PM PDT 24
Peak memory 195644 kb
Host smart-525d4407-944b-4b3d-8370-e1829c71f39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337814274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.337814274
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3026707273
Short name T293
Test name
Test status
Simulation time 894244038 ps
CPU time 50.13 seconds
Started Jul 24 06:56:00 PM PDT 24
Finished Jul 24 06:56:51 PM PDT 24
Peak memory 199704 kb
Host smart-2f333715-f883-46e9-aa47-571f91823e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026707273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3026707273
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2686442451
Short name T410
Test name
Test status
Simulation time 36860592651 ps
CPU time 38.85 seconds
Started Jul 24 06:56:00 PM PDT 24
Finished Jul 24 06:56:39 PM PDT 24
Peak memory 199772 kb
Host smart-db600fe3-808a-4ea3-bff3-5f03efc86217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686442451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2686442451
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1786732573
Short name T399
Test name
Test status
Simulation time 2333813694 ps
CPU time 473.48 seconds
Started Jul 24 06:55:59 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 675680 kb
Host smart-49f00dec-8a7d-4d3e-b08e-da900afce071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786732573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1786732573
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1799852054
Short name T528
Test name
Test status
Simulation time 21537399252 ps
CPU time 298.05 seconds
Started Jul 24 06:56:01 PM PDT 24
Finished Jul 24 07:00:59 PM PDT 24
Peak memory 199800 kb
Host smart-444bb938-61a9-449e-9aa0-899d78576c07
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799852054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1799852054
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.888196836
Short name T430
Test name
Test status
Simulation time 13250091203 ps
CPU time 70.26 seconds
Started Jul 24 06:56:01 PM PDT 24
Finished Jul 24 06:57:11 PM PDT 24
Peak memory 199728 kb
Host smart-61637e11-4bbf-437b-9f9f-d29cc1ebe7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888196836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.888196836
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.375852067
Short name T412
Test name
Test status
Simulation time 1775726277 ps
CPU time 15.78 seconds
Started Jul 24 06:56:01 PM PDT 24
Finished Jul 24 06:56:17 PM PDT 24
Peak memory 199736 kb
Host smart-43840b58-5cbc-4ec6-ab9c-7bcc34046620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375852067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.375852067
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1410354451
Short name T309
Test name
Test status
Simulation time 481940726945 ps
CPU time 1286.12 seconds
Started Jul 24 06:56:08 PM PDT 24
Finished Jul 24 07:17:34 PM PDT 24
Peak memory 620348 kb
Host smart-bcf0d937-744a-4a42-9330-891728cd8a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410354451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1410354451
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1132297118
Short name T130
Test name
Test status
Simulation time 11833917304 ps
CPU time 83.15 seconds
Started Jul 24 06:56:00 PM PDT 24
Finished Jul 24 06:57:23 PM PDT 24
Peak memory 199792 kb
Host smart-7358a07c-a3b1-41b4-9ec9-f30fd3b02c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132297118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1132297118
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3809775309
Short name T369
Test name
Test status
Simulation time 11406012 ps
CPU time 0.59 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:56:12 PM PDT 24
Peak memory 195356 kb
Host smart-7c5833b5-98db-4c0f-84d1-0d249134c7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809775309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3809775309
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.297771927
Short name T154
Test name
Test status
Simulation time 1877678137 ps
CPU time 59.26 seconds
Started Jul 24 06:56:05 PM PDT 24
Finished Jul 24 06:57:05 PM PDT 24
Peak memory 199716 kb
Host smart-798c2df9-166d-45cc-a95d-46b8c8408915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297771927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.297771927
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.733568692
Short name T168
Test name
Test status
Simulation time 3985618130 ps
CPU time 50.45 seconds
Started Jul 24 06:56:07 PM PDT 24
Finished Jul 24 06:56:57 PM PDT 24
Peak memory 199804 kb
Host smart-4eb0c3eb-0b94-442f-8dde-81be8dca849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733568692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.733568692
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1030448965
Short name T336
Test name
Test status
Simulation time 22736867217 ps
CPU time 1005.08 seconds
Started Jul 24 06:56:06 PM PDT 24
Finished Jul 24 07:12:52 PM PDT 24
Peak memory 705868 kb
Host smart-1b4c74e8-086a-4f96-94e7-4da4c1d9c875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030448965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1030448965
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3451285677
Short name T84
Test name
Test status
Simulation time 15442684751 ps
CPU time 218.28 seconds
Started Jul 24 06:56:06 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 199744 kb
Host smart-132ed289-4615-4c96-8c14-38d61762b85b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451285677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3451285677
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1366679702
Short name T326
Test name
Test status
Simulation time 107284768477 ps
CPU time 211.35 seconds
Started Jul 24 06:56:06 PM PDT 24
Finished Jul 24 06:59:37 PM PDT 24
Peak memory 199724 kb
Host smart-2793bcb2-1c42-4bc1-a178-c6729f3982d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366679702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1366679702
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1306299909
Short name T483
Test name
Test status
Simulation time 296612494 ps
CPU time 6.23 seconds
Started Jul 24 06:56:06 PM PDT 24
Finished Jul 24 06:56:12 PM PDT 24
Peak memory 199712 kb
Host smart-55a9bcf4-f045-4551-89ab-913c67823b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306299909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1306299909
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2982907005
Short name T492
Test name
Test status
Simulation time 5473790708 ps
CPU time 154.26 seconds
Started Jul 24 06:56:10 PM PDT 24
Finished Jul 24 06:58:44 PM PDT 24
Peak memory 199828 kb
Host smart-440b4715-4a4f-4aa9-925e-23b275946508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982907005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2982907005
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1249641025
Short name T316
Test name
Test status
Simulation time 30466175707 ps
CPU time 113.55 seconds
Started Jul 24 06:56:06 PM PDT 24
Finished Jul 24 06:57:59 PM PDT 24
Peak memory 199836 kb
Host smart-91ee894b-f70d-4dce-bf84-44631c033515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249641025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1249641025
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2998129603
Short name T216
Test name
Test status
Simulation time 174719852 ps
CPU time 0.61 seconds
Started Jul 24 06:56:13 PM PDT 24
Finished Jul 24 06:56:13 PM PDT 24
Peak memory 196360 kb
Host smart-89e132b9-fd37-4410-b4eb-119e6ddde057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998129603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2998129603
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3497893195
Short name T152
Test name
Test status
Simulation time 660938779 ps
CPU time 37.67 seconds
Started Jul 24 06:56:12 PM PDT 24
Finished Jul 24 06:56:49 PM PDT 24
Peak memory 199736 kb
Host smart-5e250a46-240b-4278-a14e-e159c80ce6df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497893195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3497893195
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.849268062
Short name T173
Test name
Test status
Simulation time 58065778 ps
CPU time 2.03 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:56:13 PM PDT 24
Peak memory 199704 kb
Host smart-70998e32-14cd-4f97-b165-e61c05fb2042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849268062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.849268062
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1368173454
Short name T103
Test name
Test status
Simulation time 12674988 ps
CPU time 0.78 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:56:12 PM PDT 24
Peak memory 199540 kb
Host smart-bbd1aa02-e2bd-4312-9b3a-858b0ec79f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368173454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1368173454
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1900725080
Short name T243
Test name
Test status
Simulation time 7993326181 ps
CPU time 206.78 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 199664 kb
Host smart-d9d75aad-7b22-4be6-a0ae-8338f5d1675b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900725080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1900725080
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3430318811
Short name T403
Test name
Test status
Simulation time 3741665417 ps
CPU time 26.16 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:56:37 PM PDT 24
Peak memory 199780 kb
Host smart-582045bb-76b7-4eae-ac59-44cea0b0e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430318811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3430318811
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.859410774
Short name T353
Test name
Test status
Simulation time 321652790 ps
CPU time 4.4 seconds
Started Jul 24 06:56:12 PM PDT 24
Finished Jul 24 06:56:17 PM PDT 24
Peak memory 199704 kb
Host smart-508c9b46-0cd9-46ff-9b3f-3ff24511d18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859410774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.859410774
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2551269507
Short name T36
Test name
Test status
Simulation time 114423596713 ps
CPU time 200.04 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:59:31 PM PDT 24
Peak memory 199828 kb
Host smart-54443c61-e0fc-4074-a9cd-246eeb4e9070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551269507 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2551269507
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.685750842
Short name T506
Test name
Test status
Simulation time 16300222100 ps
CPU time 56.1 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:57:07 PM PDT 24
Peak memory 199768 kb
Host smart-b18c484d-6d9f-49dd-83dc-d46c78c00226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685750842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.685750842
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.946238006
Short name T397
Test name
Test status
Simulation time 38136857 ps
CPU time 0.61 seconds
Started Jul 24 06:56:18 PM PDT 24
Finished Jul 24 06:56:19 PM PDT 24
Peak memory 195736 kb
Host smart-11164875-0012-4c75-a724-3e39f6fa9cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946238006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.946238006
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.824444777
Short name T20
Test name
Test status
Simulation time 1563641487 ps
CPU time 89.92 seconds
Started Jul 24 06:56:12 PM PDT 24
Finished Jul 24 06:57:42 PM PDT 24
Peak memory 199712 kb
Host smart-97b47b6d-0bdd-4080-8040-d52994e224ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824444777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.824444777
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2032437297
Short name T495
Test name
Test status
Simulation time 1082696238 ps
CPU time 30.95 seconds
Started Jul 24 06:56:19 PM PDT 24
Finished Jul 24 06:56:50 PM PDT 24
Peak memory 199700 kb
Host smart-4b3c541f-2739-4e42-9f64-86d50580dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032437297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2032437297
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1372178529
Short name T361
Test name
Test status
Simulation time 7563794758 ps
CPU time 1026.48 seconds
Started Jul 24 06:56:18 PM PDT 24
Finished Jul 24 07:13:25 PM PDT 24
Peak memory 757544 kb
Host smart-37eebfa2-749f-464e-a184-78971735df61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372178529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1372178529
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2442630664
Short name T269
Test name
Test status
Simulation time 63084642238 ps
CPU time 122.11 seconds
Started Jul 24 06:56:19 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 199824 kb
Host smart-f0f1b1ef-f441-4f36-ad1f-733f5c72dda6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442630664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2442630664
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1961229680
Short name T52
Test name
Test status
Simulation time 5112249164 ps
CPU time 69.86 seconds
Started Jul 24 06:56:11 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 199792 kb
Host smart-143e271d-50f7-444a-9ca1-4896913ca1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961229680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1961229680
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3373909270
Short name T51
Test name
Test status
Simulation time 671228482 ps
CPU time 4.46 seconds
Started Jul 24 06:56:12 PM PDT 24
Finished Jul 24 06:56:16 PM PDT 24
Peak memory 199720 kb
Host smart-99936f3e-6e25-43f7-82e9-0843748c967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373909270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3373909270
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.49457270
Short name T304
Test name
Test status
Simulation time 4773174822 ps
CPU time 137.28 seconds
Started Jul 24 06:56:18 PM PDT 24
Finished Jul 24 06:58:35 PM PDT 24
Peak memory 208016 kb
Host smart-605af1ac-7f16-4006-81b4-09ddccabd639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49457270 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.49457270
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.162293381
Short name T348
Test name
Test status
Simulation time 662844338 ps
CPU time 34.83 seconds
Started Jul 24 06:56:19 PM PDT 24
Finished Jul 24 06:56:54 PM PDT 24
Peak memory 199636 kb
Host smart-cfe219e5-2a91-4332-b6da-56ab7b6c2b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162293381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.162293381
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.402250635
Short name T16
Test name
Test status
Simulation time 11685152 ps
CPU time 0.58 seconds
Started Jul 24 06:56:26 PM PDT 24
Finished Jul 24 06:56:27 PM PDT 24
Peak memory 194588 kb
Host smart-5f2a275c-bff6-42b2-953e-e5b0dd16cca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402250635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.402250635
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.981384757
Short name T427
Test name
Test status
Simulation time 21597975458 ps
CPU time 120.89 seconds
Started Jul 24 06:56:25 PM PDT 24
Finished Jul 24 06:58:26 PM PDT 24
Peak memory 216084 kb
Host smart-c00a7a39-41da-4edc-9a88-774f76f5b2b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981384757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.981384757
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1768491604
Short name T25
Test name
Test status
Simulation time 12020190017 ps
CPU time 37.03 seconds
Started Jul 24 06:56:23 PM PDT 24
Finished Jul 24 06:57:01 PM PDT 24
Peak memory 199648 kb
Host smart-a00fe7f2-b3ca-47e8-822e-ebd4a61a602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768491604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1768491604
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.634429184
Short name T184
Test name
Test status
Simulation time 2034902409 ps
CPU time 410.47 seconds
Started Jul 24 06:56:27 PM PDT 24
Finished Jul 24 07:03:17 PM PDT 24
Peak memory 630332 kb
Host smart-3d8b8a69-96d7-43e2-80b2-d092317cd0de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634429184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.634429184
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.584736703
Short name T381
Test name
Test status
Simulation time 5376921354 ps
CPU time 41.61 seconds
Started Jul 24 06:56:22 PM PDT 24
Finished Jul 24 06:57:04 PM PDT 24
Peak memory 199784 kb
Host smart-6efab684-ae1f-472f-941c-e78d3e78a073
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584736703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.584736703
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1296978983
Short name T306
Test name
Test status
Simulation time 7766541425 ps
CPU time 72.86 seconds
Started Jul 24 06:56:24 PM PDT 24
Finished Jul 24 06:57:37 PM PDT 24
Peak memory 199752 kb
Host smart-a0d89ef2-dadd-4d00-bdb4-4b9d300e3a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296978983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1296978983
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1213528759
Short name T362
Test name
Test status
Simulation time 551079697 ps
CPU time 6.81 seconds
Started Jul 24 06:56:19 PM PDT 24
Finished Jul 24 06:56:26 PM PDT 24
Peak memory 199636 kb
Host smart-5ccee81f-a60c-4adf-9f6d-5c0b1bcc9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213528759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1213528759
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3134847305
Short name T443
Test name
Test status
Simulation time 229275276792 ps
CPU time 1805.05 seconds
Started Jul 24 06:56:24 PM PDT 24
Finished Jul 24 07:26:30 PM PDT 24
Peak memory 787520 kb
Host smart-a50fffec-c4b4-4179-977f-c794c2c0c591
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134847305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3134847305
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.554310029
Short name T385
Test name
Test status
Simulation time 10597269866 ps
CPU time 115.11 seconds
Started Jul 24 06:56:27 PM PDT 24
Finished Jul 24 06:58:22 PM PDT 24
Peak memory 199804 kb
Host smart-10953681-edfc-4ca2-93b1-b52bd6022e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554310029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.554310029
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.235201975
Short name T297
Test name
Test status
Simulation time 80245393 ps
CPU time 0.58 seconds
Started Jul 24 06:56:31 PM PDT 24
Finished Jul 24 06:56:32 PM PDT 24
Peak memory 194716 kb
Host smart-04da9df9-5eb9-4998-bc05-c5ab8e7d70c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235201975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.235201975
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4189121894
Short name T490
Test name
Test status
Simulation time 4233909196 ps
CPU time 60.79 seconds
Started Jul 24 06:56:25 PM PDT 24
Finished Jul 24 06:57:26 PM PDT 24
Peak memory 199844 kb
Host smart-2dbe25ca-51bc-4c1b-9529-c9b9246fa073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189121894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4189121894
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2547513082
Short name T95
Test name
Test status
Simulation time 81416172 ps
CPU time 4.08 seconds
Started Jul 24 06:56:25 PM PDT 24
Finished Jul 24 06:56:30 PM PDT 24
Peak memory 199668 kb
Host smart-3adb5b94-a168-4dd0-99e6-4aa0701ab815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547513082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2547513082
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2472561923
Short name T281
Test name
Test status
Simulation time 13619952993 ps
CPU time 1450.22 seconds
Started Jul 24 06:56:25 PM PDT 24
Finished Jul 24 07:20:36 PM PDT 24
Peak memory 782728 kb
Host smart-a1622c7c-bc82-477a-9134-f66ecb19dbba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472561923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2472561923
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4019974720
Short name T219
Test name
Test status
Simulation time 30841267002 ps
CPU time 100.32 seconds
Started Jul 24 06:56:31 PM PDT 24
Finished Jul 24 06:58:12 PM PDT 24
Peak memory 199804 kb
Host smart-93602826-427f-485e-9b0c-202eba157246
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019974720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4019974720
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2035047154
Short name T28
Test name
Test status
Simulation time 4137551752 ps
CPU time 36.93 seconds
Started Jul 24 06:56:28 PM PDT 24
Finished Jul 24 06:57:05 PM PDT 24
Peak memory 199772 kb
Host smart-21df725a-df10-40c5-8c7d-9da554df9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035047154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2035047154
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3665005826
Short name T151
Test name
Test status
Simulation time 4141221153 ps
CPU time 14.59 seconds
Started Jul 24 06:56:25 PM PDT 24
Finished Jul 24 06:56:40 PM PDT 24
Peak memory 199768 kb
Host smart-7a23d56d-2f2a-4ea4-9c79-0f1897400358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665005826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3665005826
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4205474687
Short name T327
Test name
Test status
Simulation time 561242514754 ps
CPU time 1062.73 seconds
Started Jul 24 06:56:32 PM PDT 24
Finished Jul 24 07:14:15 PM PDT 24
Peak memory 698700 kb
Host smart-6f068381-8a73-482b-93a1-23fa0286c635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205474687 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4205474687
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3185105113
Short name T41
Test name
Test status
Simulation time 18307126363 ps
CPU time 56.67 seconds
Started Jul 24 06:56:30 PM PDT 24
Finished Jul 24 06:57:27 PM PDT 24
Peak memory 199804 kb
Host smart-2a5931dc-afce-4fa1-9146-ad09bc30934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185105113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3185105113
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.735874469
Short name T98
Test name
Test status
Simulation time 32376349 ps
CPU time 0.57 seconds
Started Jul 24 06:56:39 PM PDT 24
Finished Jul 24 06:56:40 PM PDT 24
Peak memory 195692 kb
Host smart-6d3df0e0-a84b-4149-af52-3f5583ebec99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735874469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.735874469
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2571429412
Short name T275
Test name
Test status
Simulation time 136367725 ps
CPU time 7.83 seconds
Started Jul 24 06:56:31 PM PDT 24
Finished Jul 24 06:56:39 PM PDT 24
Peak memory 199760 kb
Host smart-4fa81ba0-7d94-4434-bf9b-505c5a9cc3ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571429412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2571429412
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2285548761
Short name T493
Test name
Test status
Simulation time 684105640 ps
CPU time 9.48 seconds
Started Jul 24 06:56:37 PM PDT 24
Finished Jul 24 06:56:46 PM PDT 24
Peak memory 199676 kb
Host smart-d31803dc-90cf-46f3-b77d-0568fe8a401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285548761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2285548761
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4052249288
Short name T258
Test name
Test status
Simulation time 756571781 ps
CPU time 16.48 seconds
Started Jul 24 06:56:36 PM PDT 24
Finished Jul 24 06:56:53 PM PDT 24
Peak memory 230028 kb
Host smart-9ab2de05-bdb8-4ae6-966e-0ae1477e5d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052249288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4052249288
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4079519458
Short name T408
Test name
Test status
Simulation time 1483666186 ps
CPU time 41.19 seconds
Started Jul 24 06:56:40 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 199744 kb
Host smart-aeea22b2-ff25-493e-9e7a-05eb5f011bd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079519458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4079519458
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2481481532
Short name T509
Test name
Test status
Simulation time 3923139491 ps
CPU time 30.83 seconds
Started Jul 24 06:56:33 PM PDT 24
Finished Jul 24 06:57:04 PM PDT 24
Peak memory 199756 kb
Host smart-44794f40-460b-4fa1-985e-4bf009637318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481481532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2481481532
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3189434254
Short name T147
Test name
Test status
Simulation time 1699553499 ps
CPU time 14.55 seconds
Started Jul 24 06:56:30 PM PDT 24
Finished Jul 24 06:56:45 PM PDT 24
Peak memory 199720 kb
Host smart-d28d40c1-cf39-4dd2-bac4-975fb99b3c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189434254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3189434254
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3245680704
Short name T239
Test name
Test status
Simulation time 463924018468 ps
CPU time 2989.77 seconds
Started Jul 24 06:56:36 PM PDT 24
Finished Jul 24 07:46:27 PM PDT 24
Peak memory 750072 kb
Host smart-a1090f6c-db21-4805-8033-8bfb30e8f193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245680704 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3245680704
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1195408914
Short name T71
Test name
Test status
Simulation time 12480678026 ps
CPU time 159.47 seconds
Started Jul 24 06:56:44 PM PDT 24
Finished Jul 24 06:59:23 PM PDT 24
Peak memory 199764 kb
Host smart-c6497696-2bf5-4e74-8e6d-4c8f01b1a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195408914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1195408914
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3257902465
Short name T265
Test name
Test status
Simulation time 43875500 ps
CPU time 0.58 seconds
Started Jul 24 06:56:46 PM PDT 24
Finished Jul 24 06:56:47 PM PDT 24
Peak memory 195592 kb
Host smart-cf4188fc-4b7e-4156-a4e7-1ee28e6d4d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257902465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3257902465
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2397059008
Short name T373
Test name
Test status
Simulation time 2472690259 ps
CPU time 38.9 seconds
Started Jul 24 06:56:42 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 199760 kb
Host smart-2a2353d3-bb60-48eb-8f66-3753850e9eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397059008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2397059008
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.775232702
Short name T201
Test name
Test status
Simulation time 166542370 ps
CPU time 8.88 seconds
Started Jul 24 06:56:43 PM PDT 24
Finished Jul 24 06:56:52 PM PDT 24
Peak memory 199704 kb
Host smart-7cc3c637-a112-4c74-872a-3525c2599180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775232702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.775232702
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3878772693
Short name T489
Test name
Test status
Simulation time 12306939397 ps
CPU time 1210.67 seconds
Started Jul 24 06:56:46 PM PDT 24
Finished Jul 24 07:16:57 PM PDT 24
Peak memory 759412 kb
Host smart-ee6cc38e-1f17-4f1b-8f23-c3307fbf27da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878772693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3878772693
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3839818098
Short name T255
Test name
Test status
Simulation time 23807910844 ps
CPU time 99.3 seconds
Started Jul 24 06:56:43 PM PDT 24
Finished Jul 24 06:58:22 PM PDT 24
Peak memory 199876 kb
Host smart-c0cb1b12-7572-4ba3-b00b-4b765d101695
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839818098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3839818098
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2781259440
Short name T498
Test name
Test status
Simulation time 7493834632 ps
CPU time 87.81 seconds
Started Jul 24 06:56:42 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 199740 kb
Host smart-1d68fb34-0666-4b6f-a062-1bf5dc1dafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781259440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2781259440
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3092003031
Short name T183
Test name
Test status
Simulation time 179965118 ps
CPU time 2.38 seconds
Started Jul 24 06:56:42 PM PDT 24
Finished Jul 24 06:56:44 PM PDT 24
Peak memory 199708 kb
Host smart-3109efb0-3e69-48a9-ab0f-abdaf8e6da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092003031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3092003031
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3824704473
Short name T519
Test name
Test status
Simulation time 361334270713 ps
CPU time 2560.61 seconds
Started Jul 24 06:56:43 PM PDT 24
Finished Jul 24 07:39:24 PM PDT 24
Peak memory 757372 kb
Host smart-085347f2-835a-4a3d-aac0-e3ead43b0068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824704473 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3824704473
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3836284563
Short name T101
Test name
Test status
Simulation time 48877720930 ps
CPU time 64.99 seconds
Started Jul 24 06:56:43 PM PDT 24
Finished Jul 24 06:57:48 PM PDT 24
Peak memory 199840 kb
Host smart-17536718-7545-42ea-8e8c-a86f370b5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836284563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3836284563
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.456341491
Short name T452
Test name
Test status
Simulation time 47076409 ps
CPU time 0.61 seconds
Started Jul 24 06:56:57 PM PDT 24
Finished Jul 24 06:56:58 PM PDT 24
Peak memory 196416 kb
Host smart-e738a78f-a5c1-443f-a73f-52540faed912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456341491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.456341491
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.220030400
Short name T196
Test name
Test status
Simulation time 3062608835 ps
CPU time 38.65 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:57:29 PM PDT 24
Peak memory 199720 kb
Host smart-9eb5c101-2f8f-427b-a626-97f5b9004b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220030400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.220030400
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3081621073
Short name T38
Test name
Test status
Simulation time 24147985462 ps
CPU time 28.73 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:57:19 PM PDT 24
Peak memory 199748 kb
Host smart-a4a35532-dc5b-429b-8eba-69bfe5642e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081621073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3081621073
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2667131361
Short name T198
Test name
Test status
Simulation time 11172377749 ps
CPU time 1005.41 seconds
Started Jul 24 06:56:49 PM PDT 24
Finished Jul 24 07:13:34 PM PDT 24
Peak memory 739824 kb
Host smart-86655ec0-96f1-409d-ae94-25f591696287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667131361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2667131361
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3952469875
Short name T261
Test name
Test status
Simulation time 15277880798 ps
CPU time 189.46 seconds
Started Jul 24 06:56:52 PM PDT 24
Finished Jul 24 07:00:02 PM PDT 24
Peak memory 199780 kb
Host smart-07cc6fc4-cbbf-4e05-91cc-e109c353d869
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952469875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3952469875
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1314783286
Short name T301
Test name
Test status
Simulation time 9531257055 ps
CPU time 138.54 seconds
Started Jul 24 06:56:48 PM PDT 24
Finished Jul 24 06:59:07 PM PDT 24
Peak memory 199684 kb
Host smart-0454f9dd-04b8-40c5-a4e0-57e70dd4bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314783286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1314783286
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2418166768
Short name T334
Test name
Test status
Simulation time 2115966414 ps
CPU time 6.13 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:56:56 PM PDT 24
Peak memory 199728 kb
Host smart-71210130-8eda-463d-9777-c9d4cfe52e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418166768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2418166768
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2413001631
Short name T310
Test name
Test status
Simulation time 56556342508 ps
CPU time 1990.58 seconds
Started Jul 24 06:56:54 PM PDT 24
Finished Jul 24 07:30:05 PM PDT 24
Peak memory 774192 kb
Host smart-fd2b25f4-2ece-46a6-8390-1b99b683adcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413001631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2413001631
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4151268581
Short name T259
Test name
Test status
Simulation time 7088053595 ps
CPU time 95.49 seconds
Started Jul 24 06:56:49 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 199840 kb
Host smart-9ef847a6-7eae-4d08-9564-4a46ed39612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151268581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4151268581
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1902213621
Short name T524
Test name
Test status
Simulation time 13184377 ps
CPU time 0.6 seconds
Started Jul 24 06:52:50 PM PDT 24
Finished Jul 24 06:52:51 PM PDT 24
Peak memory 195624 kb
Host smart-f925880f-08f0-4743-9bd4-7719d9e02a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902213621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1902213621
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2640036946
Short name T445
Test name
Test status
Simulation time 4188218481 ps
CPU time 61.34 seconds
Started Jul 24 06:52:41 PM PDT 24
Finished Jul 24 06:53:42 PM PDT 24
Peak memory 199788 kb
Host smart-66125176-505e-4222-834c-bc50e57fab1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640036946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2640036946
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3360333586
Short name T384
Test name
Test status
Simulation time 573855604 ps
CPU time 9.5 seconds
Started Jul 24 06:52:47 PM PDT 24
Finished Jul 24 06:52:56 PM PDT 24
Peak memory 199628 kb
Host smart-f422f9df-3f78-4552-b665-4491ed0ae94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360333586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3360333586
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3265459595
Short name T167
Test name
Test status
Simulation time 265771758 ps
CPU time 31.87 seconds
Started Jul 24 06:52:50 PM PDT 24
Finished Jul 24 06:53:22 PM PDT 24
Peak memory 258576 kb
Host smart-820a13d2-5b8c-478e-bc83-d2070c6c2322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265459595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3265459595
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1881874608
Short name T221
Test name
Test status
Simulation time 6955346451 ps
CPU time 138.47 seconds
Started Jul 24 06:52:49 PM PDT 24
Finished Jul 24 06:55:08 PM PDT 24
Peak memory 199796 kb
Host smart-5276bd7c-6c22-47ff-8d8b-ef7af148fbab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881874608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1881874608
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1771579916
Short name T202
Test name
Test status
Simulation time 318945612 ps
CPU time 19.62 seconds
Started Jul 24 06:52:43 PM PDT 24
Finished Jul 24 06:53:03 PM PDT 24
Peak memory 199672 kb
Host smart-9d99967f-8f05-44d5-9605-e705bf7801d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771579916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1771579916
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.34278396
Short name T391
Test name
Test status
Simulation time 42332359 ps
CPU time 0.67 seconds
Started Jul 24 06:52:46 PM PDT 24
Finished Jul 24 06:52:47 PM PDT 24
Peak memory 196360 kb
Host smart-f97b5f92-3bc3-46e0-8175-ae3ebda6d0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34278396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.34278396
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2872306136
Short name T8
Test name
Test status
Simulation time 130895040197 ps
CPU time 613.71 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 07:03:07 PM PDT 24
Peak memory 215932 kb
Host smart-6231e625-f69c-4589-8e89-8f40509a0dc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872306136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2872306136
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3429244598
Short name T30
Test name
Test status
Simulation time 1893642435 ps
CPU time 33.03 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 06:53:27 PM PDT 24
Peak memory 199740 kb
Host smart-0710f146-933e-445f-a1b3-cf24f66e1896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429244598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3429244598
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3643369538
Short name T318
Test name
Test status
Simulation time 305915380 ps
CPU time 4.9 seconds
Started Jul 24 06:52:59 PM PDT 24
Finished Jul 24 06:53:04 PM PDT 24
Peak memory 199692 kb
Host smart-9be006b2-07fb-4d5e-9115-f340267269c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643369538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3643369538
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1089062912
Short name T527
Test name
Test status
Simulation time 34413427189 ps
CPU time 33.64 seconds
Started Jul 24 06:52:48 PM PDT 24
Finished Jul 24 06:53:21 PM PDT 24
Peak memory 199740 kb
Host smart-aa81b5d1-9868-48fe-a11b-b4d263a5deb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089062912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1089062912
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2040109053
Short name T364
Test name
Test status
Simulation time 1958648462 ps
CPU time 438.74 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 07:00:12 PM PDT 24
Peak memory 629664 kb
Host smart-38332897-66c7-4946-8a84-28ecb154cbb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040109053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2040109053
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4152143903
Short name T7
Test name
Test status
Simulation time 3968023744 ps
CPU time 233.91 seconds
Started Jul 24 06:52:49 PM PDT 24
Finished Jul 24 06:56:43 PM PDT 24
Peak memory 199848 kb
Host smart-d91b0f68-cf1b-49dc-983d-f33ebbcbc36d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152143903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4152143903
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2787469512
Short name T464
Test name
Test status
Simulation time 1309454589 ps
CPU time 77.18 seconds
Started Jul 24 06:52:48 PM PDT 24
Finished Jul 24 06:54:06 PM PDT 24
Peak memory 199704 kb
Host smart-87521ddd-bf6a-4777-806f-b7e9792d38b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787469512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2787469512
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1754830097
Short name T270
Test name
Test status
Simulation time 267161490 ps
CPU time 4.59 seconds
Started Jul 24 06:52:48 PM PDT 24
Finished Jul 24 06:52:53 PM PDT 24
Peak memory 199708 kb
Host smart-9a9ec37f-2ba3-4797-a2c1-edef662e4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754830097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1754830097
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4221448000
Short name T416
Test name
Test status
Simulation time 271872556366 ps
CPU time 1565.66 seconds
Started Jul 24 06:52:59 PM PDT 24
Finished Jul 24 07:19:05 PM PDT 24
Peak memory 649232 kb
Host smart-e0cd8cb5-e319-42cd-91c8-f2459ac7d525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221448000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4221448000
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2548818969
Short name T29
Test name
Test status
Simulation time 994488847985 ps
CPU time 4072.95 seconds
Started Jul 24 06:52:50 PM PDT 24
Finished Jul 24 08:00:43 PM PDT 24
Peak memory 786896 kb
Host smart-48562b10-623d-494b-abbd-66ce3cbe046d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548818969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2548818969
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1759095206
Short name T260
Test name
Test status
Simulation time 7874509965 ps
CPU time 36.34 seconds
Started Jul 24 06:52:49 PM PDT 24
Finished Jul 24 06:53:25 PM PDT 24
Peak memory 199772 kb
Host smart-89d544a4-dc88-4d63-b17a-144ba7dc067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759095206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1759095206
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1308114136
Short name T172
Test name
Test status
Simulation time 23848029 ps
CPU time 0.56 seconds
Started Jul 24 06:52:56 PM PDT 24
Finished Jul 24 06:52:57 PM PDT 24
Peak memory 194628 kb
Host smart-11847a9e-3730-4c51-8e32-2867885c582e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308114136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1308114136
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.525072996
Short name T264
Test name
Test status
Simulation time 2073745725 ps
CPU time 77.77 seconds
Started Jul 24 06:52:48 PM PDT 24
Finished Jul 24 06:54:06 PM PDT 24
Peak memory 199736 kb
Host smart-1b3ab2b7-1797-44dc-8b95-b19d8beb1caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525072996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.525072996
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2747559894
Short name T411
Test name
Test status
Simulation time 390488571 ps
CPU time 10.38 seconds
Started Jul 24 06:52:54 PM PDT 24
Finished Jul 24 06:53:05 PM PDT 24
Peak memory 199688 kb
Host smart-1d19e8d8-b2cf-4986-9642-bf4a70a737ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747559894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2747559894
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1758507553
Short name T292
Test name
Test status
Simulation time 9408057307 ps
CPU time 859.36 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 706084 kb
Host smart-3a5818a3-069d-4710-87d9-f850fbd9a9d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758507553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1758507553
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1366768410
Short name T48
Test name
Test status
Simulation time 3171430552 ps
CPU time 39.98 seconds
Started Jul 24 06:52:54 PM PDT 24
Finished Jul 24 06:53:35 PM PDT 24
Peak memory 199752 kb
Host smart-cbd4b2be-a626-40bb-9fee-4450b1fb9e83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366768410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1366768410
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.509382629
Short name T376
Test name
Test status
Simulation time 1634710637 ps
CPU time 97.95 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 06:54:31 PM PDT 24
Peak memory 199740 kb
Host smart-85ebc78c-f644-4f4b-9c75-2403ea6cd5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509382629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.509382629
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4148070153
Short name T491
Test name
Test status
Simulation time 1428539830 ps
CPU time 4.81 seconds
Started Jul 24 06:52:59 PM PDT 24
Finished Jul 24 06:53:04 PM PDT 24
Peak memory 199708 kb
Host smart-a112fba5-f309-48aa-bf41-f848fc0ef8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148070153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4148070153
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2742871489
Short name T429
Test name
Test status
Simulation time 185137113008 ps
CPU time 828.82 seconds
Started Jul 24 06:53:58 PM PDT 24
Finished Jul 24 07:07:47 PM PDT 24
Peak memory 199748 kb
Host smart-53cba112-be41-4894-b7ea-7f8533cab28d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742871489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2742871489
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2653526303
Short name T484
Test name
Test status
Simulation time 1434944784 ps
CPU time 58.64 seconds
Started Jul 24 06:52:55 PM PDT 24
Finished Jul 24 06:53:54 PM PDT 24
Peak memory 199768 kb
Host smart-0c755a09-5d00-415a-9faa-e7962d34e2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653526303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2653526303
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.806227041
Short name T241
Test name
Test status
Simulation time 13144337 ps
CPU time 0.58 seconds
Started Jul 24 06:52:58 PM PDT 24
Finished Jul 24 06:52:59 PM PDT 24
Peak memory 194716 kb
Host smart-35b94086-1561-4ec6-93d9-1351a0746fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806227041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.806227041
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4203649043
Short name T199
Test name
Test status
Simulation time 4523284394 ps
CPU time 66.23 seconds
Started Jul 24 06:52:55 PM PDT 24
Finished Jul 24 06:54:01 PM PDT 24
Peak memory 208004 kb
Host smart-0697b240-725c-4b22-8bd8-c3494bdcf48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203649043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4203649043
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.212481005
Short name T160
Test name
Test status
Simulation time 575581246 ps
CPU time 32.26 seconds
Started Jul 24 06:52:57 PM PDT 24
Finished Jul 24 06:53:30 PM PDT 24
Peak memory 199692 kb
Host smart-ba9a75c8-c02e-40dd-b7f9-f930d7d2fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212481005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.212481005
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1587482789
Short name T436
Test name
Test status
Simulation time 10830003113 ps
CPU time 1130.81 seconds
Started Jul 24 06:52:55 PM PDT 24
Finished Jul 24 07:11:46 PM PDT 24
Peak memory 682324 kb
Host smart-4af2ee09-9cb0-43b7-a2f5-16733b4ce951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587482789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1587482789
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2604491438
Short name T6
Test name
Test status
Simulation time 2575871934 ps
CPU time 145.88 seconds
Started Jul 24 06:53:00 PM PDT 24
Finished Jul 24 06:55:26 PM PDT 24
Peak memory 199780 kb
Host smart-063939f5-801e-4d2f-b7bc-f9aed8a149c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604491438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2604491438
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1214324000
Short name T56
Test name
Test status
Simulation time 8947098670 ps
CPU time 163.67 seconds
Started Jul 24 06:52:55 PM PDT 24
Finished Jul 24 06:55:38 PM PDT 24
Peak memory 199768 kb
Host smart-f1ca4412-a95d-4f2d-a0da-da854ccba2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214324000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1214324000
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3979765076
Short name T150
Test name
Test status
Simulation time 635613919 ps
CPU time 11.37 seconds
Started Jul 24 06:52:53 PM PDT 24
Finished Jul 24 06:53:05 PM PDT 24
Peak memory 199644 kb
Host smart-4b1c1103-88b1-4ba0-b514-1d2af2aec5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979765076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3979765076
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2387885188
Short name T526
Test name
Test status
Simulation time 80246905105 ps
CPU time 5109.02 seconds
Started Jul 24 06:53:02 PM PDT 24
Finished Jul 24 08:18:12 PM PDT 24
Peak memory 851096 kb
Host smart-715ced1c-886d-46fe-9eee-1ca1bb776a7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387885188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2387885188
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.488003878
Short name T31
Test name
Test status
Simulation time 122535040637 ps
CPU time 9550.11 seconds
Started Jul 24 06:53:00 PM PDT 24
Finished Jul 24 09:32:12 PM PDT 24
Peak memory 953636 kb
Host smart-90d1665d-f360-43b2-9532-42cba317f38c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488003878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.488003878
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1607263868
Short name T456
Test name
Test status
Simulation time 16964922582 ps
CPU time 55.48 seconds
Started Jul 24 06:53:02 PM PDT 24
Finished Jul 24 06:53:57 PM PDT 24
Peak memory 199836 kb
Host smart-1fc1658a-3041-4b27-8a2f-d33756fb8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607263868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1607263868
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3964326395
Short name T164
Test name
Test status
Simulation time 80196555 ps
CPU time 0.59 seconds
Started Jul 24 06:53:08 PM PDT 24
Finished Jul 24 06:53:09 PM PDT 24
Peak memory 196368 kb
Host smart-0c7f0f40-b5b2-415b-bb19-d56079e767c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964326395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3964326395
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3434986702
Short name T303
Test name
Test status
Simulation time 1683447755 ps
CPU time 21.25 seconds
Started Jul 24 06:53:02 PM PDT 24
Finished Jul 24 06:53:23 PM PDT 24
Peak memory 199732 kb
Host smart-cf5521c4-0363-444e-bc10-114545abc1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434986702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3434986702
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3514381535
Short name T294
Test name
Test status
Simulation time 3487269767 ps
CPU time 50.64 seconds
Started Jul 24 06:53:03 PM PDT 24
Finished Jul 24 06:53:54 PM PDT 24
Peak memory 199820 kb
Host smart-6754b93c-a85c-44a9-95f8-4567d26c969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514381535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3514381535
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2650325705
Short name T367
Test name
Test status
Simulation time 4770077899 ps
CPU time 187.1 seconds
Started Jul 24 06:53:03 PM PDT 24
Finished Jul 24 06:56:11 PM PDT 24
Peak memory 581900 kb
Host smart-7d2d53a0-5bd6-4393-b8e0-c6f5b664381c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650325705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2650325705
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4108459457
Short name T313
Test name
Test status
Simulation time 1670691972 ps
CPU time 5.76 seconds
Started Jul 24 06:53:03 PM PDT 24
Finished Jul 24 06:53:09 PM PDT 24
Peak memory 199696 kb
Host smart-5b93255e-5ad1-4acb-9340-98dada01b318
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108459457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4108459457
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3363338068
Short name T465
Test name
Test status
Simulation time 1752915470 ps
CPU time 98.98 seconds
Started Jul 24 06:53:00 PM PDT 24
Finished Jul 24 06:54:39 PM PDT 24
Peak memory 199656 kb
Host smart-f8bae286-8e1e-480a-b02a-42a51e3eee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363338068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3363338068
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1265745601
Short name T267
Test name
Test status
Simulation time 990166503 ps
CPU time 10.97 seconds
Started Jul 24 06:52:58 PM PDT 24
Finished Jul 24 06:53:09 PM PDT 24
Peak memory 199724 kb
Host smart-0b0b01b4-bc7c-4ecc-a500-45bc280dd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265745601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1265745601
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1160857124
Short name T328
Test name
Test status
Simulation time 45746898466 ps
CPU time 208.77 seconds
Started Jul 24 06:53:10 PM PDT 24
Finished Jul 24 06:56:39 PM PDT 24
Peak memory 199792 kb
Host smart-de6ae406-65df-4ab1-83eb-5ae90b78b25a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160857124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1160857124
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2020681899
Short name T15
Test name
Test status
Simulation time 812777305630 ps
CPU time 1238.81 seconds
Started Jul 24 06:53:09 PM PDT 24
Finished Jul 24 07:13:48 PM PDT 24
Peak memory 717864 kb
Host smart-e4730b92-4b88-4fc8-878b-ba726eaf0a3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020681899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2020681899
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2626068083
Short name T321
Test name
Test status
Simulation time 6017459596 ps
CPU time 51.49 seconds
Started Jul 24 06:53:04 PM PDT 24
Finished Jul 24 06:53:55 PM PDT 24
Peak memory 199852 kb
Host smart-a1884046-6481-4272-80cc-790c136567af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626068083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2626068083
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%