Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50115071

1

T1

6

T2

134396

T3

19371

full_word

43868031

1

T1

2

T2

956738

T3

16839

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	93982692	1			T1	8		T2	230069		T3	36210
auto[TlIntgErrCmd]	145	1			T53	2		T54	1		T55	11
auto[TlIntgErrData]	136	1			T53	4		T54	6		T55	2
auto[TlIntgErrBoth]	129	1			T53	4		T54	3		T55	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43925195

1

T1

1

T2

102085

T3

18186

auto[1]

50057907

1

T1

7

T2

127984

T3

18024

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22781613	1			T2	562000		T3	9084		T6	7049
auto[TlIntgErrNone]	partial	auto[1]	27333084	1			T1	6		T2	781961		T3	10287
auto[TlIntgErrNone]	full_word	auto[0]	21143396	1			T1	1		T2	458855		T3	9102
auto[TlIntgErrNone]	full_word	auto[1]	22724599	1			T1	1		T2	497883		T3	7737
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T53	2		T55	5		T56	4
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T54	1		T55	5		T56	9
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T55	1		T111	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T110	2		T114	1		T58	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T53	3		T54	2		T55	1
auto[TlIntgErrData]	partial	auto[1]	63	1			T53	1		T54	3		T55	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T114	1		T58	1		T57	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T54	1		T111	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T53	2		T54	1		T55	4
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T53	1		T54	2		T55	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T53	1		T56	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T55	1		T56	1		T111	1