Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	553999167	2429581	0	0
intr_enable_rd_A	553999167	3775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553999167	2429581	0	0
T2	574432	217516	0	0
T3	255968	0	0	0
T4	462890	0	0	0
T5	285431	0	0	0
T6	279189	0	0	0
T7	24019	0	0	0
T8	0	85015	0	0
T9	0	359236	0	0
T12	0	117785	0	0
T13	0	53496	0	0
T14	239511	0	0	0
T15	411778	0	0	0
T16	895314	0	0	0
T20	0	270471	0	0
T21	0	31838	0	0
T22	0	219503	0	0
T25	144030	0	0	0
T59	0	158578	0	0
T60	0	26191	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553999167	3775	0	0
T9	0	386	0	0
T12	0	68	0	0
T19	64600	0	0	0
T37	104039	0	0	0
T61	643538	12	0	0
T62	0	58	0	0
T63	0	5	0	0
T64	0	69	0	0
T65	0	28	0	0
T66	0	98	0	0
T67	0	25	0	0
T68	0	34	0	0
T69	234310	0	0	0
T70	183560	0	0	0
T71	39136	0	0	0
T72	17350	0	0	0
T73	186627	0	0	0
T74	215268	0	0	0
T75	50813	0	0	0