Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48867441

1

T1

89717

T2

21206

T3

23961

full_word

42800330

1

T1

84853

T2

17251

T3

19294

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91667391	1			T1	174570		T2	38457		T3	43255
auto[TlIntgErrCmd]	110	1			T49	3		T50	7		T51	6
auto[TlIntgErrData]	127	1			T49	5		T50	11		T51	10
auto[TlIntgErrBoth]	143	1			T49	2		T50	12		T51	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42824504

1

T1

83499

T2

19345

T3

21756

auto[1]

48843267

1

T1

91071

T2

19112

T3

21499

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22180564	1			T1	41804		T2	9690		T3	10956
auto[TlIntgErrNone]	partial	auto[1]	26686529	1			T1	47913		T2	11516		T3	13005
auto[TlIntgErrNone]	full_word	auto[0]	20643768	1			T1	41695		T2	9655		T3	10800
auto[TlIntgErrNone]	full_word	auto[1]	22156530	1			T1	43158		T2	7596		T3	8494
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T49	2		T50	1		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T49	1		T50	5		T51	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T95	1		T99	1		T100	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T50	1		T51	1		T101	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T49	2		T50	5		T51	2
auto[TlIntgErrData]	partial	auto[1]	65	1			T49	3		T50	5		T51	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T50	1		T102	1		T100	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T51	3		T98	1		T103	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T50	6		T51	5		T95	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T49	1		T50	5		T51	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T49	1		T104	1		T97	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T50	1		T51	1		T95	1