Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	528525324	2357416	0	0
intr_enable_rd_A	528525324	3446	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528525324	2357416	0	0
T6	913182	335616	0	0
T8	249240	0	0	0
T10	100602	0	0	0
T11	219713	0	0	0
T12	0	108939	0	0
T13	0	113372	0	0
T15	0	88240	0	0
T16	0	62854	0	0
T17	0	37059	0	0
T23	765551	0	0	0
T24	108703	0	0	0
T26	47281	0	0	0
T27	211317	0	0	0
T28	401290	0	0	0
T29	292472	0	0	0
T53	0	77884	0	0
T54	0	216432	0	0
T55	0	129976	0	0
T56	0	178057	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528525324	3446	0	0
T8	249240	0	0	0
T9	94479	0	0	0
T10	100602	17	0	0
T23	765551	0	0	0
T24	108703	0	0	0
T26	47281	0	0	0
T27	211317	0	0	0
T28	401290	0	0	0
T29	292472	0	0	0
T57	0	25	0	0
T58	0	20	0	0
T59	0	15	0	0
T60	0	12	0	0
T61	0	25	0	0
T62	0	41	0	0
T63	0	29	0	0
T64	0	58	0	0
T65	0	89	0	0
T66	27015	0	0	0