Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44276918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42334882

1

T1

982503

T2

25009

T3

8315

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	41175948	1			T1	925491		T2	17468		T3	5409
values[0x0]	21274750	1			T1	510136		T2	11701		T3	3556
values[0x1]	24161102	1			T1	560033		T2	12243		T3	3646

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34069364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52542436

1

T1

121131

T2

28294

T3

9458

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	277677	1			T7	7558		T6	1069		T14	463
valid_sources[0x01]	271039	1			T7	7715		T6	1121		T14	453
valid_sources[0x02]	244828	1			T7	7131		T6	1153		T14	490
valid_sources[0x03]	285299	1			T7	7837		T6	1125		T14	496
valid_sources[0x04]	254062	1			T7	7342		T6	1173		T14	476
valid_sources[0x05]	247656	1			T7	7492		T6	1193		T14	495
valid_sources[0x06]	247746	1			T7	7847		T6	1170		T14	502
valid_sources[0x07]	246393	1			T7	7512		T6	1171		T14	494
valid_sources[0x08]	244929	1			T7	7808		T6	1129		T14	474
valid_sources[0x09]	248919	1			T7	7499		T6	1171		T14	503
valid_sources[0x0a]	241111	1			T7	7456		T6	1126		T14	484
valid_sources[0x0b]	420790	1			T7	7094		T6	1171		T14	484
valid_sources[0x0c]	247281	1			T7	7623		T6	1133		T14	450
valid_sources[0x0d]	377258	1			T7	7468		T6	1159		T14	469
valid_sources[0x0e]	245031	1			T7	7491		T6	1183		T14	485
valid_sources[0x0f]	338054	1			T7	7611		T6	1111		T14	486
valid_sources[0x10]	243682	1			T7	7522		T6	1112		T14	489
valid_sources[0x11]	250024	1			T7	7936		T6	1066		T14	484
valid_sources[0x12]	244378	1			T7	7841		T6	1172		T14	444
valid_sources[0x13]	329767	1			T7	7836		T6	1135		T14	518
valid_sources[0x14]	244167	1			T7	7848		T6	1143		T14	470
valid_sources[0x15]	243728	1			T7	7480		T6	1133		T14	451
valid_sources[0x16]	246374	1			T7	7473		T6	1123		T14	518
valid_sources[0x17]	245987	1			T7	7518		T6	1081		T14	472
valid_sources[0x18]	247791	1			T7	7889		T6	1043		T14	496
valid_sources[0x19]	246042	1			T7	7865		T6	1158		T14	473
valid_sources[0x1a]	690325	1			T7	7778		T6	1148		T14	487
valid_sources[0x1b]	508743	1			T7	7559		T6	1143		T14	502
valid_sources[0x1c]	284692	1			T7	7112		T6	1165		T14	521
valid_sources[0x1d]	335180	1			T7	7451		T6	1192		T14	493
valid_sources[0x1e]	319841	1			T7	7765		T6	1153		T14	491
valid_sources[0x1f]	283637	1			T2	41412		T7	7300		T6	1139
valid_sources[0x20]	243434	1			T7	7531		T6	1213		T14	464
valid_sources[0x21]	244991	1			T7	7467		T6	1131		T14	490
valid_sources[0x22]	243877	1			T7	7817		T6	1120		T14	494
valid_sources[0x23]	246759	1			T7	8001		T6	1171		T14	535
valid_sources[0x24]	242119	1			T7	7595		T6	1170		T14	486
valid_sources[0x25]	403067	1			T3	12611		T7	7478		T6	1117
valid_sources[0x26]	245326	1			T7	8059		T6	1162		T14	460
valid_sources[0x27]	255365	1			T7	7736		T6	1167		T14	508
valid_sources[0x28]	243731	1			T7	7609		T6	1156		T14	491
valid_sources[0x29]	271490	1			T7	7732		T6	1066		T14	486
valid_sources[0x2a]	247101	1			T7	7681		T6	1124		T14	483
valid_sources[0x2b]	243699	1			T7	7685		T6	1168		T14	466
valid_sources[0x2c]	2174756	1			T7	7586		T6	1158		T14	495
valid_sources[0x2d]	260268	1			T7	7915		T6	1126		T14	479
valid_sources[0x2e]	251541	1			T7	7684		T6	1085		T14	456
valid_sources[0x2f]	249635	1			T7	7452		T6	1112		T14	468
valid_sources[0x30]	247112	1			T7	7977		T6	1186		T14	478
valid_sources[0x31]	243915	1			T7	7664		T6	1163		T14	477
valid_sources[0x32]	350798	1			T7	7355		T6	1102		T14	469
valid_sources[0x33]	244018	1			T7	7476		T6	1046		T14	523
valid_sources[0x34]	249753	1			T7	8114		T6	1143		T14	458
valid_sources[0x35]	246175	1			T7	7596		T6	1172		T14	490
valid_sources[0x36]	243950	1			T7	7552		T6	1114		T14	472
valid_sources[0x37]	242552	1			T7	7829		T6	1089		T14	487
valid_sources[0x38]	241725	1			T7	7553		T6	1157		T14	458
valid_sources[0x39]	243678	1			T7	7118		T6	1098		T14	527
valid_sources[0x3a]	250151	1			T7	7313		T6	1162		T14	448
valid_sources[0x3b]	621635	1			T7	7569		T6	1117		T14	512
valid_sources[0x3c]	256513	1			T7	7808		T6	1062		T14	453
valid_sources[0x3d]	246082	1			T7	7430		T6	1136		T14	487
valid_sources[0x3e]	245650	1			T7	7828		T6	1167		T14	514
valid_sources[0x3f]	506612	1			T7	7256		T6	1131		T14	526
valid_sources[0x40]	245421	1			T7	7390		T6	1137		T14	485
valid_sources[0x41]	243949	1			T7	7648		T6	1160		T14	510
valid_sources[0x42]	247009	1			T7	7444		T6	1190		T14	521
valid_sources[0x43]	248066	1			T7	7834		T6	1136		T14	516
valid_sources[0x44]	405173	1			T7	7453		T6	1060		T14	491
valid_sources[0x45]	245167	1			T7	7484		T6	1051		T14	500
valid_sources[0x46]	246715	1			T7	7783		T6	1198		T14	464
valid_sources[0x47]	349758	1			T7	7488		T6	1134		T14	475
valid_sources[0x48]	293639	1			T7	7841		T6	1122		T14	465
valid_sources[0x49]	240835	1			T7	7672		T6	1116		T14	475
valid_sources[0x4a]	244379	1			T7	7532		T6	1142		T14	449
valid_sources[0x4b]	247816	1			T7	7370		T6	1160		T14	436
valid_sources[0x4c]	243917	1			T7	7448		T6	1222		T14	451
valid_sources[0x4d]	244149	1			T7	7422		T6	1181		T14	483
valid_sources[0x4e]	244285	1			T7	7730		T6	1104		T14	477
valid_sources[0x4f]	244275	1			T7	7334		T6	1162		T14	485
valid_sources[0x50]	244541	1			T7	7848		T6	1121		T14	463
valid_sources[0x51]	243874	1			T7	7289		T6	1190		T14	457
valid_sources[0x52]	245584	1			T7	7865		T6	1140		T14	464
valid_sources[0x53]	1410254	1			T7	7446		T6	1149		T14	468
valid_sources[0x54]	314488	1			T7	7558		T6	1092		T14	487
valid_sources[0x55]	250334	1			T7	7672		T6	1152		T14	491
valid_sources[0x56]	242204	1			T7	7745		T6	1110		T14	515
valid_sources[0x57]	249328	1			T7	7333		T6	1118		T14	451
valid_sources[0x58]	275338	1			T7	7860		T6	1143		T14	515
valid_sources[0x59]	246681	1			T7	7644		T6	1058		T14	476
valid_sources[0x5a]	246878	1			T7	7239		T6	1089		T14	458
valid_sources[0x5b]	330459	1			T7	7673		T6	1114		T14	488
valid_sources[0x5c]	244651	1			T7	7792		T6	1147		T14	475
valid_sources[0x5d]	248078	1			T7	7660		T6	1111		T14	469
valid_sources[0x5e]	246441	1			T7	7458		T6	1154		T14	472
valid_sources[0x5f]	249569	1			T7	7491		T6	1161		T14	510
valid_sources[0x60]	244027	1			T7	7989		T6	1191		T14	483
valid_sources[0x61]	243121	1			T7	7485		T6	1201		T14	513
valid_sources[0x62]	244854	1			T7	6957		T6	1088		T14	473
valid_sources[0x63]	2096657	1			T7	7877		T6	1122		T14	491
valid_sources[0x64]	321813	1			T7	7230		T6	1128		T14	531
valid_sources[0x65]	261127	1			T7	7628		T5	15105		T6	1127
valid_sources[0x66]	312311	1			T7	7630		T6	1116		T14	453
valid_sources[0x67]	1578664	1			T7	7415		T6	1145		T14	498
valid_sources[0x68]	298420	1			T7	7913		T6	1083		T14	479
valid_sources[0x69]	291591	1			T7	7625		T6	1155		T14	471
valid_sources[0x6a]	479642	1			T7	7789		T6	1108		T14	480
valid_sources[0x6b]	752194	1			T7	7603		T6	1173		T14	489
valid_sources[0x6c]	248184	1			T7	7625		T6	1203		T14	472
valid_sources[0x6d]	241516	1			T7	7495		T6	1153		T14	494
valid_sources[0x6e]	244461	1			T7	7696		T6	1089		T14	461
valid_sources[0x6f]	245627	1			T7	7786		T6	1190		T14	509
valid_sources[0x70]	243830	1			T7	7821		T6	1150		T14	449
valid_sources[0x71]	244762	1			T7	7872		T6	1117		T14	470
valid_sources[0x72]	274302	1			T7	7773		T6	1129		T14	468
valid_sources[0x73]	244157	1			T7	7645		T6	1090		T14	500
valid_sources[0x74]	245195	1			T7	8025		T6	1089		T14	495
valid_sources[0x75]	270162	1			T7	7799		T6	1123		T14	478
valid_sources[0x76]	243914	1			T7	7473		T6	1080		T14	530
valid_sources[0x77]	278490	1			T7	7726		T6	1102		T14	466
valid_sources[0x78]	514630	1			T7	7478		T6	1158		T14	483
valid_sources[0x79]	241943	1			T7	7803		T6	1178		T14	450
valid_sources[0x7a]	242470	1			T7	7163		T6	1160		T14	483
valid_sources[0x7b]	374555	1			T7	7567		T6	1101		T14	488
valid_sources[0x7c]	249529	1			T7	7628		T6	1159		T14	458
valid_sources[0x7d]	243681	1			T7	7600		T6	1141		T14	505
valid_sources[0x7e]	281658	1			T7	8015		T6	1104		T14	480
valid_sources[0x7f]	1330165	1			T7	7679		T6	1150		T14	474
valid_sources[0x80]	332144	1			T7	7445		T6	1151		T14	504

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20392541

1

T1

462394

T2

8296

T3

2126

values[0x0]

all_enables

biggest_size

11799934

1

T1

281647

T2

8634

T3

3104

values[0x1]

all_enables

biggest_size

10142407

1

T1

238462

T2

8079

T3

3085