Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48212809

1

T1

101315

T2

16403

T3

4296

full_word

42591112

1

T1

982503

T2

25009

T3

8315

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90803521	1			T1	199566		T2	41412		T3	12611
auto[TlIntgErrCmd]	122	1			T56	3		T57	5		T58	3
auto[TlIntgErrData]	154	1			T56	3		T57	4		T58	3
auto[TlIntgErrBoth]	124	1			T56	4		T57	1		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42496637

1

T1

925491

T2

17468

T3

5409

auto[1]

48307284

1

T1

107016

T2

23944

T3

7202

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22003223	1			T1	463097		T2	9172		T3	3283
auto[TlIntgErrNone]	partial	auto[1]	26209213	1			T1	550060		T2	7231		T3	1013
auto[TlIntgErrNone]	full_word	auto[0]	20493226	1			T1	462394		T2	8296		T3	2126
auto[TlIntgErrNone]	full_word	auto[1]	22097859	1			T1	520109		T2	16713		T3	6189
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T56	2		T57	1		T122	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T56	1		T57	4		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T58	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T123	1		T127	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T57	4		T58	1		T122	1
auto[TlIntgErrData]	partial	auto[1]	71	1			T56	3		T58	2		T122	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T122	1		T127	2		T129	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T123	1		T130	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T56	2		T58	2		T123	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T56	1		T57	1		T58	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T131	1		T59	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T56	1		T127	1		T132	1