Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	558428515	2251100	0	0
intr_enable_rd_A	558428515	3137	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558428515	2251100	0	0
T11	124713	227548	0	0
T12	0	413600	0	0
T13	0	308221	0	0
T16	0	172147	0	0
T20	0	21282	0	0
T26	0	86802	0	0
T41	1205	0	0	0
T42	1017	0	0	0
T60	0	373501	0	0
T61	0	90441	0	0
T62	0	84244	0	0
T63	0	143946	0	0
T64	423787	0	0	0
T65	9188	0	0	0
T66	330087	0	0	0
T67	831959	0	0	0
T68	26740	0	0	0
T69	134796	0	0	0
T70	1223	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558428515	3137	0	0
T20	0	40	0	0
T43	113553	55	0	0
T71	0	154	0	0
T72	0	62	0	0
T73	0	31	0	0
T74	0	5	0	0
T75	0	23	0	0
T76	0	5	0	0
T77	0	6	0	0
T78	0	20	0	0
T79	16418	0	0	0
T80	968940	0	0	0
T81	932571	0	0	0
T82	364986	0	0	0
T83	1212	0	0	0
T84	96103	0	0	0
T85	119674	0	0	0
T86	324806	0	0	0
T87	119418	0	0	0