Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41660649	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39812090

1

T1

4

T2

66169

T3

20878

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38735537	1			T1	1		T2	75386		T3	22654
values[0x0]	20029818	1			T1	5		T2	34115		T3	10731
values[0x1]	22707384	1			T1	3		T2	40487		T3	12471

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32042386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49430353

1

T1

5

T2

85100

T3

26455

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	564502	1			T2	660		T7	376		T4	1549
valid_sources[0x01]	250389	1			T2	445		T7	390		T4	1669
valid_sources[0x02]	553860	1			T2	343		T7	364		T4	1544
valid_sources[0x03]	258260	1			T2	633		T7	396		T4	1590
valid_sources[0x04]	262947	1			T2	811		T7	386		T4	1622
valid_sources[0x05]	242392	1			T2	469		T7	365		T4	1662
valid_sources[0x06]	383871	1			T2	1017		T7	350		T4	1556
valid_sources[0x07]	254800	1			T2	626		T7	387		T4	1633
valid_sources[0x08]	300824	1			T2	501		T7	370		T4	1597
valid_sources[0x09]	278902	1			T2	1000		T7	373		T4	1539
valid_sources[0x0a]	252426	1			T2	870		T7	378		T4	1518
valid_sources[0x0b]	251501	1			T2	654		T7	388		T4	1657
valid_sources[0x0c]	301152	1			T2	394		T7	384		T4	1557
valid_sources[0x0d]	248692	1			T2	387		T7	392		T4	1487
valid_sources[0x0e]	273475	1			T2	639		T7	391		T4	1499
valid_sources[0x0f]	247756	1			T2	1074		T7	364		T4	1534
valid_sources[0x10]	437088	1			T2	601		T7	399		T4	1572
valid_sources[0x11]	290592	1			T2	436		T7	375		T4	1646
valid_sources[0x12]	272387	1			T2	754		T7	331		T4	1608
valid_sources[0x13]	240268	1			T2	792		T7	344		T4	1657
valid_sources[0x14]	262673	1			T2	651		T7	403		T4	1479
valid_sources[0x15]	246908	1			T2	433		T7	386		T4	1537
valid_sources[0x16]	246441	1			T2	400		T7	391		T4	1630
valid_sources[0x17]	285898	1			T2	682		T7	380		T4	1603
valid_sources[0x18]	302600	1			T2	406		T7	371		T4	1667
valid_sources[0x19]	249177	1			T2	1038		T7	399		T4	1670
valid_sources[0x1a]	243011	1			T2	803		T7	376		T4	1510
valid_sources[0x1b]	252064	1			T2	441		T7	383		T4	1575
valid_sources[0x1c]	246453	1			T2	730		T7	417		T4	1586
valid_sources[0x1d]	253356	1			T2	651		T7	376		T4	1488
valid_sources[0x1e]	1250148	1			T2	1044		T7	387		T4	1592
valid_sources[0x1f]	242367	1			T2	638		T7	335		T4	1542
valid_sources[0x20]	240996	1			T2	535		T7	406		T4	1669
valid_sources[0x21]	240896	1			T2	441		T7	360		T4	1713
valid_sources[0x22]	249573	1			T2	397		T7	407		T4	1625
valid_sources[0x23]	363809	1			T2	509		T7	378		T4	1635
valid_sources[0x24]	252252	1			T2	572		T7	359		T4	1579
valid_sources[0x25]	255070	1			T2	525		T7	386		T4	1565
valid_sources[0x26]	699460	1			T2	769		T7	377		T4	1794
valid_sources[0x27]	280061	1			T2	683		T7	362		T4	1701
valid_sources[0x28]	249731	1			T2	648		T7	365		T4	1684
valid_sources[0x29]	238178	1			T2	586		T7	374		T4	1550
valid_sources[0x2a]	325883	1			T2	882		T7	374		T4	1621
valid_sources[0x2b]	312513	1			T2	339		T7	384		T4	1772
valid_sources[0x2c]	310377	1			T2	659		T7	392		T4	1627
valid_sources[0x2d]	781188	1			T2	661		T7	374		T4	1541
valid_sources[0x2e]	308642	1			T2	1063		T7	354		T4	1654
valid_sources[0x2f]	258323	1			T2	447		T7	387		T4	1609
valid_sources[0x30]	244482	1			T2	755		T7	388		T4	1534
valid_sources[0x31]	457376	1			T2	561		T7	435		T4	1674
valid_sources[0x32]	241129	1			T2	366		T7	407		T4	1629
valid_sources[0x33]	248354	1			T2	670		T7	381		T4	1644
valid_sources[0x34]	310811	1			T2	844		T7	387		T4	1511
valid_sources[0x35]	245062	1			T2	524		T7	400		T4	1756
valid_sources[0x36]	256797	1			T2	417		T7	392		T4	1727
valid_sources[0x37]	243671	1			T2	346		T7	402		T4	1639
valid_sources[0x38]	285156	1			T2	485		T7	397		T4	1737
valid_sources[0x39]	263934	1			T2	366		T7	438		T4	1680
valid_sources[0x3a]	268118	1			T2	328		T7	375		T4	1674
valid_sources[0x3b]	254455	1			T2	538		T7	409		T4	1628
valid_sources[0x3c]	538162	1			T2	323		T7	386		T4	1627
valid_sources[0x3d]	243384	1			T2	401		T7	395		T4	1505
valid_sources[0x3e]	242698	1			T2	660		T7	380		T4	1623
valid_sources[0x3f]	316182	1			T2	541		T7	401		T4	1608
valid_sources[0x40]	253899	1			T2	476		T7	356		T4	1523
valid_sources[0x41]	256226	1			T2	708		T7	401		T4	1542
valid_sources[0x42]	253939	1			T2	921		T7	381		T4	1576
valid_sources[0x43]	253083	1			T2	668		T7	362		T4	1603
valid_sources[0x44]	249714	1			T2	813		T7	402		T4	1628
valid_sources[0x45]	246379	1			T2	945		T7	364		T4	1567
valid_sources[0x46]	250407	1			T2	726		T7	407		T4	1493
valid_sources[0x47]	950673	1			T2	361		T7	350		T4	1526
valid_sources[0x48]	250267	1			T2	347		T7	413		T4	1686
valid_sources[0x49]	249913	1			T2	774		T7	365		T4	1535
valid_sources[0x4a]	242732	1			T2	466		T7	375		T4	1630
valid_sources[0x4b]	236875	1			T2	885		T7	362		T4	1574
valid_sources[0x4c]	237184	1			T2	492		T7	366		T4	1681
valid_sources[0x4d]	249292	1			T2	343		T7	420		T4	1705
valid_sources[0x4e]	416504	1			T2	496		T7	364		T4	1612
valid_sources[0x4f]	252782	1			T2	298		T7	363		T4	1617
valid_sources[0x50]	241744	1			T2	424		T7	390		T4	1519
valid_sources[0x51]	313619	1			T2	343		T7	336		T4	1512
valid_sources[0x52]	243814	1			T2	587		T7	425		T4	1666
valid_sources[0x53]	250688	1			T2	758		T7	377		T4	1682
valid_sources[0x54]	519188	1			T2	770		T7	387		T4	1572
valid_sources[0x55]	278071	1			T2	533		T7	386		T4	1582
valid_sources[0x56]	247771	1			T2	630		T7	365		T4	1538
valid_sources[0x57]	239682	1			T2	453		T7	372		T4	1813
valid_sources[0x58]	239978	1			T2	557		T7	391		T4	1617
valid_sources[0x59]	259010	1			T2	626		T7	400		T4	1549
valid_sources[0x5a]	243646	1			T2	445		T7	382		T4	1546
valid_sources[0x5b]	300003	1			T2	426		T7	404		T4	1459
valid_sources[0x5c]	362416	1			T2	927		T7	382		T4	1725
valid_sources[0x5d]	482693	1			T2	719		T7	398		T4	1608
valid_sources[0x5e]	253216	1			T2	491		T7	385		T4	1632
valid_sources[0x5f]	250627	1			T2	339		T7	366		T4	1638
valid_sources[0x60]	241187	1			T2	622		T7	399		T4	1634
valid_sources[0x61]	334406	1			T2	471		T7	388		T4	1764
valid_sources[0x62]	569817	1			T2	544		T7	338		T4	1576
valid_sources[0x63]	250213	1			T2	667		T7	395		T4	1582
valid_sources[0x64]	406520	1			T2	798		T7	380		T4	1699
valid_sources[0x65]	266337	1			T2	823		T7	365		T4	1723
valid_sources[0x66]	260457	1			T2	366		T7	391		T4	1699
valid_sources[0x67]	249211	1			T2	417		T7	367		T4	1589
valid_sources[0x68]	245918	1			T2	543		T7	380		T4	1571
valid_sources[0x69]	252899	1			T2	619		T7	361		T4	1782
valid_sources[0x6a]	236445	1			T2	874		T7	355		T4	1569
valid_sources[0x6b]	248876	1			T2	625		T7	406		T4	1681
valid_sources[0x6c]	672126	1			T2	431		T7	391		T4	1656
valid_sources[0x6d]	253464	1			T2	656		T7	374		T4	1537
valid_sources[0x6e]	246094	1			T2	416		T7	391		T4	1618
valid_sources[0x6f]	241754	1			T2	384		T7	416		T4	1621
valid_sources[0x70]	2411110	1			T2	507		T7	392		T4	1584
valid_sources[0x71]	298936	1			T2	719		T7	367		T4	1547
valid_sources[0x72]	247189	1			T2	479		T7	379		T4	1691
valid_sources[0x73]	273182	1			T2	531		T7	428		T4	1645
valid_sources[0x74]	279722	1			T2	352		T7	388		T4	1642
valid_sources[0x75]	239494	1			T2	512		T7	425		T4	1534
valid_sources[0x76]	237805	1			T2	553		T7	402		T4	1659
valid_sources[0x77]	254003	1			T2	670		T7	373		T4	1581
valid_sources[0x78]	252235	1			T2	1140		T7	415		T4	1580
valid_sources[0x79]	241222	1			T2	403		T7	393		T4	1666
valid_sources[0x7a]	244246	1			T2	527		T7	404		T4	1637
valid_sources[0x7b]	244975	1			T2	455		T7	360		T4	1591
valid_sources[0x7c]	245163	1			T2	784		T7	365		T4	1640
valid_sources[0x7d]	510752	1			T2	451		T7	401		T4	1664
valid_sources[0x7e]	383582	1			T2	486		T7	374		T4	1569
valid_sources[0x7f]	257564	1			T2	963		T7	429		T4	1634
valid_sources[0x80]	239370	1			T2	240		T7	379		T4	1567

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19159661

1

T1

1

T2

37631

T3

11243

values[0x0]

all_enables

biggest_size

11110985

1

T1

3

T2

15723

T3

5254

values[0x1]

all_enables

biggest_size

9541444

1

T2

12815

T3

4381

T7

14691