Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45240150

1

T1

5

T2

83819

T3

24978

full_word

40044854

1

T1

4

T2

66169

T3

20878

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85284594	1			T1	9		T2	149988		T3	45856
auto[TlIntgErrCmd]	130	1			T69	9		T70	8		T71	5
auto[TlIntgErrData]	125	1			T69	8		T70	13		T71	3
auto[TlIntgErrBoth]	155	1			T69	13		T70	9		T71	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39939707

1

T1

1

T2

75386

T3

22654

auto[1]

45345297

1

T1

8

T2

74602

T3

23202

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20688158	1			T2	37755		T3	11411		T7	24857
auto[TlIntgErrNone]	partial	auto[1]	24551626	1			T1	5		T2	46064		T3	13567
auto[TlIntgErrNone]	full_word	auto[0]	19251359	1			T1	1		T2	37631		T3	11243
auto[TlIntgErrNone]	full_word	auto[1]	20793451	1			T1	3		T2	28538		T3	9635
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T69	4		T70	4		T71	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T69	5		T70	4		T71	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T133	1		T134	1
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T71	1		T135	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T69	3		T70	6		T131	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T69	5		T70	6		T71	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T70	1		T71	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T129	2		T136	1		T134	2
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T69	4		T70	4		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	94	1			T69	9		T70	5		T71	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T131	1		T137	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T132	1		T128	1		T134	2