Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	453700329	2049898	0	0
intr_enable_rd_A	453700329	3248	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453700329	2049898	0	0
T11	278572	34603	0	0
T12	0	141004	0	0
T13	0	47952	0	0
T14	0	42920	0	0
T15	0	273087	0	0
T17	0	88635	0	0
T18	0	41638	0	0
T25	0	118469	0	0
T26	79472	0	0	0
T72	0	174741	0	0
T73	0	248232	0	0
T74	1093	0	0	0
T75	138871	0	0	0
T76	151109	0	0	0
T77	1298	0	0	0
T78	223720	0	0	0
T79	752290	0	0	0
T80	76359	0	0	0
T81	950056	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453700329	3248	0	0
T11	278572	82	0	0
T17	0	75	0	0
T18	0	24	0	0
T74	1093	0	0	0
T75	138871	0	0	0
T76	151109	0	0	0
T82	678487	34	0	0
T83	0	11	0	0
T84	0	88	0	0
T85	0	37	0	0
T86	0	43	0	0
T87	0	7	0	0
T88	0	44	0	0
T89	162448	0	0	0
T90	579117	0	0	0
T91	58064	0	0	0
T92	81239	0	0	0
T93	133172	0	0	0