Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

49197646

1

T1

61828

T2

11328

T3

24561

full_word

43591120

1

T1

51286

T2

34011

T3

19645

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92788336	1			T1	113114		T2	45339		T3	44206
auto[TlIntgErrCmd]	149	1			T60	9		T61	3		T62	3
auto[TlIntgErrData]	131	1			T60	9		T61	3		T62	6
auto[TlIntgErrBoth]	150	1			T60	12		T61	4		T62	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43615186

1

T1

54193

T2

14181

T3

22176

auto[1]

49173580

1

T1

58921

T2

31158

T3

22030

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22527260	1			T1	27214		T2	8559		T3	11175
auto[TlIntgErrNone]	partial	auto[1]	26669994	1			T1	34614		T2	2769		T3	13386
auto[TlIntgErrNone]	full_word	auto[0]	21087733	1			T1	26979		T2	5622		T3	11001
auto[TlIntgErrNone]	full_word	auto[1]	22503349	1			T1	24307		T2	28389		T3	8644
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T60	4		T61	2		T132	3
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T60	4		T61	1		T62	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T60	1		T135	1		T133	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T132	1		T136	2		T134	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T60	4		T61	1		T62	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T60	4		T61	1		T62	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T60	1		T61	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T137	1		T138	1		T67	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T60	5		T62	3		T132	3
auto[TlIntgErrBoth]	partial	auto[1]	84	1			T60	5		T61	4		T62	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T60	1		T132	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	13	1			T60	1		T132	1		T65	1