Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	513889800	1909611	0	0
intr_enable_rd_A	513889800	3423	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513889800	1909611	0	0
T9	947401	187187	0	0
T10	734296	137678	0	0
T11	0	103352	0	0
T18	0	141476	0	0
T19	0	15537	0	0
T33	0	258834	0	0
T68	0	69741	0	0
T69	0	230139	0	0
T70	0	182087	0	0
T71	0	139507	0	0
T72	115359	0	0	0
T73	193041	0	0	0
T74	92370	0	0	0
T75	644720	0	0	0
T76	89817	0	0	0
T77	837469	0	0	0
T78	922225	0	0	0
T79	249849	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513889800	3423	0	0
T5	135717	0	0	0
T7	325045	1	0	0
T8	954533	0	0	0
T18	0	200	0	0
T38	153614	0	0	0
T40	513788	0	0	0
T64	0	26	0	0
T78	0	2	0	0
T80	0	40	0	0
T81	0	25	0	0
T82	0	37	0	0
T83	0	16	0	0
T84	0	13	0	0
T85	0	31	0	0
T86	6010	0	0	0
T87	99184	0	0	0
T88	514642	0	0	0
T89	129746	0	0	0
T90	88121	0	0	0