Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48679138

1

T1

5243

T2

14

T3

592

full_word

42821066

1

T1

8143

T2

2

T3

584

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91499784	1			T1	13386		T2	16		T3	1176
auto[TlIntgErrCmd]	131	1			T60	4		T61	11		T62	5
auto[TlIntgErrData]	157	1			T60	8		T61	8		T62	2
auto[TlIntgErrBoth]	132	1			T60	8		T61	11		T62	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42879952

1

T1

6448

T2

1

T3

589

auto[1]

48620252

1

T1

6938

T2

15

T3

587

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22210257	1			T1	3983		T3	303		T4	9961
auto[TlIntgErrNone]	partial	auto[1]	26468498	1			T1	1260		T2	14		T3	289
auto[TlIntgErrNone]	full_word	auto[0]	20669494	1			T1	2465		T2	1		T3	286
auto[TlIntgErrNone]	full_word	auto[1]	22151535	1			T1	5678		T2	1		T3	298
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T60	2		T61	6		T62	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T60	1		T61	4		T62	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T127	1		T126	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T60	1		T61	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T60	4		T61	4		T62	1
auto[TlIntgErrData]	partial	auto[1]	67	1			T60	4		T61	2		T62	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T61	1		T128	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T61	1		T123	2		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T60	2		T61	4		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T60	6		T61	5		T62	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T128	1		T130	1		T126	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T61	2		T129	1		T131	1