Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	485609461	2145280	0	0
intr_enable_rd_A	485609461	3127	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485609461	2145280	0	0
T8	689982	106895	0	0
T9	104330	199706	0	0
T10	0	12501	0	0
T14	0	111958	0	0
T21	0	100127	0	0
T22	0	236185	0	0
T23	0	7490	0	0
T31	0	146311	0	0
T64	0	383886	0	0
T65	0	31162	0	0
T66	110050	0	0	0
T67	532196	0	0	0
T68	459414	0	0	0
T69	762519	0	0	0
T70	110195	0	0	0
T71	955	0	0	0
T72	329801	0	0	0
T73	294712	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485609461	3127	0	0
T8	0	96	0	0
T10	0	39	0	0
T14	0	120	0	0
T40	126976	13	0	0
T41	104557	0	0	0
T42	120363	0	0	0
T47	770	0	0	0
T65	0	87	0	0
T74	0	35	0	0
T75	0	38	0	0
T76	0	10	0	0
T77	0	22	0	0
T78	0	22	0	0
T79	324932	0	0	0
T80	247404	0	0	0
T81	2102	0	0	0
T82	5513	0	0	0
T83	32360	0	0	0
T84	64728	0	0	0