Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42318702 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 40247336 1 T1 54148 T2 3831 T3 21859



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 39333539 1 T1 61229 T2 3757 T3 23091
values[0x0] 20278474 1 T1 27777 T2 1608 T3 9708
values[0x1] 22954025 1 T1 32807 T2 1845 T3 11251



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 32615457 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 49950581 1 T1 69569 T2 4616 T3 27105



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 269338 1 T1 440 T3 152 T5 361
valid_sources[0x01] 266515 1 T1 488 T3 166 T5 393
valid_sources[0x02] 265792 1 T1 459 T3 158 T5 366
valid_sources[0x03] 309227 1 T1 485 T3 205 T5 343
valid_sources[0x04] 267455 1 T1 478 T3 158 T5 276
valid_sources[0x05] 435844 1 T1 468 T3 182 T5 351
valid_sources[0x06] 267884 1 T1 472 T3 154 T5 378
valid_sources[0x07] 363358 1 T1 481 T3 171 T5 308
valid_sources[0x08] 267729 1 T1 451 T3 181 T5 455
valid_sources[0x09] 303114 1 T1 482 T3 159 T5 322
valid_sources[0x0a] 269809 1 T1 456 T3 177 T5 275
valid_sources[0x0b] 266817 1 T1 461 T3 167 T5 402
valid_sources[0x0c] 270157 1 T1 519 T3 164 T5 265
valid_sources[0x0d] 264865 1 T1 470 T3 171 T5 401
valid_sources[0x0e] 268097 1 T1 447 T3 194 T5 392
valid_sources[0x0f] 404722 1 T1 471 T3 183 T5 495
valid_sources[0x10] 267498 1 T1 475 T3 194 T5 349
valid_sources[0x11] 289358 1 T1 473 T3 165 T5 371
valid_sources[0x12] 267429 1 T1 533 T3 180 T5 290
valid_sources[0x13] 268430 1 T1 466 T3 172 T5 352
valid_sources[0x14] 267059 1 T1 481 T3 174 T5 422
valid_sources[0x15] 266183 1 T1 485 T3 189 T5 403
valid_sources[0x16] 267495 1 T1 466 T3 173 T5 430
valid_sources[0x17] 267519 1 T1 458 T3 167 T5 385
valid_sources[0x18] 266060 1 T1 488 T3 168 T5 376
valid_sources[0x19] 266683 1 T1 464 T3 157 T5 404
valid_sources[0x1a] 382092 1 T1 452 T3 151 T5 230
valid_sources[0x1b] 267832 1 T1 503 T3 133 T5 321
valid_sources[0x1c] 292026 1 T1 498 T3 188 T5 379
valid_sources[0x1d] 265911 1 T1 448 T3 169 T5 367
valid_sources[0x1e] 1799026 1 T1 412 T3 172 T5 351
valid_sources[0x1f] 268007 1 T1 459 T3 180 T5 372
valid_sources[0x20] 347358 1 T1 498 T3 166 T5 457
valid_sources[0x21] 332746 1 T1 491 T3 187 T5 392
valid_sources[0x22] 267969 1 T1 480 T3 186 T5 321
valid_sources[0x23] 267097 1 T1 511 T3 169 T5 405
valid_sources[0x24] 2509920 1 T1 456 T3 155 T5 299
valid_sources[0x25] 269317 1 T1 493 T3 162 T5 371
valid_sources[0x26] 267366 1 T1 451 T3 170 T5 358
valid_sources[0x27] 265829 1 T1 437 T3 154 T5 360
valid_sources[0x28] 352378 1 T1 510 T3 184 T5 472
valid_sources[0x29] 266825 1 T1 508 T3 173 T5 345
valid_sources[0x2a] 333646 1 T1 460 T3 177 T5 299
valid_sources[0x2b] 268607 1 T1 493 T3 162 T5 365
valid_sources[0x2c] 266641 1 T1 434 T3 166 T5 406
valid_sources[0x2d] 268314 1 T1 445 T3 175 T5 376
valid_sources[0x2e] 702197 1 T1 469 T3 191 T5 377
valid_sources[0x2f] 266174 1 T1 509 T3 190 T5 314
valid_sources[0x30] 352808 1 T1 421 T3 173 T5 448
valid_sources[0x31] 269205 1 T1 470 T3 175 T5 285
valid_sources[0x32] 267503 1 T1 461 T3 172 T5 309
valid_sources[0x33] 267987 1 T1 450 T3 174 T5 385
valid_sources[0x34] 268179 1 T1 460 T3 162 T5 388
valid_sources[0x35] 267773 1 T1 474 T3 143 T5 332
valid_sources[0x36] 267118 1 T1 511 T3 170 T5 362
valid_sources[0x37] 283343 1 T1 487 T3 166 T5 352
valid_sources[0x38] 265937 1 T1 474 T3 185 T5 423
valid_sources[0x39] 264460 1 T1 438 T3 178 T5 387
valid_sources[0x3a] 265923 1 T1 487 T3 197 T5 363
valid_sources[0x3b] 370088 1 T1 405 T3 181 T4 102070
valid_sources[0x3c] 267318 1 T1 455 T3 166 T5 342
valid_sources[0x3d] 269534 1 T1 457 T3 169 T5 391
valid_sources[0x3e] 268240 1 T1 470 T3 171 T5 384
valid_sources[0x3f] 266482 1 T1 500 T3 191 T5 306
valid_sources[0x40] 268535 1 T1 421 T3 194 T5 340
valid_sources[0x41] 296232 1 T1 482 T3 153 T5 348
valid_sources[0x42] 264909 1 T1 442 T3 162 T5 326
valid_sources[0x43] 265759 1 T1 508 T3 169 T5 394
valid_sources[0x44] 300668 1 T1 468 T3 190 T5 441
valid_sources[0x45] 268323 1 T1 442 T3 179 T5 427
valid_sources[0x46] 299127 1 T1 475 T3 201 T5 440
valid_sources[0x47] 265454 1 T1 508 T3 148 T5 268
valid_sources[0x48] 276368 1 T1 532 T3 194 T5 350
valid_sources[0x49] 266413 1 T1 526 T3 166 T5 411
valid_sources[0x4a] 267936 1 T1 507 T3 184 T5 332
valid_sources[0x4b] 427592 1 T1 442 T3 169 T5 362
valid_sources[0x4c] 268211 1 T1 534 T3 183 T5 300
valid_sources[0x4d] 266076 1 T1 499 T3 191 T5 392
valid_sources[0x4e] 269031 1 T1 501 T3 194 T5 376
valid_sources[0x4f] 269703 1 T1 450 T3 186 T5 334
valid_sources[0x50] 266833 1 T1 526 T3 150 T5 427
valid_sources[0x51] 477858 1 T1 427 T3 144 T5 447
valid_sources[0x52] 267526 1 T1 435 T3 155 T5 332
valid_sources[0x53] 265358 1 T1 475 T3 148 T5 324
valid_sources[0x54] 282399 1 T1 440 T3 184 T5 308
valid_sources[0x55] 460008 1 T1 508 T3 144 T5 306
valid_sources[0x56] 264337 1 T1 421 T3 202 T5 308
valid_sources[0x57] 266187 1 T1 429 T3 186 T5 384
valid_sources[0x58] 265382 1 T1 472 T3 172 T5 344
valid_sources[0x59] 263166 1 T1 471 T3 173 T5 395
valid_sources[0x5a] 269249 1 T1 455 T3 170 T5 435
valid_sources[0x5b] 276959 1 T1 458 T3 177 T5 302
valid_sources[0x5c] 267540 1 T1 470 T3 172 T5 386
valid_sources[0x5d] 266832 1 T1 508 T3 169 T5 388
valid_sources[0x5e] 321257 1 T1 488 T3 147 T5 400
valid_sources[0x5f] 265907 1 T1 524 T3 190 T5 343
valid_sources[0x60] 360168 1 T1 463 T3 192 T5 341
valid_sources[0x61] 303274 1 T1 455 T3 174 T5 364
valid_sources[0x62] 270909 1 T1 494 T3 197 T5 341
valid_sources[0x63] 266344 1 T1 495 T3 168 T5 427
valid_sources[0x64] 266641 1 T1 549 T3 161 T5 376
valid_sources[0x65] 268264 1 T1 414 T3 157 T5 415
valid_sources[0x66] 271904 1 T1 441 T3 177 T5 445
valid_sources[0x67] 348414 1 T1 445 T3 155 T5 358
valid_sources[0x68] 343324 1 T1 434 T3 179 T5 361
valid_sources[0x69] 269464 1 T1 471 T3 172 T5 320
valid_sources[0x6a] 330145 1 T1 516 T3 153 T5 303
valid_sources[0x6b] 1463198 1 T1 472 T3 183 T5 312
valid_sources[0x6c] 269245 1 T1 491 T3 162 T5 458
valid_sources[0x6d] 263635 1 T1 458 T3 191 T5 361
valid_sources[0x6e] 271422 1 T1 448 T3 195 T5 410
valid_sources[0x6f] 314027 1 T1 437 T3 171 T5 327
valid_sources[0x70] 263336 1 T1 477 T3 158 T5 373
valid_sources[0x71] 268970 1 T1 461 T3 158 T5 374
valid_sources[0x72] 265489 1 T1 501 T3 182 T5 378
valid_sources[0x73] 265400 1 T1 451 T3 162 T5 377
valid_sources[0x74] 265719 1 T1 512 T3 148 T5 425
valid_sources[0x75] 398559 1 T1 443 T3 160 T5 394
valid_sources[0x76] 265049 1 T1 483 T3 187 T5 429
valid_sources[0x77] 264836 1 T1 449 T3 185 T5 393
valid_sources[0x78] 265438 1 T1 462 T3 206 T5 353
valid_sources[0x79] 266152 1 T1 464 T3 164 T5 443
valid_sources[0x7a] 566881 1 T1 458 T3 171 T5 354
valid_sources[0x7b] 267318 1 T1 468 T3 167 T5 417
valid_sources[0x7c] 283233 1 T1 500 T3 191 T5 298
valid_sources[0x7d] 272473 1 T1 453 T3 192 T5 318
valid_sources[0x7e] 264820 1 T1 490 T3 177 T5 395
valid_sources[0x7f] 264584 1 T1 485 T3 181 T5 339
valid_sources[0x80] 263056 1 T1 497 T3 172 T5 385



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 19461715 1 T1 30636 T2 1860 T3 11381
values[0x0] all_enables biggest_size 11188321 1 T1 12945 T2 1015 T3 5421
values[0x1] all_enables biggest_size 9597300 1 T1 10567 T2 956 T3 5057

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%