Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44734831

1

T1

67665

T2

3379

T3

22191

full_word

40404331

1

T1

54148

T2

3831

T3

21859

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85138812	1			T1	121813		T2	7210		T3	44050
auto[TlIntgErrCmd]	114	1			T68	8		T69	1		T128	5
auto[TlIntgErrData]	113	1			T67	6		T68	9		T69	2
auto[TlIntgErrBoth]	123	1			T67	4		T68	13		T69	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40146431

1

T1

61229

T2

3757

T3

23091

auto[1]

44992731

1

T1

60584

T2

3453

T3

20959

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20622750	1			T1	30593		T2	1897		T3	11710
auto[TlIntgErrNone]	partial	auto[1]	24111763	1			T1	37072		T2	1482		T3	10481
auto[TlIntgErrNone]	full_word	auto[0]	19523535	1			T1	30636		T2	1860		T3	11381
auto[TlIntgErrNone]	full_word	auto[1]	20880764	1			T1	23512		T2	1971		T3	10478
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T68	5		T69	1		T128	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T68	3		T128	3		T129	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T129	2		T130	1		T70	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T130	2		T133	1		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T67	4		T68	2		T69	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T67	1		T68	6		T69	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T67	1		T129	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T68	1		T134	1		T135	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T67	1		T68	2		T69	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T67	3		T68	9		T69	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T68	1		T134	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T68	1		T128	1		T129	1