Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	474842485	1396354	0	0
intr_enable_rd_A	474842485	2977	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474842485	1396354	0	0
T5	110629	13047	0	0
T6	565635	88123	0	0
T7	30877	0	0	0
T8	0	155956	0	0
T12	53369	0	0	0
T13	213536	0	0	0
T14	859454	0	0	0
T18	379824	0	0	0
T19	0	51341	0	0
T20	0	214970	0	0
T21	11192	0	0	0
T24	0	262961	0	0
T40	0	65345	0	0
T50	888	0	0	0
T71	0	88241	0	0
T72	0	57459	0	0
T73	0	125534	0	0
T74	72418	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474842485	2977	0	0
T5	110629	28	0	0
T6	565635	67	0	0
T7	30877	0	0	0
T8	0	99	0	0
T12	53369	0	0	0
T13	213536	0	0	0
T14	859454	0	0	0
T18	379824	59	0	0
T21	11192	0	0	0
T50	888	0	0	0
T71	0	141	0	0
T72	0	59	0	0
T74	72418	0	0	0
T75	0	122	0	0
T76	0	53	0	0
T77	0	33	0	0
T78	0	35	0	0