Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45921730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

43750987

1

T1

46289

T2

50490

T3

3540

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42699500	1			T1	52372		T2	52637		T3	3981
values[0x0]	21970993	1			T1	23831		T2	26303		T3	1761
values[0x1]	25002224	1			T1	27984		T2	30308		T3	2154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35286079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54386638

1

T1

59407

T2

63601

T3

4499

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	258506	1			T1	413		T2	427		T4	37
valid_sources[0x01]	260168	1			T1	381		T2	405		T4	26
valid_sources[0x02]	259248	1			T1	398		T2	443		T4	42
valid_sources[0x03]	611527	1			T1	386		T2	450		T4	32
valid_sources[0x04]	265829	1			T1	422		T2	378		T4	31
valid_sources[0x05]	269164	1			T1	387		T2	379		T4	34
valid_sources[0x06]	261707	1			T1	405		T2	390		T4	49
valid_sources[0x07]	254407	1			T1	442		T2	404		T4	43
valid_sources[0x08]	1659320	1			T1	409		T2	413		T4	50
valid_sources[0x09]	290694	1			T1	439		T2	468		T4	36
valid_sources[0x0a]	320335	1			T1	377		T2	410		T4	38
valid_sources[0x0b]	352853	1			T1	390		T2	403		T4	26
valid_sources[0x0c]	300506	1			T1	349		T2	438		T4	35
valid_sources[0x0d]	262792	1			T1	448		T2	413		T3	7895
valid_sources[0x0e]	261735	1			T1	453		T2	428		T4	31
valid_sources[0x0f]	345099	1			T1	409		T2	447		T4	33
valid_sources[0x10]	269210	1			T1	375		T2	449		T4	37
valid_sources[0x11]	266661	1			T1	436		T2	451		T4	33
valid_sources[0x12]	255446	1			T1	430		T2	447		T4	54
valid_sources[0x13]	262670	1			T1	359		T2	486		T4	46
valid_sources[0x14]	267506	1			T1	455		T2	458		T4	45
valid_sources[0x15]	459841	1			T1	350		T2	401		T4	33
valid_sources[0x16]	455983	1			T1	410		T2	413		T4	36
valid_sources[0x17]	258280	1			T1	398		T2	364		T4	43
valid_sources[0x18]	265027	1			T1	377		T2	455		T4	25
valid_sources[0x19]	292275	1			T1	393		T2	420		T4	38
valid_sources[0x1a]	259772	1			T1	489		T2	394		T4	24
valid_sources[0x1b]	257389	1			T1	484		T2	438		T4	38
valid_sources[0x1c]	421625	1			T1	369		T2	419		T4	31
valid_sources[0x1d]	257645	1			T1	360		T2	392		T4	31
valid_sources[0x1e]	254959	1			T1	383		T2	405		T4	27
valid_sources[0x1f]	286180	1			T1	446		T2	422		T4	35
valid_sources[0x20]	282256	1			T1	427		T2	422		T4	39
valid_sources[0x21]	265954	1			T1	327		T2	408		T4	36
valid_sources[0x22]	266401	1			T1	425		T2	419		T4	43
valid_sources[0x23]	258015	1			T1	422		T2	393		T4	34
valid_sources[0x24]	258688	1			T1	409		T2	428		T4	49
valid_sources[0x25]	260219	1			T1	408		T2	446		T4	36
valid_sources[0x26]	263915	1			T1	402		T2	379		T4	57
valid_sources[0x27]	260821	1			T1	396		T2	476		T4	44
valid_sources[0x28]	266739	1			T1	406		T2	418		T4	39
valid_sources[0x29]	322004	1			T1	360		T2	485		T4	31
valid_sources[0x2a]	256979	1			T1	411		T2	387		T4	36
valid_sources[0x2b]	258186	1			T1	370		T2	485		T4	38
valid_sources[0x2c]	264077	1			T1	410		T2	415		T4	27
valid_sources[0x2d]	297486	1			T1	348		T2	421		T4	45
valid_sources[0x2e]	253033	1			T1	444		T2	407		T4	39
valid_sources[0x2f]	255516	1			T1	424		T2	433		T4	36
valid_sources[0x30]	487848	1			T1	431		T2	429		T4	40
valid_sources[0x31]	262535	1			T1	414		T2	429		T4	44
valid_sources[0x32]	299201	1			T1	409		T2	430		T4	44
valid_sources[0x33]	293415	1			T1	407		T2	469		T4	28
valid_sources[0x34]	253315	1			T1	352		T2	436		T4	41
valid_sources[0x35]	263313	1			T1	461		T2	449		T4	36
valid_sources[0x36]	938064	1			T1	380		T2	402		T4	30
valid_sources[0x37]	399743	1			T1	411		T2	416		T4	27
valid_sources[0x38]	264167	1			T1	398		T2	367		T4	30
valid_sources[0x39]	259275	1			T1	380		T2	397		T4	38
valid_sources[0x3a]	255737	1			T1	438		T2	436		T4	57
valid_sources[0x3b]	1122937	1			T1	443		T2	379		T4	36
valid_sources[0x3c]	258425	1			T1	426		T2	413		T4	37
valid_sources[0x3d]	263593	1			T1	368		T2	421		T4	25
valid_sources[0x3e]	315734	1			T1	371		T2	394		T4	34
valid_sources[0x3f]	261786	1			T1	420		T2	410		T4	37
valid_sources[0x40]	261290	1			T1	385		T2	387		T4	37
valid_sources[0x41]	264025	1			T1	405		T2	386		T4	32
valid_sources[0x42]	262333	1			T1	413		T2	394		T4	21
valid_sources[0x43]	263303	1			T1	391		T2	424		T4	23
valid_sources[0x44]	252551	1			T1	387		T2	430		T4	30
valid_sources[0x45]	264969	1			T1	421		T2	479		T4	32
valid_sources[0x46]	250644	1			T1	350		T2	406		T4	35
valid_sources[0x47]	262625	1			T1	405		T2	409		T4	31
valid_sources[0x48]	345765	1			T1	432		T2	396		T4	42
valid_sources[0x49]	249350	1			T1	378		T2	445		T4	52
valid_sources[0x4a]	294865	1			T1	474		T2	360		T4	38
valid_sources[0x4b]	261339	1			T1	359		T2	371		T4	56
valid_sources[0x4c]	261993	1			T1	354		T2	446		T4	44
valid_sources[0x4d]	261012	1			T1	414		T2	417		T4	38
valid_sources[0x4e]	278636	1			T1	399		T2	417		T4	36
valid_sources[0x4f]	262116	1			T1	390		T2	459		T4	27
valid_sources[0x50]	262436	1			T1	412		T2	374		T4	53
valid_sources[0x51]	260084	1			T1	378		T2	444		T4	37
valid_sources[0x52]	256733	1			T1	426		T2	420		T4	36
valid_sources[0x53]	265111	1			T1	368		T2	479		T4	39
valid_sources[0x54]	275070	1			T1	389		T2	451		T4	31
valid_sources[0x55]	1274932	1			T1	420		T2	481		T4	46
valid_sources[0x56]	301664	1			T1	396		T2	413		T4	27
valid_sources[0x57]	253599	1			T1	410		T2	482		T4	31
valid_sources[0x58]	713283	1			T1	390		T2	366		T4	33
valid_sources[0x59]	253193	1			T1	435		T2	423		T4	32
valid_sources[0x5a]	258728	1			T1	435		T2	468		T4	25
valid_sources[0x5b]	257624	1			T1	396		T2	446		T4	42
valid_sources[0x5c]	254375	1			T1	414		T2	461		T4	28
valid_sources[0x5d]	291454	1			T1	386		T2	432		T4	40
valid_sources[0x5e]	257582	1			T1	395		T2	452		T4	43
valid_sources[0x5f]	258946	1			T1	393		T2	435		T4	33
valid_sources[0x60]	263943	1			T1	444		T2	460		T4	50
valid_sources[0x61]	514818	1			T1	351		T2	469		T4	37
valid_sources[0x62]	262359	1			T1	452		T2	431		T4	34
valid_sources[0x63]	261125	1			T1	388		T2	370		T4	35
valid_sources[0x64]	262398	1			T1	382		T2	411		T4	39
valid_sources[0x65]	260909	1			T1	393		T2	436		T4	36
valid_sources[0x66]	256685	1			T1	430		T2	448		T4	41
valid_sources[0x67]	269233	1			T1	424		T2	431		T4	30
valid_sources[0x68]	264646	1			T1	358		T2	425		T4	28
valid_sources[0x69]	279180	1			T1	402		T2	463		T4	31
valid_sources[0x6a]	260343	1			T1	394		T2	425		T4	31
valid_sources[0x6b]	309387	1			T1	366		T2	408		T4	32
valid_sources[0x6c]	305312	1			T1	380		T2	401		T4	33
valid_sources[0x6d]	256160	1			T1	406		T2	399		T4	32
valid_sources[0x6e]	255122	1			T1	378		T2	434		T4	48
valid_sources[0x6f]	250560	1			T1	402		T2	452		T4	36
valid_sources[0x70]	256810	1			T1	413		T2	412		T4	35
valid_sources[0x71]	319413	1			T1	473		T2	430		T4	43
valid_sources[0x72]	409887	1			T1	364		T2	456		T4	40
valid_sources[0x73]	474304	1			T1	397		T2	460		T4	46
valid_sources[0x74]	306878	1			T1	418		T2	411		T4	39
valid_sources[0x75]	271089	1			T1	479		T2	443		T4	39
valid_sources[0x76]	315922	1			T1	401		T2	440		T4	43
valid_sources[0x77]	331650	1			T1	359		T2	415		T4	32
valid_sources[0x78]	252731	1			T1	360		T2	454		T4	41
valid_sources[0x79]	267810	1			T1	406		T2	418		T4	38
valid_sources[0x7a]	297737	1			T1	355		T2	466		T4	42
valid_sources[0x7b]	260206	1			T1	421		T2	467		T4	33
valid_sources[0x7c]	259811	1			T1	411		T2	478		T4	35
valid_sources[0x7d]	252252	1			T1	365		T2	476		T4	35
valid_sources[0x7e]	267224	1			T1	379		T2	448		T4	31
valid_sources[0x7f]	254030	1			T1	407		T2	402		T4	26
valid_sources[0x80]	266674	1			T1	464		T2	397		T4	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21137523

1

T1

26096

T2

26304

T3

2004

values[0x0]

all_enables

biggest_size

12161570

1

T1

11123

T2

13197

T3

831

values[0x1]

all_enables

biggest_size

10451894

1

T1

9070

T2

10989

T3

705