Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50483245

1

T1

57898

T2

58758

T3

4356

full_word

44048146

1

T1

46289

T2

50490

T3

3540

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	94530991	1			T1	104187		T2	109248		T3	7896
auto[TlIntgErrCmd]	138	1			T73	11		T74	8		T75	4
auto[TlIntgErrData]	131	1			T73	9		T74	7		T75	2
auto[TlIntgErrBoth]	131	1			T73	10		T74	5		T75	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44227698

1

T1

52372

T2

52637

T3

3981

auto[1]

50303693

1

T1

51815

T2

56611

T3

3915

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22972961	1			T1	26276		T2	26333		T3	1977
auto[TlIntgErrNone]	partial	auto[1]	27509909	1			T1	31622		T2	32425		T3	2379
auto[TlIntgErrNone]	full_word	auto[0]	21254546	1			T1	26096		T2	26304		T3	2004
auto[TlIntgErrNone]	full_word	auto[1]	22793575	1			T1	20193		T2	24186		T3	1536
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T73	6		T74	3		T75	4
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T73	5		T74	5		T115	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T119	1		T120	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T116	1		T122	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T73	2		T74	3		T75	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T73	7		T74	3		T115	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T74	1		T123	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T117	1		T121	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T73	3		T74	3		T75	1
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T73	7		T74	2		T75	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T116	1		T124	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T115	1		T125	1		-	-