Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	482057490	2600117	0	0
intr_enable_rd_A	482057490	4349	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482057490	2600117	0	0
T7	135968	0	0	0
T8	114542	0	0	0
T10	412255	55188	0	0
T11	0	533298	0	0
T12	0	70394	0	0
T16	0	77788	0	0
T17	0	150335	0	0
T21	316389	0	0	0
T23	0	430272	0	0
T24	0	49126	0	0
T25	0	362134	0	0
T29	0	64406	0	0
T60	116348	0	0	0
T69	238969	0	0	0
T70	258545	0	0	0
T71	166986	0	0	0
T72	492462	0	0	0
T77	0	221751	0	0
T78	6612	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482057490	4349	0	0
T7	135968	0	0	0
T8	114542	0	0	0
T10	412255	34	0	0
T16	0	86	0	0
T17	0	244	0	0
T21	316389	0	0	0
T60	116348	0	0	0
T69	238969	0	0	0
T70	258545	0	0	0
T71	166986	0	0	0
T72	492462	0	0	0
T76	0	11	0	0
T78	6612	0	0	0
T79	0	20	0	0
T80	0	28	0	0
T81	0	29	0	0
T82	0	44	0	0
T83	0	53	0	0
T84	0	8	0	0