Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48315305

1

T1

2802

T2

5485

T3

15296

full_word

42822208

1

T1

2297

T2

5932

T3

29525

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91137153	1			T1	5099		T2	11417		T3	44821
auto[TlIntgErrCmd]	108	1			T67	9		T68	2		T69	2
auto[TlIntgErrData]	121	1			T67	4		T68	3		T69	4
auto[TlIntgErrBoth]	131	1			T67	7		T68	5		T69	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42812454

1

T1

2546

T2

5916

T3

19083

auto[1]

48325059

1

T1

2553

T2

5501

T3

25738

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22138487	1			T1	1259		T2	3014		T3	11683
auto[TlIntgErrNone]	partial	auto[1]	26176477	1			T1	1543		T2	2471		T3	3613
auto[TlIntgErrNone]	full_word	auto[0]	20673811	1			T1	1287		T2	2902		T3	7400
auto[TlIntgErrNone]	full_word	auto[1]	22148378	1			T1	1010		T2	3030		T3	22125
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T67	4		T68	2		T69	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T67	5		T133	5		T134	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T133	1		T135	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T133	1		T136	1		-	-
auto[TlIntgErrData]	partial	auto[0]	56	1			T67	1		T68	1		T69	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T67	3		T68	2		T69	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T133	1		T137	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T134	1		T136	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T67	5		T68	1		T69	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T67	2		T68	4		T69	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T139	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T133	1		T137	1		T138	1